JPH06196586A - Manufacture of multilayer hybrid - Google Patents

Manufacture of multilayer hybrid

Info

Publication number
JPH06196586A
JPH06196586A JP5247685A JP24768593A JPH06196586A JP H06196586 A JPH06196586 A JP H06196586A JP 5247685 A JP5247685 A JP 5247685A JP 24768593 A JP24768593 A JP 24768593A JP H06196586 A JPH06196586 A JP H06196586A
Authority
JP
Japan
Prior art keywords
ceramic plate
pile
ceramic
green sheet
dielectric constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5247685A
Other languages
Japanese (ja)
Inventor
Ulrich Goebel
ゲーベル ウルリッヒ
Walter Roethlingshoefer
レートリングスヘーファー ヴァルター
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of JPH06196586A publication Critical patent/JPH06196586A/en
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/50—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials
    • C04B41/51—Metallising, e.g. infiltration of sintered ceramic preforms with molten metal
    • C04B41/5194—Metallisation of multilayered ceramics, e.g. for the fabrication of multilayer ceramic capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
    • C04B2111/00474—Uses not provided for elsewhere in C04B2111/00
    • C04B2111/00844—Uses not provided for elsewhere in C04B2111/00 for electronic applications
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09672—Superposed layout, i.e. in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Organic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE: To make feasible assembling two materials making notable difference in dielectric constant unable to be assembled together in the case of using green sheets, only by a method wherein ceramic made of a material in large dielectric constant is arranged to be sintered. CONSTITUTION: A pile 10 made of four pieces of green sheets 1 and a ceramic sheet 2 is displayed in a separated state as shown in the Fig. The sheets 1 are provided with conductor paths 3 and connecting parts 4 while the ceramic sheet 2 is provided with the connecting parts 4. Furthermore, the green sheets 1 positioned immediately above and below the ceramic sheet 2 are provided with a capacitor sheet 5. At least one ceramic sheet 2 made of an especially large dielectric constant is to be arranged ion the pile 10. Through these procesures, the large capacitance can be realized in the capacitor while improving the quality of the hybrid.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は，グリーンシートに導体
路及び接続部を設け，接続部によって導体路の間に電気
的接続が生ぜしめられるように，グリーンシートを重ね
合わせてパイルにする形式の多層ハイブリッドの製法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a type in which a green sheet is provided with a conductor path and a connecting portion, and the green sheet is piled into a pile so that an electrical connection is made between the conductor paths by the connecting portion. The manufacturing method of the multilayer hybrid of.

【０００２】[0002]

【従来の技術】このような多層ハイブリッドの製法はヨ
ーロッパ特許第３４５８０９号によって既に公知であ
る。この場合導体路のための材料としてなかんずく銅及
び銀が使用される。グリーンシートのパイルの焼結温度
は１０００°Ｃよりも低い。2. Description of the Prior Art A method for producing such a multi-layer hybrid is already known from EP 345809. Copper and silver are used above all as materials for the conductor tracks. The sintering temperature of the pile of green sheets is lower than 1000 ° C.

【０００３】[0003]

【発明が解決しようとする課題】本発明の課題は，多層
ハイブリッドを製作する場合に，グリーンシートだけを
使用する場合には互いに組み合わすことのできない誘電
率に大きな差のある材料を互いに組み合わせ得るように
することである。An object of the present invention is to combine materials having a large difference in permittivity which cannot be combined with each other when only a green sheet is used in manufacturing a multi-layer hybrid. To do so.

【０００４】[0004]

【課題を解決するための手段】この課題を解決するため
に，本発明の構成では，最初に述べた形式の多層ハイブ
リッドの製法において，大きな誘電率を有する材料から
成る少なくとも１つのセラミック板をパイル内に配置す
るようにした。In order to solve this problem, in the method according to the invention, at least one ceramic plate made of a material having a large dielectric constant is piled up in the method for producing a multilayer hybrid of the type mentioned at the beginning. I decided to place it inside.

【０００５】[0005]

【発明の効果】この構成によって本発明の課題が解決さ
れ，多層ハイブリッドの製作費が安価になり，品質が改
善される。With this configuration, the problems of the present invention are solved, the manufacturing cost of the multilayer hybrid is reduced, and the quality is improved.

【０００６】請求項２以下に記載した手段によって，請
求項１の製法を更に改善することが可能である。セラミ
ック板は別のグリーンシートを焼結することによって，
特に簡単に製作することができる。この場合焼結温度を
１１００°Ｃよりも高くすると，特に誘電率の大きい材
料を気孔のないセラミック板に焼結することができる。
パイルの焼結温度を１０００°Ｃよりも低くすると，特
にわずかな誘電率の材料を使用することができ，したが
って多層ハイブリッドの導電特性が特に有利になる。更
にこのように低い焼結温度は特に低オームの銅又は銀の
使用を可能にする。多層ハイブリッド内にコンデンサを
構成するために，特に誘電率の大きいセラミック板を使
用すると，表面に取り付けられる著しく高価な部品によ
ってしか達成し得ないような大きなコンデンサ容量を実
現することができる。この場合セラミック板を特に薄く
構成すると，特に大きな容量値を達成することができ
る。[0006] The manufacturing method of claim 1 can be further improved by the means described in claim 2 and thereafter. The ceramic plate is made by sintering another green sheet.
It can be manufactured particularly easily. In this case, if the sintering temperature is higher than 1100 ° C., a material having a particularly large dielectric constant can be sintered into a ceramic plate having no pores.
Lowering the sintering temperature of the pile below 1000 ° C. makes it possible to use materials with a particularly low dielectric constant, thus making the conductive properties of the multilayer hybrid particularly advantageous. Furthermore, such low sintering temperatures allow the use of particularly low ohmic copper or silver. The use of particularly high-dielectric-constant ceramic plates for constructing capacitors in a multi-layer hybrid makes it possible to achieve large capacitor capacities which can only be achieved by extremely expensive components mounted on the surface. In this case, if the ceramic plate is made particularly thin, a particularly large capacitance value can be achieved.

【０００７】[0007]

【実施例】以下においては図１〜図３に示した本発明の
実施例に基づいて本発明の構成を具体的に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be specifically described below based on the embodiments of the present invention shown in FIGS.

【０００８】図１においては，４つのグリーンシート１
及び１つのセラミック板２から成るパイル１０が引き離
した状態で示されている。グリーンシート１は導体路３
及び接続部４を備えている。セラミック板２は接続部４
を備えている。更に，セラミック板２のすぐ上下に位置
するグリーンシート１はコンデンサ板５を備えている。In FIG. 1, four green sheets 1
And a pile 10 of one ceramic plate 2 is shown in a pulled apart state. Green sheet 1 is conductor path 3
And a connecting portion 4. The ceramic plate 2 is the connection part 4
Is equipped with. Further, the green sheet 1 located immediately above and below the ceramic plate 2 has a capacitor plate 5.

【０００９】グリーンシート１はセラミック粉末と，無
機バインダと，有機バインダとから成っている。焼結の
際にグリーンシート１は１０００°Ｃよりも低い温度に
加熱される。焼結の最初の段階では，有機バインダ，一
般的にはプラスチック，が完全に燃焼せしめられる。焼
結過程が進むと，セラミック粉末，例えばアルミナ，及
び無機バインダ，一般にガラス，がセラミック板に焼結
される。The green sheet 1 is composed of ceramic powder, an inorganic binder and an organic binder. During sintering, the green sheet 1 is heated to a temperature lower than 1000 ° C. In the first stage of sintering, the organic binder, typically plastic, is completely burned. As the sintering process proceeds, ceramic powder, such as alumina, and an inorganic binder, typically glass, are sintered into a ceramic plate.

【００１０】接続部４は一般的に，生の状態のグリーン
シート１に例えば打ち抜きによって孔を形成することに
よって作られる。そしてこのグリーンシート１の孔内に
金属ペーストを満たすのである。このような金属ペース
トは，グリーンシート１上に導体路３のための構造体を
形成するためにも利用される。この場合金属ペーストは
スクリーン印刷される。金属ペーストは金属粉末と，無
機バインダと，有機ペーストとから成っている。焼結過
程の際に有機ペーストは完全に燃焼せしめられ，金属粉
末と無機バインダとは金属の導体路３又は接続部４を形
成する。The connections 4 are generally made by forming holes in the green sheet 1 in the green state, for example by punching. The holes in the green sheet 1 are filled with the metal paste. Such a metal paste is also used to form a structure for the conductor track 3 on the green sheet 1. In this case, the metal paste is screen printed. The metal paste is composed of metal powder, an inorganic binder, and an organic paste. During the sintering process, the organic paste is completely burned, and the metal powder and the inorganic binder form the metal conductor paths 3 or the connecting portions 4.

【００１１】図２においては，図１のパイル１０を焼結
して製作した多層ハイブリッド７が示されている。この
多層ハイブリッド７は４つのセラミック板１と１つのセ
ラミック板２とから構成されている。多層ハイブリッド
７の上面には別の部品としてシリコンチップ８が取り付
けられている。このシリコンチップ８は結合線９によっ
て多層ハイブリッドの導体路３に接続されている。更に
多層ハイブリッド７は支持体６上に取り付けられてい
る。コンデンサ板５によってコンデンサが構成されてい
る。セラミック板の高い誘電率によって，このコンデン
サの電気容量は特に大きい。FIG. 2 shows a multilayer hybrid 7 produced by sintering the pile 10 of FIG. The multilayer hybrid 7 is composed of four ceramic plates 1 and one ceramic plate 2. A silicon chip 8 is attached to the upper surface of the multilayer hybrid 7 as another component. This silicon chip 8 is connected to the conductor line 3 of the multi-layer hybrid by a connecting line 9. Furthermore, the multilayer hybrid 7 is mounted on the support 6. The capacitor plate 5 constitutes a capacitor. Due to the high dielectric constant of the ceramic plate, the capacitance of this capacitor is particularly large.

【００１２】導体路のために金属ペーストを印刷され，
接続部のために孔に金属ペーストを満たされているグリ
ーンシートを焼結することによって多層ハイブリッドを
製作する場合，グリーンシートのための材料と金属ペー
ストのための材料とを互いに適合させておかなければな
らない。この場合，１０００°Ｃよりも低い焼結温度が
特に好ましい。なぜならこの温度範囲においては，特に
安価で導電性のよい材料，例えば銅又は銀を金属ペース
トのために使用できるからである。１１００°Ｃよりも
高い焼結温度は一般に金属ペーストのためにタングステ
ンを使用することを必要とする。しかしながらタングス
テンは導電性が比較的にわずかで，しかも高価である。
１０００°Ｃよりも低い焼結温度においては，セラミッ
クシートはガラス分が大きい。したがってこのようなセ
ラミックシートは誘電率が低い。高い誘電率を達成する
ことのできる充てん材料例えばチタン酸バリウムは１０
００°Ｃよりも低い焼結温度ではセラミックシート内に
使用しにくい。すなわち，１０００°Ｃよりも低い焼結
温度では，このような材料を使用して，気孔のない高品
質の多層ハイブリッドを製作することはできない。高い
誘電率を有している材料は一般に１０００°Ｃよりも高
い焼結温度を必要とする。しかしながらこのような焼結
温度では，１０００°Ｃよりも低い温度で焼結可能なメ
タライズの利点を使用することができない。本発明によ
る製法は両方の利点を多層ハイブリッドにおいて生ぜし
めるのである。すなわち，まず大きな誘電率を有してい
るセラミック板２を製作する。このセラミック板２はも
はや生の状態ではなく，したがって１０００°Ｃよりも
低い温度での焼結過程によってほとんど変化しない。こ
のセラミック板２は１０００°Ｃよりも低い焼結温度を
必要とするグリーンシート１及び金属ペーストと組み合
わされるのである。したがって本発明による製法は，１
０００°Ｃよりも低い温度で焼結される多層ハイブリッ
ドの利点と，１０００°Ｃよりも高い焼結温度を必要と
するセラミック板の利点とを組み合わせるのである。Printed with a metal paste for the conductor tracks,
When making a multi-layer hybrid by sintering a green sheet whose holes are filled with a metal paste for the connection, the material for the green sheet and the material for the metal paste must be compatible with each other. I have to. In this case, sintering temperatures below 1000 ° C. are particularly preferred. This is because, in this temperature range, particularly cheap and electrically conductive materials, such as copper or silver, can be used for the metal paste. Sintering temperatures higher than 1100 ° C generally require the use of tungsten for the metal paste. However, tungsten has a relatively low conductivity and is expensive.
At sintering temperatures below 1000 ° C, the ceramic sheet has a high glass content. Therefore, such a ceramic sheet has a low dielectric constant. A filling material that can achieve a high dielectric constant, such as barium titanate, is 10
It is difficult to use in a ceramic sheet at a sintering temperature lower than 00 ° C. That is, at sintering temperatures below 1000 ° C., it is not possible to use these materials to fabricate high quality multilayer hybrids without porosity. Materials with high dielectric constants generally require sintering temperatures above 1000 ° C. However, at such sintering temperatures, the advantages of metallization which can be sintered at temperatures below 1000 ° C. cannot be used. The method according to the invention gives both advantages in a multi-layer hybrid. That is, first, the ceramic plate 2 having a large dielectric constant is manufactured. This ceramic plate 2 is no longer in its green state and therefore hardly changes during the sintering process at temperatures below 1000 ° C. This ceramic plate 2 is combined with the green sheet 1 and the metal paste which require a sintering temperature lower than 1000 ° C. Therefore, the manufacturing method according to the present invention is
It combines the advantages of multilayer hybrids that are sintered at temperatures below 000 ° C with the advantages of ceramic plates that require sintering temperatures above 1000 ° C.

【００１３】図３には接続部４とコンデンサ板５とを有
するセラミック板２が示されている。このセラミック板
２を製作するために，接続部４のための孔を有するグリ
ーンシートを焼結する。セラミック板２のためには，高
い誘電率を有している材料が使用されるので，この場合
１０００°Ｃよりも大きい焼結温度が必要である。他面
において，接続部４のための孔を焼結の後で，例えばレ
ーザーによって形成することも可能である。次いでスク
リーン印刷によってコンデンサ板５及び接続部４のため
の金属ペーストを取り付ける。しかしながらこの場合，
金属ペーストは１０００°Ｃよりも低い温度で焼結する
ものを使用する。図１のセラミック板２と異なって，図
３のセラミック板２においては，コンデンサ板５は直接
にセラミック板２上に取り付けられる。多層ハイブリッ
ド内にコンデンサを構成することは，これら両方のやり
方によることができる。重要なことは，図３に示したや
り方の場合，コンデンサ板５のための金属ペーストが低
い温度範囲で焼結可能なことである。FIG. 3 shows a ceramic plate 2 having a connecting part 4 and a capacitor plate 5. In order to produce this ceramic plate 2, a green sheet having holes for the connecting parts 4 is sintered. Since a material having a high dielectric constant is used for the ceramic plate 2, a sintering temperature of more than 1000 ° C. is necessary in this case. On the other hand, it is also possible to form the holes for the connections 4 after sintering, for example by means of a laser. Then, a metal paste for the capacitor plate 5 and the connecting portion 4 is attached by screen printing. However, in this case,
The metal paste used is one that sinters at a temperature lower than 1000 ° C. Unlike the ceramic plate 2 of FIG. 1, in the ceramic plate 2 of FIG. 3, the capacitor plate 5 is directly mounted on the ceramic plate 2. Constructing capacitors in a multilayer hybrid can be by both of these approaches. Importantly, in the case of the method shown in FIG. 3, the metal paste for the capacitor plate 5 can be sintered in the low temperature range.

【図面の簡単な説明】[Brief description of drawings]

【図１】グリーンシートと１つのセラミック板とのパイ
ルを示した図である。FIG. 1 is a diagram showing a pile of a green sheet and one ceramic plate.

【図２】図１のパイルから製作された多層ハイブリッド
を示した図である。2 shows a multi-layer hybrid made from the pile of FIG.

【図３】別の実施例のセラミック板を示した図である。FIG. 3 is a view showing a ceramic plate of another example.

【符号の説明】[Explanation of symbols]

１ グリーンシート又はセラミックシート， ２ セラ
ミック板， ３ 導体路， ４ 接続部， ５ コンデ
ンサ板， ６ 支持体， ７ 多層ハイブリッド， ８
シリコンチップ， ９ 結合線， １０ パイル1 green sheet or ceramic sheet, 2 ceramic plate, 3 conductor paths, 4 connection parts, 5 capacitor plate, 6 support, 7 multilayer hybrid, 8
Silicon chip, 9 bond wires, 10 piles

───────────────────────────────────────────────────── フロントページの続き (72)発明者 ヴァルター レートリングスヘーファー ドイツ連邦共和国 ロイトリンゲン ケー ニッヒシュトレッスレ 129 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Walther Leedlingschafer Germany, Reutlingen Königstraßle 129

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 グリーンシート（１）に導体路（３）及
び接続部（４）を設け，接続部（４）によって導体路
（３）の間に電気的接続が生ぜしめられるように，グリ
ーンシート（１）を重ね合わせてパイル（１０）にする
形式の多層ハイブリッドの製法において，大きな誘電率
を有する材料から成る少なくとも１つのセラミック板
（２）をパイル（１０）内に配置することを特徴とする
多層ハイブリッドの製法。1. A green sheet (1) is provided with a conductor path (3) and a connecting portion (4), so that the connecting portion (4) makes an electrical connection between the conductor paths (3). A method for producing a multi-layer hybrid in which sheets (1) are piled up into a pile (10), characterized in that at least one ceramic plate (2) made of a material having a large dielectric constant is arranged in the pile (10). Multi-layer hybrid manufacturing method. 【請求項２】 セラミック板（２）を別のグリーンシー
トの焼結によって製作し，別のグリーンシートの材料
を，焼結温度が１０００°Ｃよりも高いように選択する
請求項１記載の製法。2. A method according to claim 1, wherein the ceramic plate (2) is produced by sintering another green sheet and the material of the other green sheet is selected so that the sintering temperature is higher than 1000 ° C. . 【請求項３】 パイル（１０）の焼結温度を１０００°
Ｃよりも低くする請求項２記載の製法。3. The sintering temperature of the pile (10) is 1000 °.
The method according to claim 2, wherein the temperature is lower than C. 【請求項４】 導体路（３）及び接続部（４）の材料と
して銅又は銀を選択する請求項３記載の製法。4. The method according to claim 3, wherein copper or silver is selected as a material for the conductor track (3) and the connecting part (4). 【請求項５】 セラミック板（２）に接続部（４）を設
ける請求項１から請求項４までのいずれか１項に記載の
製法。5. The manufacturing method according to claim 1, wherein the ceramic plate (2) is provided with a connecting portion (4). 【請求項６】 多層ハイブリッドに少なくとも１つのコ
ンデンサを設けるために，セラミック板（２）の両側に
コンデンサ板（５）を設けてパイル（１０）内に配置す
る請求項１から請求項５まどのいずれか１項に記載の製
法。6. In order to provide at least one capacitor in a multilayer hybrid, capacitor plates (5) are provided on both sides of the ceramic plate (2) and are arranged in a pile (10). The method according to any one of items. 【請求項７】 セラミック板（２）の厚さをセラミック
シート（１）の厚さよりも薄く選択する請求項１から請
求項６までのいずれか１項に記載の製法。7. The method according to claim 1, wherein the thickness of the ceramic plate (2) is selected to be smaller than the thickness of the ceramic sheet (1).
JP5247685A 1992-10-05 1993-10-04 Manufacture of multilayer hybrid Pending JPH06196586A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4233403A DE4233403C2 (en) 1992-10-05 1992-10-05 Process for the production of multi-layer hybrids
DE4233403.9 1992-10-05

Publications (1)

Publication Number Publication Date
JPH06196586A true JPH06196586A (en) 1994-07-15

Family

ID=6469644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5247685A Pending JPH06196586A (en) 1992-10-05 1993-10-04 Manufacture of multilayer hybrid

Country Status (2)

Country Link
JP (1) JPH06196586A (en)
DE (1) DE4233403C2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0857961A2 (en) 1997-02-05 1998-08-12 Muto Pure Chemicals Company Ltd. Sample preparing apparatus used with preparation disk with filter
KR100711008B1 (en) * 1999-12-15 2007-04-24 고등기술연구원연구조합 A method for facturing a composite ceramic module package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5601672A (en) * 1994-11-01 1997-02-11 International Business Machines Corporation Method for making ceramic substrates from thin and thick ceramic greensheets
JP3451868B2 (en) * 1997-01-17 2003-09-29 株式会社デンソー Manufacturing method of ceramic laminated substrate
WO2000004577A1 (en) * 1998-07-15 2000-01-27 Siemens Aktiengesellschaft Method for producing a ceramic body having an integrated passive electronic component, such a body and use of same
JP3666321B2 (en) * 1999-10-21 2005-06-29 株式会社村田製作所 Multilayer ceramic substrate and manufacturing method thereof
US20060162844A1 (en) 2005-01-26 2006-07-27 Needes Christopher R Multi-component LTCC substrate with a core of high dielectric constant ceramic material and processes for the development thereof
DE102014208526B4 (en) * 2014-05-07 2020-01-30 Infineon Technologies Ag ELECTRONICS ASSEMBLY

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0635462Y2 (en) * 1988-08-11 1994-09-14 株式会社村田製作所 Multilayer capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0857961A2 (en) 1997-02-05 1998-08-12 Muto Pure Chemicals Company Ltd. Sample preparing apparatus used with preparation disk with filter
KR100711008B1 (en) * 1999-12-15 2007-04-24 고등기술연구원연구조합 A method for facturing a composite ceramic module package

Also Published As

Publication number Publication date
DE4233403C2 (en) 2003-08-28
DE4233403A1 (en) 1994-04-07

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