JPH06187167A - Interruption control circuit and interruption control system - Google Patents

Abstract

PURPOSE:To provide an interruption control circuit and an interruption control system made possible of suppressing the number of input terminals for interruption use to the minimum required and coping with more interruption requests. CONSTITUTION:The interruption request signals 4a-4f of external circuits 3a-3f are connected so as to be imparted to the registers 5a-5f of a register circuit 50 and also connected so as to be imparted to an OR circuit 6. The register circuit 50 is readably and writably connected with a CPU 1 and the OR circuit 6 outputs the OR signals 7 of the interruption request signals 4a-4f to the input terminal 2a for the interruption use. Since interruption processings for the plural external circuits can be executed by providing just one input terminal for the interruption use, a lot of the interruption requests can be coped with while the number of the input terminals for the interruption is suppressed to the minimum required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control circuit and an interrupt control method for controlling interrupt processing in response to an interrupt request from an external circuit.

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram showing a configuration of a conventional interrupt control circuit. As shown in the figure, the interrupt request signals 4a to 4c from the plurality of external circuits 3a to 3c, respectively.
4c is provided to the interrupt input terminals 2a to 2c of the CPU 1. Although not shown,
The CPU 1 is connected to the external circuits 3a to 3c so that the interrupt processing for the external circuits 3a to 3c can be executed.

Interrupt request signal 4 of external circuits 3a-3c
a to 4c are connected to C via the interrupt input terminals 2a to 2c.
When assigned to PU1, the CPU1 causes the interrupt request signal 4
The interrupt processing is performed on the external circuit 3 that has received the signal.

[0004]

The conventional interrupt control circuit is configured as described above, and one interrupt input terminal 2 is assigned to one interrupt request. More interrupts than the number of input terminals 2 could not be processed.

On the other hand, the CPU 1 is generally restricted in the number of terminals in terms of the chip size, package size, and price of the LSI, and it is difficult to increase the number of terminals. Therefore, it is not realistic to increase the number of interrupt input terminals in order to handle a large number of interrupt processes.

The present invention has been made in order to solve the above problems, and provides an interrupt control circuit and an interrupt control system in which the number of interrupt input terminals is kept to a necessary minimum and more interrupt requests can be handled. With the goal.

[0007]

An interrupt control circuit according to a first aspect of the present invention has an interrupt input terminal for fetching a CPU input interrupt request signal and is capable of executing interrupt processing for each of a plurality of external circuits. CPU
A storage unit provided corresponding to the plurality of external circuits and configured to store a plurality of interrupt request signals from the plurality of external circuits as stored data; and a plurality of the interrupt request signals, When at least one of the plurality of interrupt request signals indicates an interrupt request, the CPU input interrupt request signal indicating the interrupt request is output to the interrupt input terminal, the interrupt request control means is provided, and the CPU stores the memory. The stored data is readable and writable to each of the plurality of registers of the means.

An interrupt control system according to a second aspect of the present invention uses the interrupt control circuit according to the first aspect,
A control method when the CPU input interrupt request signal indicates an interrupt request, wherein: (a) data stored in the plurality of registers of the storage unit is read and an interrupt request is made among the plurality of external circuits. Specifying an external circuit as an interrupt request external circuit, (b) performing an interrupt process for the interrupt request external circuit, and (c) an interrupt request instruction of the interrupt request signal of the interrupt request external circuit. And clearing the interrupt request instruction of the stored data of the register corresponding to the interrupt request external circuit among the plurality of registers.

Preferably, as in the interrupt control method according to claim 3, priorities are set in advance for interrupt processing for the plurality of external circuits, and the step (a) is performed.
Performs the specifying process of the interrupt request external circuit in the order based on the priority order.

Preferably, in the interrupt control method according to the fourth aspect, the step (a) is performed based on a predetermined specific processing order from an external circuit next to the interrupt request external circuit specified last time. , Interrupt request Performs specific processing of the external circuit.

An interrupt control system according to a fifth aspect of the present invention uses the interrupt control circuit according to the first aspect,
When the CPU input interrupt request signal indicates an interrupt request, a plurality of interrupt processing tasks that perform actual interrupt processing for each of the plurality of external circuits and an interrupt handler that controls the execution of the interrupt processing tasks are independently executed. In the method, the interrupt handler reads (a) the data stored in the plurality of registers of the storage unit, and of the plurality of external circuits, an external circuit that has made an interrupt request is used as an interrupt request external circuit. A step of specifying, (b) of the plurality of interrupt processing tasks, a step of enabling an interrupt processing task for the interrupt request external circuit, and (c) the interrupt request signal of the interrupt request external circuit. Clears the interrupt request instruction, and selects the above-mentioned interrupt request among the plurality of registers. A step of clearing an interrupt request instruction of the stored data of the register corresponding to the circuit, and the interrupt processing task for the interrupt request external circuit executes an interrupt process for the interrupt request external circuit when the task becomes executable. To do.

Preferably, as in the interrupt control method according to claim 6, priorities are set in advance for interrupt processing for external circuits, and in the step (a), the interrupt processing is performed in an order based on the priority. Performs specified processing of the requested external circuit.

Preferably, as in the interrupt control method according to claim 7, when the plurality of interrupt processing tasks have priorities set in advance, and two or more interrupt processing tasks are simultaneously ready for execution. , Execute interrupt processing tasks in the order based on the priority.

According to another aspect of the present invention, there is provided an interrupt control circuit for transmitting / receiving input / output data to / from a general-purpose input / output circuit and an interrupt input terminal for fetching a CPU input interrupt request signal. A plurality of general-purpose input / output ports to which a plurality of interrupt request signals are given, capable of executing interrupt processing for each of the plurality of external circuits, and a plurality of interrupts that receive the plurality of interrupt request signals. At least one of the request signals
And an interrupt request control means for outputting the CPU input interrupt request signal instructing an interrupt request to the interrupt input terminal.

An interrupt control system according to a ninth aspect of the present invention uses the interrupt control circuit according to the eighth aspect.
A control method when the CPU input interrupt request signal indicates an interrupt request, comprising: (a) reading the signal levels of the plurality of interrupt request signals provided to the plurality of general-purpose input / output ports, Among the external circuits, a step of specifying the external circuit that has made an interrupt request as an interrupt request external circuit; (b) a step of performing an interrupt process for the interrupt request external circuit; and (c) the interrupt request external circuit. Clearing the interrupt request instruction of the interrupt request signal.

Preferably, as in the interrupt control method according to claim 10, priorities are set in advance for interrupt processing for the plurality of external circuits, and the step
(a) performs the process of identifying the interrupt request external circuit in the order based on the priority.

Preferably, in the interrupt control method according to the eleventh aspect, the step (a) is performed from an external circuit arranged next to the interrupt request external circuit specified last time based on a predetermined specific processing order. , Interrupt request Performs specific processing of the external circuit.

An interrupt control system according to a twelfth aspect of the present invention uses the interrupt control circuit according to the eighth aspect, and when the CPU input interrupt request signal indicates an interrupt request, an actual operation for each of the plurality of external circuits is performed. A method of independently executing a plurality of interrupt processing tasks for performing the interrupt processing and an interrupt handler for controlling the execution of the interrupt processing tasks, wherein the interrupt handler is (a) Reading the signal levels of the plurality of interrupt request signals that are given, and specifying the external circuit that has made an interrupt request among the plurality of external circuits as an interrupt request external circuit; and (b) the plurality of interrupt processes. Among the tasks, a step of enabling the interrupt processing task for the interrupt request external circuit, (c) clearing an interrupt request instruction of the interrupt request signal of the interrupt request external circuit, the interrupt processing task for the interrupt request external circuit, to the interrupt request external circuit when the ready state Execute interrupt processing.

Preferably, as in the interrupt control method according to the thirteenth aspect, priorities are set in advance for interrupt processing for external circuits, and in the step (a), the interrupt processing is performed in an order based on the priority order. Performs specified processing of the requested external circuit.

Preferably, as in the interrupt control method according to claim 14, when the plurality of interrupt processing tasks have priorities set in advance, and two or more interrupt processing tasks are simultaneously ready for execution. , Execute interrupt processing tasks in the order based on the priority.

[0021]

Since the CPU of the interrupt control circuit according to the first aspect of the present invention is connected to each of the plurality of registers of the storage means so that the stored data can be read and written, the CPU of the plurality of external circuits is connected via the storage means. It is possible to detect whether the interrupt request signal indicates an interrupt request.

Therefore, when the CPU input interrupt request signal indicates an interrupt request as in the interrupt control method according to the second aspect of the present invention, the data stored in the plurality of registers of the storage means are read out to select one of the plurality of external circuits. The external circuit that has issued the interrupt request can be specified as the interrupt request external circuit.

It should be noted that the input / output terminals required for connecting to the storage means in a readable and writable manner can share the input / output terminals for the external storage device which should be originally connected.
There is no need to newly install it.

Further, as in the interrupt control method according to the fifth aspect, a plurality of interrupt processing tasks that perform actual interrupt processing for each of the plurality of external circuits and an interrupt handler that controls the execution of the interrupt processing tasks are independently provided. You can also do it.

In the CPU of the interrupt control circuit according to claim 8 of the present invention, since a plurality of interrupt request signals from a plurality of external circuits are given to the plurality of general-purpose input / output ports, a plurality of general-purpose input / output ports are used. It is possible to detect whether or not the interrupt request signals of the plurality of external circuits indicate the interrupt request.

Therefore, when the CPU input interrupt request signal indicates an interrupt request as in the interrupt control system according to the ninth aspect, the signal levels of the plurality of interrupt request signals given to the plurality of general-purpose input / output ports are set. Of the plurality of external circuits that have been read, the external circuit that has made the interrupt request can be specified as the interrupt request external circuit.

Since the general-purpose input / output port shares the port of the input / output circuit to be originally connected, it is not necessary to newly provide it.

Further, as in the interrupt control method according to the twelfth aspect, a plurality of interrupt processing tasks that perform actual interrupt processing for each of the plurality of external circuits and an interrupt handler that controls the execution of the interrupt processing tasks are independently provided. You can also do it.

[0029]

【Example】

<First Embodiment> FIG. 1 is a circuit diagram showing a configuration of an interrupt control circuit according to a first embodiment of the present invention. As shown in the figure, the external circuits 3g and 3h are connected to the interrupt input terminals 2b and 2c, respectively, and the interrupt request signal 4g and
4h is configured to be directly given to the CPU 1.

On the other hand, the interrupt request signals 4a to 4f of the external circuits 3a to 3f are transferred to the registers 5a to 5f of the register circuit 50.
It is connected so as to be given to 5f and is also connected so as to be given to the logical sum circuit 6. The external circuit 3
The interrupt request signals 4a to 4f of a to 3f are at the H level (logic "1") when the interrupt request is instructed, and are at the L level (logic "0") when the interrupt request is not instructed.
Is the signal. Although not shown in FIG. 1, CP
U1 is connected to the external circuits 3a to 3c so that interrupt processing for the external circuits 3a to 3c can be executed.

The register circuit 50 is connected via the read control terminal 11 and the write control terminal 12 of the CPU 1 so that the read control signal RD and the write control signal WR can be input, and the registers 5a to 5f of the register circuit 50 are connected.
Are connected via the data input / output terminals 13a to 13f of the CPU 1 so that data can be written and read.

The OR circuit 6 includes the interrupt request signals 4a to 4a.
The logical sum signal 7 of 4f is output to the interrupt input terminal 2a.

The read control terminal 11, the write control terminal 12, and the data input / output terminals 13a to 13f are R.
The terminals used for connection with ordinary external memories such as AM and ROM are only used for the register circuit 50, and are not newly provided for connection with the register circuit 50.

In such a configuration, the external circuits 3a ...
When any of the interrupt request signals 4a to 4f of 3f becomes the H level that instructs the interrupt request, the logical sum circuit 6 outputs the logical sum signal 7 of the H level to the interrupt input terminal 2a.
The interrupt request is issued to the CPU 1 by being assigned to the CPU 1.

FIG. 2 is a flow chart showing an interrupt processing routine when an interrupt request is issued to the CPU 1 through the interrupt input terminal 2a in the interrupt control circuit of the first embodiment.

The interrupt input terminal 2a is set to level sense for detecting the signal level of the input signal.

Referring to FIG. 2, first, in step S1,
After the read control signal RD for instructing the read is given to the register circuit 50, the data stored in the registers 5a to 5f in the register circuit 50 are transferred to the data input / output terminals 13a to 1a.
Read out via 3f.

Then, in step S2, each register 5a
If the value of the stored data of ~ 5f is detected and even one "H" is detected, it is determined that "interrupt (request) is present", the process proceeds to step S3, and if all are "L", "interrupt (request)" is issued. ) None ”, and returns from the interrupt processing routine.

In step S3, one of the external circuits 3a to 3f corresponding to the register 5 of which the stored data is "H" among the registers 5a to 5f is set to the interrupt request external source which is the interrupt generation source of the interrupt request. Specify as a circuit. Subsequently, in step S4, interrupt processing is performed on the interrupt request external circuit specified in step S3.

When the interrupt processing is completed, step S5
Then, after clearing the interrupt request signal output from the interrupt request external circuit to "L" and applying the write control signal WR for instructing writing to the register circuit 50, the registers 5a to 5a corresponding to the interrupt request external circuit are provided.
Write "L" in 5f to clear the interrupt request.

When step S5 ends, step S2
Returning to step S2, steps S2 to S5 are repeated until it is determined that there is no interrupt (request) in step S2.

When there is an interrupt request from the external circuits 3g and 3h, the interrupt processing is performed as in the conventional case.

With this configuration, one interrupt input terminal 2a can handle a plurality of interrupt requests. Therefore, the number of interrupt input terminals can be minimized to increase the number of interrupt requests. Can handle. <Second Embodiment> FIG. 3 is a circuit diagram showing the structure of an interrupt control circuit according to a second embodiment of the present invention. As shown in the figure, the external circuits 3g and 3h are connected to the interrupt input terminals 2b and 2c, respectively, and the interrupt request signal 4g and
4h is directly applied to the CPU 1.

On the other hand, the interrupt request signals 4a to 4f of the external circuits 3a to 3f are sent to the general-purpose input / output port 10a of the CPU 1.
10f, interrupt request signals 4a-4f,
It is configured to be directly applied to the CPU 1. The interrupt request signals 4a to 4f are also given to the logical sum circuit 6. The interrupt request signal 4 of the external circuits 3a to 3f
Signals a to 4f are H level signals when an interrupt request is instructed. Although not shown in FIG. 3, the CPU
1 is connected to the external circuits 3a to 3c so that the interrupt processing for the external circuits 3a to 3c can be executed.

The OR circuit 6 includes the interrupt request signals 4a to 4a.
The logical sum signal 7 of 4f is output to the interrupt input terminal 2a.

General purpose input / output ports 10a to 10f
Is a terminal shared by external input / output circuits, and is not newly provided for inputting the interrupt request signals 4a-4f of the external circuits 3a-3f.

In such a configuration, the external circuits 3a ...
When any of the interrupt request signals 4a to 4f of 3f becomes the H level that instructs the interrupt request, the logical sum circuit 6 outputs the logical sum signal 7 of the H level to the interrupt input terminal 2a.
The interrupt request is issued to the CPU 1 by being assigned to the CPU 1.

FIG. 4 is a flow chart showing an interrupt processing routine when an interrupt request is issued to the CPU 1 via the interrupt input terminal 2a in the interrupt control circuit of the first embodiment.

The interrupt input terminal 2a is set to level sense for detecting the signal level of an input signal.

Referring to FIG. 4, first, step S11.
Then, the signal levels of the general-purpose input / output ports 10a to 10f to which the interrupt request signals 4a to 4 are given are checked.

Then, in step S12, if "H" is detected from at least one signal level of the general-purpose input / output ports 10a to 10f, it is determined that "interrupt (request) is present", the process proceeds to step S13, and all are "L". "in the case of,
It judges that there is no interrupt (request) and returns from the interrupt processing routine.

In step S13, the general purpose input / output port 10
Based on the signal levels of the signals obtained from a to 10f, one of the external circuits 3a to 3f corresponding to the general-purpose input / output ports 10a to 10f whose signal level is "H" is an interrupt source. Specify as an interrupt request external circuit. Then, in step S14, step S13
Performs interrupt processing for the interrupt request external circuit specified in.

When the interrupt processing is completed, step S1
In step S13, the interrupt request signal of the interrupt request external circuit is set to "L" in step S13 to clear the interrupt request.

When step S15 ends, step S15
12, and thereafter, steps S12 to S15 are performed until it is determined in step S12 that "no interrupt (request)".
repeat.

When there is an interrupt request from the external circuits 3g and 3h, the interrupt processing is performed as in the conventional case.

With this configuration, one interrupt input terminal 2a can handle a plurality of interrupt requests. Therefore, the number of interrupt input terminals can be minimized to increase the number of interrupt requests. Can handle.

FIG. 5 is a timing chart showing a state of multiple interrupt processing at the time of executing the interrupt processing routines of the first and second embodiments shown in FIGS. 2 and 4, respectively.

As shown in the figure, at time T1, the external circuit 3a generates an "H" interrupt request signal 4a for instructing an interrupt request, and at time T2, the external circuit 3b issues an interrupt request "H". The interrupt request signal 4b of "" has been generated.

In this case, the interrupt processing is performed for the external circuit 3a that has previously received the interrupt request. And
At time T3, the interrupt request signal 4a falls to "L" at the same time when the interrupt processing for the external circuit 3a ends.

At time T3, the interrupt request signal 4b
Is "H" and the logical sum signal 7 maintains "H", the interrupt processing routine is continued, and from time T3,
An interrupt process for the external circuit 3b is performed.

Then, at time T4, at the same time as the interrupt processing for the external circuit 3b ends, the interrupt request signal 4
b is lowered to "L". As a result, the logical sum signal 7
Also falls to “L”, the interrupt processing routine ends, and the CPU 1 performs normal processing from time T4. <Third Embodiment> FIG. 6 is a flow chart showing an interrupt processing routine according to an interrupt control system according to a third embodiment of the present invention. As the interrupt control circuit, even in the configuration of the first embodiment shown in FIG. 1, the interrupt control circuit of the second embodiment shown in FIG.
The configuration of the embodiment may be used. Note that this interrupt processing routine is an interrupt processing routine when an interrupt request is made to the interrupt input terminal 2a.

First, in step S21, the interrupt source is checked. This operation is performed for the interrupt control circuit of the first embodiment by verifying the contents of the data stored in the registers 5a to 5f in the register circuit 50 (step S in FIG. 2).
1), which corresponds to the operation of verifying the signal level of the signals obtained from the general-purpose input / output ports 10a to 10f (step S11 in FIG. 4) for the interrupt control circuit of the second embodiment.

Then, in step S22, it is verified whether or not the interrupt request signal 4a is "H" indicating the interrupt request, and if it is "H", the process proceeds to step S23.
If not "H", the process proceeds to the interrupt processing routine for the external circuit 3b after step S25.

If YES is determined in step S22, the process proceeds to step S23. In step S23, an interrupt process for the external circuit 3a is performed, and step S24
Then, the interrupt request signal 4a is set to "L", and in the case of the interrupt control circuit of the first embodiment, the data stored in the register 5a is further set to "L" to clear the interrupt request.

As described above, steps S22 to S24 are an interrupt processing routine for the external circuit 3a.

Thereafter, similarly, an interrupt processing routine for the external circuit 3b (steps S25 to S27) and an interrupt processing routine for the external circuit 3c (step S28).
To S30), an interrupt processing routine for the external circuit 3d (steps S31 to S33), an interrupt processing routine for the external circuit 3e (steps S34 to S36), an interrupt processing routine for the external circuit 3f (step S).
After sequentially executing steps 37 to S39), the process returns from the interrupt process.

By executing the interrupt processing in this way, the external circuits 3a, 3b, 3c, 3d, 3e and 3 are generated.
The interrupt processing with priorities could be performed in the order of f. <Fourth Embodiment> FIG. 7 is a flow chart showing an interrupt processing routine according to an interrupt control system according to a fourth embodiment of the present invention. As the interrupt control circuit, even in the configuration of the first embodiment shown in FIG. 1, the interrupt control circuit of the second embodiment shown in FIG.
The configuration of the embodiment may be used. However, in either configuration, an interrupt execution storage means for storing the previous external circuit for executing interrupt processing is newly provided. In addition, as the specific order of the interrupt request external circuits, the external circuits 3a, 3
The order of b, 3c, 3d, 3e, 3f is preset.

The interrupt processing routine shown in FIG. 7 is an interrupt processing routine when there is an interrupt request at the interrupt input terminal 2a.

First, in step S41, the interrupt source is checked. This operation is similar to the register 5 of the register circuit 50 in the interrupt control circuit of the first embodiment.
Content verification of the stored data of a to 5f (step S of FIG. 2)
1), which corresponds to the operation of verifying the signal level of the signals obtained from the general-purpose input / output ports 10a to 10f (step S11 in FIG. 4) for the interrupt control circuit of the second embodiment.

Then, in step S42, step S4
When it is detected that at least one of the interrupt request signals 4a to 4f is "H" based on the check of the interrupt generation source of No. 1, it is determined that "interrupt (request) is present", the process proceeds to step S43, and all are "L". In the case of "(logic" 0 "), it is determined that there is no interrupt (request), and the process returns from the interrupt processing routine.

In step S43, the external circuit which previously performed the interrupt process is checked from the interrupt execution storage means.

Then, in step S44, the interrupt request of the external circuit whose order is set next to the external circuit which previously performed the interrupt process is checked. For example, when the external circuit that performed the interrupt process last time is the external circuit 3c, the interrupt request of the external circuit 3d is checked, and thereafter, in this step, the external circuits 3e, 3f, 3a, 3
Checked in the order of b and 3c.

Next, in step S45, it is verified whether or not an interrupt request signal for instructing an interrupt request is output from the external circuit to be checked. When it is determined that the interrupt request is instructed, the external circuit to be checked is recognized as the interrupt request external circuit, and the process proceeds to step S46.
If it is determined that the interrupt request is not instructed, the process returns to step S44.

In step S46, the interrupt process for the interrupt request external circuit recognized in step S45 is executed.

Then, in step S47, the interrupt request signal of the interrupt request external circuit is set to "L", and in the case of the interrupt control circuit of the first embodiment, the data stored in the register 5 corresponding to the interrupt request external circuit is further changed. Set to "L" to clear the interrupt request.

After that, the interrupt request external circuit is registered in the interrupt execution storage means as the external circuit that has previously performed the interrupt process, and the data is updated. <Fifth Embodiment> FIGS. 8 and 9 are flow charts showing an interrupt processing routine according to an interrupt control system according to a fifth embodiment of the present invention. The interrupt control circuit may have the configuration of the first embodiment shown in FIG. 1 or the configuration of the second embodiment shown in FIG. Note that this interrupt processing routine is an interrupt processing routine when an interrupt request is made to the interrupt input terminal 2a.

FIG. 8 shows the operation of the interrupt handler, and FIG. 9 shows the operation of the interrupt processing task. These operations can be performed independently of each other.

The operation of the interrupt handler will be described below with reference to FIG.

First, in step S51, the interrupt source is checked. This operation is similar to the register 5 of the register circuit 50 in the interrupt control circuit of the first embodiment.
Content verification of the stored data of a to 5f (step S of FIG. 2)
1), which corresponds to the operation of verifying the signal level of the signals obtained from the general-purpose input / output ports 10a to 10f (step S11 in FIG. 4) for the interrupt control circuit of the second embodiment.

Then, in step S52, the interrupt processing task for performing the interrupt processing on the corresponding external circuit 3 is set to the ready state (executable state) based on the interrupt request signal 4a instructing the interrupt request.

Next, in step S53, the interrupt request signal of the interrupt request external circuit is set to "L", and in the case of the interrupt control circuit of the first embodiment, the register 5 corresponding to the interrupt request external circuit is further stored. After setting the data to "L" to clear the interrupt request, the interrupt handler is terminated.

The operation of interrupt task processing will be described below with reference to FIG.

Step S61 is a waiting state, and is made ready by an instruction of the interrupt handler. When an execution instruction is given to an interrupt processing task control program called a monitor program, the process proceeds to step S62 for the first time. Then, in step S62, the corresponding external circuit 3
Execute interrupt processing for.

The interrupt task process is a process provided for each interrupt process of one external circuit 3.

As described above, in the fifth embodiment, the interrupt processing can be divided into the interrupt handler processing and the interrupt processing task and independently executed. As a result, the interrupt handler can entrust the actual interrupt processing to the interrupt processing task, so there are many interrupt sources and complicated interrupt control such as when the processing corresponding to each interrupt source is complicated. Can be performed relatively easily. <Sixth Embodiment> FIG. 10 is a flow chart showing an interrupt processing routine by an interrupt control system according to a sixth embodiment of the present invention. As an interrupt control circuit,
The configuration of the first embodiment shown in FIG. 1 or the configuration of the second embodiment shown in FIG. 3 may be used. Note that this interrupt processing routine is an interrupt processing routine when an interrupt request is made to the interrupt input terminal 2a. In addition, FIG.
8 corresponds to the processing of the interrupt handler of the fifth embodiment shown in FIG. 8, and the actual interrupt processing is performed by the interrupt processing task of the fifth embodiment shown in FIG.

First, in step S101, the interrupt source is checked. This operation is performed for the interrupt control circuit of the first embodiment by verifying the contents of the data stored in the registers 5a to 5f of the register circuit 50 (step S in FIG. 2).
This corresponds to 1) and to the interrupt control circuit of the second embodiment, it corresponds to the verification operation of the signal level obtained from the general-purpose input / output ports 10a to 10f (step S11 in FIG. 4).

Then, in step S102, it is verified whether the interrupt request signal 4f is "H" indicating an interrupt request. If "H", the process proceeds to step S103, and if not "H". The process proceeds to the interrupt processing routine for the external circuit 3e after step S105.

If YES is determined in step S102, the process proceeds to step S103. In step S103, the interrupt processing task for the external circuit 3f is set to the ready state. Then, in step S104, the interrupt request signal 4
In the case of the interrupt control circuit of the first embodiment, f is set to "L", and further, the data stored in the register 5f is set to "L" to clear the interrupt request.

Above, steps S102 to S104 are the interrupt processing routine for the external circuit 3f.

Thereafter, similarly, an interrupt processing routine for the external circuit 3e (steps S105 to S107) and an interrupt processing routine for the external circuit 3d (step S).
108 to S110), an interrupt processing routine for the external circuit 3c (steps S111 to S113), an interrupt processing routine for the external circuit 3b (step S114).
To S116) and the interrupt processing routine for the external circuit 3a (steps S117 to S119) are sequentially executed, and then the interrupt handler returns.

By executing the interrupt handler interrupt processing in this way, when the execution instructions to the interrupt processing tasks for the external circuits 3a to 3f by the monitor program have the same priority, the external circuits 3f and 3f are processed.
It is possible to perform interrupt processing with priorities in the order of e, 3d, 3c, 3b and 3a. <Seventh Embodiment> In the sixth embodiment, the priority order of the interrupt processing tasks by the monitor program is set to be the same, but an execution instruction to the interrupt processing task is arbitrarily issued regardless of the ready state setting order by the interrupt handler. Priorities can be determined.

For example, the priority order of execution instructions to the interrupt processing task by the monitor program is set to the external circuits 3a, 3
If the settings are made in the order of b, 3c, 3d, 3e, 3f, FIG.
As in the operation of the sixth embodiment shown in FIG.
Even if the ready state of the interrupt processing task is set in the order of 3e, 3d, 3c, 3b, 3a, the monitor program
The external circuits 3a, 3b, 3c, 3d, 3e, and 3f are controlled so that interrupt processing is preferentially performed in this order.

In this way, by setting the priority of execution instructions to the interrupt processing task by the monitor program,
It is possible to execute the interrupt processing with priority from the interrupt request having the higher priority regardless of the ready state setting order of the interrupt processing tasks by the interrupt handler.

[0094]

As described above, the CPU of the interrupt control circuit according to the first aspect of the present invention is connected to each of the plurality of registers of the storage means so that the stored data can be read and written. It is possible to detect whether or not the interrupt request signals of the plurality of external circuits indicate the interrupt request via the.

Therefore, when the CPU input interrupt request signal indicates an interrupt request as in the interrupt control method according to the second aspect of the present invention, the data stored in the plurality of registers of the storage means are read out to select one of the plurality of external circuits. The external circuit that has issued the interrupt request can be specified as the interrupt request external circuit.

Since the input / output terminals required for connecting to the storage means in a readable / writable manner can share the input / output terminals for the external storage device which should be connected originally,
There is no need to newly install it.

As a result, since it is possible to execute interrupt processing for a plurality of external circuits by providing only one interrupt input terminal, it is possible to handle many interrupt requests while keeping the number of interrupt input terminals to a necessary minimum. it can.

According to a fifth aspect of the present invention, an interrupt control system independently executes a plurality of interrupt processing tasks that perform actual interrupt processing for each of a plurality of external circuits and an interrupt handler that controls execution of the interrupt processing tasks. Therefore, complicated interrupt control can be performed relatively easily by the interrupt handler that does not need to perform the actual interrupt processing.

In the CPU of the interrupt control circuit according to the eighth aspect of the present invention, since a plurality of interrupt request signals from a plurality of external circuits are given to the plurality of general-purpose input / output ports, a plurality of general-purpose input / output ports are used. It is possible to detect whether or not the interrupt request signals of the plurality of external circuits indicate the interrupt request.

Therefore, when the CPU input interrupt request signal indicates an interrupt request as in the interrupt control method according to the ninth aspect, the signal levels of the plurality of interrupt request signals given to the plurality of general-purpose input / output ports are set. Of the plurality of external circuits that have been read, the external circuit that has made the interrupt request can be specified as the interrupt request external circuit.

Since the general-purpose input / output port shares the port of the input / output circuit to be originally connected, it is not necessary to newly provide it.

As a result, since it is possible to execute interrupt processing for a plurality of external circuits by providing only one interrupt input terminal, it is possible to handle many interrupt requests while keeping the number of interrupt input terminals to a necessary minimum. it can.

In the interrupt control system according to the twelfth aspect of the present invention, a plurality of interrupt processing tasks that perform actual interrupt processing for each of a plurality of external circuits and an interrupt handler that controls the execution of the interrupt processing tasks are independently executed. Therefore, complicated interrupt control can be performed relatively easily by an interrupt handler that does not need to actually perform interrupt processing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an interrupt control circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an interrupt control system of the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of an interrupt control circuit according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing an interrupt control system of a second embodiment.

FIG. 5 is a timing chart showing an interrupt processing situation of the interrupt control circuits of the first and second embodiments.

FIG. 6 is a flowchart showing an interrupt control method according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing an interrupt control system according to a fourth embodiment of the present invention.

FIG. 8 is a flowchart showing an interrupt control method according to a fifth embodiment of the present invention.

FIG. 9 is a flowchart showing an interrupt control system according to a fifth embodiment of the present invention.

FIG. 10 is a flowchart showing an interrupt control system according to a sixth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a conventional interrupt control circuit.

[Explanation of symbols]

 1 CPU 2a to 2c Interrupt input terminal 3a to 3h External circuit 5a to 5f Register 6 Logical sum circuit 50 Register circuit

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[Procedure amendment]

[Submission date] April 20, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 5

[Correction method] Change

[Correction content]

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 8

[Correction method] Change

[Correction content]

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 9

[Correction method] Change

[Correction content]

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 12

[Correction method] Change

[Correction content]

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 14

[Correction method] Change

[Correction content]

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram showing a configuration of a conventional interrupt control circuit. As shown in the figure, the interrupt request signals 4a to 4c from the plurality of external circuits 3a to 3c, respectively.
4c is provided to the interrupt input terminals 2a to 2c of the CPU 1. Although not shown,
As a matter of course, the CPU 1 is connected to the external circuits 3a to 3c so that the interrupt processing for the external circuits 3a to 3c can be executed.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007]

An interrupt control circuit according to a first aspect of the present invention has an interrupt input terminal set to level sense for taking in a CPU input interrupt request signal, and is provided for each of a plurality of external circuits. a CPU interrupt processing can be executed, provided corresponding to said plurality of external circuits, and a plurality of memorize means for storing a plurality of interrupt request signals from the plurality of external circuits as the storage data, said plurality of interrupt Interrupt request control means for outputting the CPU input interrupt request signal for instructing an interrupt request to the interrupt input terminal when at least one of the plurality of interrupt request signals indicates an interrupt request, the CPU, the the plurality of <br/> storage means Noso respectively, read and write connected of the storage data That.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

An interrupt control system according to a second aspect of the present invention uses the interrupt control circuit according to the first aspect,
A control method when the CP U is requested an interrupt, (a) reads the store data of the plurality of storage means, the plurality of external circuits, interrupt an external circuit performing an interrupt request Specifying as a request external circuit, (b) performing an interrupt process for the interrupt request external circuit, (c) clearing the interrupt request instruction of the interrupt request signal of the interrupt request external circuit, and And a step of clearing an interrupt request instruction of the stored data of the storage means corresponding to the interrupt request external circuit among the plurality of storage means .

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

An interrupt control system according to a fifth aspect of the present invention uses the interrupt control circuit according to the first aspect,
In the case where CP U is an interrupt request, a method of executing a plurality of interrupt processing tasks to actual interrupt processing for each of the plurality of external circuits, and the interrupt handler for controlling the execution of the interrupt processing task independently there are, the interrupt handler, identifying as (a) reads the store data of the plurality of storage means, the plurality of external circuits, interrupt request external circuit external circuit performing an interrupt request, (b) among the plurality of interrupt processing tasks, versus the interrupt request external circuit
A step of the interrupt processing task to executable state, as well as clear the interrupt request instruction of the interrupt request signal (c) said interrupt request external circuit, among the plurality of storage means, corresponding to said interrupt request external circuit And a step of clearing an interrupt request instruction of the stored data of the storage means ,
The interrupt processing task for (1) executes the interrupt processing for the interrupt request external circuit when the task becomes ready to execute.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

[0014] The interrupt control circuit according to claim 8, wherein according to the present invention is to incorporate CPU input interrupt request signal
The interrupt input pin set to Bellsense and the input
It is set, and a plurality of general purpose input and output ports for receiving a plurality of interrupt request signals from a plurality of external circuits, external circuitry
Wherein the interrupt processing can be executed CPU against, the receiving a plurality of interrupt request signals, when at least one of the multiple interrupt request signal instructing the interrupt request, the CPU input interrupt request signal indicating an interrupt request And an interrupt request control means for outputting to an interrupt input terminal.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

An interrupt control system according to a ninth aspect of the present invention uses the interrupt control circuit according to the eighth aspect.
A control method when the CP U is requested an interrupt, (a) reads the signal levels of the plurality of interrupt request signals applied to the plurality of general purpose input and output ports, said plurality of external circuits Of these, a step of identifying the external circuit that has made an interrupt request as an interrupt request external circuit,
(b) a step of performing an interrupt process on the interrupt request external circuit; and (c) a step of clearing an interrupt request instruction of the interrupt request signal of the interrupt request external circuit.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

The interrupt control method according claim 12 wherein in the present invention, using an interrupt control circuit according to claim 8, wherein when the CP U is an interrupt request, actual interrupt processing for each of the plurality of external circuits A method of independently executing a plurality of interrupt processing tasks that perform the above and an interrupt handler that controls the execution of the interrupt processing tasks, wherein the interrupt handler is (a) assigned to the plurality of general-purpose input / output ports. Reading the signal levels of the plurality of interrupt request signals and, of the plurality of external circuits, identifying an external circuit that has made an interrupt request as an interrupt request external circuit; and (b) out of the plurality of interrupt processing tasks. , versus the interrupt request external circuit
And a step of (c) clearing an interrupt request instruction of the interrupt request signal of the interrupt request external circuit , the interrupt processing task for the interrupt request external circuit, When the ready state is reached, the interrupt process for the interrupt request external circuit is executed.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

[0021]

[Action] CPU interrupt control circuit according to claim 1, wherein in the present invention, the plurality of memory hand stage their respective, because it is writable connected stored data, a plurality of outside via a storage means It is possible to detect whether the interrupt request signal of the circuit indicates an interrupt request.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

Therefore, as in the interrupt control system according to the second aspect, when the CPU is requested for an interrupt, a plurality of interrupts are issued.
It reads the store data in the storage means, among the plurality of external circuits, it is possible to specify the external circuit of performing an interrupt request as an interrupt request external circuit.

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

[0026] Thus, as in the interrupt control method according to claim 9, when the CP U is requested an interrupt, reads the signal levels of the plurality of interrupt request signals applied to the plurality of general purpose input and output ports, Among the plurality of external circuits, the external circuit that has made the interrupt request can be specified as the interrupt request external circuit.

[Procedure 18]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Change

[Correction content]

The general-purpose I / O port is originally a CPU
Since the port of the equipped input / output circuit is used , there is no need to newly install it.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

On the other hand, the interrupt request signals 4a to 4f of the external circuits 3a to 3f are transferred to the registers 5a to 5f of the register circuit 50.
It is connected so as to be given to 5f and is also connected so as to be given to the logical sum circuit 6. The external circuit 3
The interrupt request signals 4a to 4f of a to 3f are at the H level (logic "1") when the interrupt request is instructed, and are at the L level (logic "0") when the interrupt request is not instructed.
Is the signal. Although not shown in FIG. 1, naturally
However , the CPU 1 executes the interrupt processing on the external circuits 3a to 3c so that the external circuits 3a to 3c can execute interrupt processing.
~ 3c is connected.

[Procedure amendment 20]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

The register circuit 50 via the read control terminal 11 and the write control terminal 12 of CPU1, the read control signal 8 and the write control signal 9 is connected, each register 5a~5f register circuit 50, the CPU1 The data input / output terminals 13a to 13f are connected so that data can be written and read.

[Procedure correction 21]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

Referring to FIG. 2, first, in step S1,
After applying the read control signal 8 for instructing the read to the register circuit 50, each register 5 in the register circuit 50
Data stored in a to 5f are transferred to the data input / output terminals 13a to 13
Read out via f.

[Procedure correction 22]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction content]

When the interrupt processing is completed, step S5
Then, after clearing the interrupt request signal output from the interrupt request external circuit to "L" and applying the write control signal 9 for instructing the write to the register circuit 50, the registers 5a to 5 corresponding to the interrupt request external circuit are provided.
Write "L" in f to clear the interrupt request.

[Procedure amendment 23]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

On the other hand, the interrupt request signals 4a to 4f of the external circuits 3a to 3f are sent to the general-purpose input / output port 10a of the CPU 1.
10f, interrupt request signals 4a-4f,
It is configured to be directly applied to the CPU 1. The interrupt request signals 4a to 4f are also given to the logical sum circuit 6. The interrupt request signal 4 of the external circuits 3a to 3f
Signals a to 4f are H level signals when an interrupt request is instructed. Incidentally, not shown in FIG. 3, but of course
In this regard, the CPU 1 executes the external circuits 3a to 3c so that the interrupt processing for the external circuits 3a to 3c can be executed.
3c is connected.

[Procedure correction 24]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction content]

General purpose input / output ports 10a to 10f
Is a child shared by an external input / output circuit, and the external circuit 3
It is not newly provided for inputting the interrupt request signals 4a to 4f of a to 3f. Also, the interrupt request signals 4a-4
The input is set so that the value of f can be read.

[Procedure correction 25]

[Document name to be amended] Statement

[Correction target item name] 0060

[Correction method] Change

[Correction content]

At time T3, the interrupt request signal 4b
Is "H", the logical sum signal 7 maintains "H" ,
Since the interrupt of the CPU 1 is set to level sense , the interrupt processing routine is continued, and from time T3,
An interrupt process for the external circuit 3b is performed.

[Procedure Amendment 26]

[Document name to be amended] Statement

[Name of item to be corrected] 0070

[Correction method] Change

[Correction content]

Then, in step S42, step S4
When it is detected that at least one of the interrupt request signals 4a to 4f is "H" based on the check of the interrupt generation source of No. 1, it is determined that "interrupt (request) is present", the process proceeds to step S43, and all are "L" In the case of "(logic" 0 "), it is judged that there is no interrupt (request), and the process returns from the interrupt processing routine.

[Procedure Amendment 27]

[Document name to be amended] Statement

[Correction target item name] 0080

[Correction method] Change

[Correction content]

Then, in step S52, step S5
Based on the value verified in 1, the interrupt processing task that performs interrupt processing for the corresponding external circuit 3 is set to the ready state (executable state).

[Procedure correction 28]

[Document name to be amended] Statement

[Correction target item name] 0082

[Correction method] Change

[Correction content]

[0082] Hereinafter, the interrupt processing tasks with reference to FIG. 9
The operation of will be described.

[Procedure correction 29]

[Document name to be amended] Statement

[Name of item to be corrected] 0083

[Correction method] Change

[Correction content]

[0083] Step S61 is a standby state, is in the ready state by the instruction of the interrupt handler, Ralt given more execution instruction to the filter disk control program called a monitor plug ram, the first time proceeds to step S62. Then, in step S62, interrupt processing for the corresponding external circuit 3 is executed. When interrupt processing is completed
At this point, it shifts to the standby state S61 and prepares for new interrupt processing.
Get

[Procedure amendment 30]

[Document name to be amended] Statement

[Correction target item name] 0084

[Correction method] Change

[Correction content]

It should be noted that one interrupt processing task is provided for each interrupt processing of one external circuit 3.

[Procedure correction 31]

[Document name to be amended] Statement

[Correction target item name] 0085

[Correction method] Change

[Correction content]

As described above, in the fifth embodiment, the interrupt processing can be divided into the interrupt handler processing and the interrupt processing task and independently executed. As a result, the interrupt handler can entrust the actual interrupt processing to the interrupt processing task, so there are many interrupt sources and complicated interrupt control such as when the processing corresponding to each interrupt source is complicated. Can be performed relatively easily. <Sixth Embodiment> FIG. 10 is a flow chart showing a processing routine of an interrupt handler according to the sixth embodiment of the present invention. As the interrupt control circuit, even in the configuration of the first embodiment shown in FIG.
The configuration of the second embodiment shown in FIG. It should be noted that this interrupt handler is an interrupt handler when there is an interrupt request to the interrupt input terminal 2a. Also, FIG.
The interrupt handler of 0 corresponds to the processing of the interrupt handler of the fifth embodiment shown in FIG. 8, and the actual interrupt processing is performed by the interrupt processing task of the fifth embodiment shown in FIG.

[Procedure correction 32]

[Document name to be amended] Statement

[Correction target item name] 0092

[Correction method] Change

[Correction content]

For example, the priority order of execution instructions to the interrupt processing task by the monitor program is set to the external circuits 3a, 3
If the settings are made in the order of b, 3c, 3d, 3e, 3f, FIG.
As in the operation of the sixth embodiment shown in FIG.
3e, 3d, 3c, 3b, in the order of 3a, be set the ready state of the interrupt processing task, monitor program Yu
According to the order of precedence , the external circuits 3a, 3b, 3c, 3d, 3
The interrupt processing task is executed in the order of e and 3f .

[Procedure amendment 33]

[Document name to be amended] Statement

[Correction target item name] 0094

[Correction method] Change

[Correction content]

[0094]

As described above, according to the present invention, CPU interrupt control circuit according to claim 1, wherein in the present invention, the multiple serial
Since the storage data is connected to each storage device so that the storage data can be read and written, it is possible to detect whether or not the interrupt request signals of the plurality of external circuits indicate the interrupt request via the storage device.

[Procedure amendment 34]

[Document name to be amended] Statement

[Correction target item name] 0095

[Correction method] Change

[Correction content]

[0095] Thus, as in the interrupt control method according to claim 2, when the CP U is requested an interrupt, reads the data stored in the multiple storage means among a plurality of external circuits, performing an interrupt request It is possible to specify the external circuit as an interrupt request external circuit.

[Procedure amendment 35]

[Document name to be amended] Statement

[Correction target item name] 0100

[Correction method] Change

[Correction content]

[0101] Thus, as in the interrupt control method according to claim 9, when the CP U is requested an interrupt, reads the signal levels of the plurality of interrupt request signals applied to the plurality of general purpose input and output ports, Among the plurality of external circuits, the external circuit that has made the interrupt request can be specified as the interrupt request external circuit.

[Procedure correction 36]

[Document name to be amended] Statement

[Correction target item name] 0101

[Correction method] Change

[Correction content]

[0102] Incidentally, the general-purpose input-output ports, because it uses the port of the input and output circuits to be originally connected is not necessary to newly provide.

[Procedure amendment 37]

[Document name to be corrected] Drawing

[Correction target item name] Figure 9

[Correction method] Change

[Correction content]

[Figure 9]

Claims (14)

[Claims] 1. A CPU having an interrupt input terminal for fetching a CPU input interrupt request signal and capable of executing interrupt processing for each of a plurality of external circuits; and a CPU provided corresponding to the plurality of external circuits. Storage means comprising a plurality of registers for storing a plurality of interrupt request signals from an external circuit as stored data; and receiving at least one of the plurality of interrupt request signals and at least one of the plurality of interrupt request signals indicates an interrupt request. An interrupt request control means for outputting the CPU input interrupt request signal for instructing an interrupt request to the interrupt input terminal is provided, and the CPU can read and write the stored data with respect to each of the plurality of registers of the storage means. Connected interrupt control circuit. 2. An interrupt control method using the interrupt control circuit according to claim 1, wherein the CPU input interrupt request signal indicates an interrupt request, and (a) storing the plurality of registers in the storage means. A step of reading the data and, of the plurality of external circuits, specifying an external circuit that has made an interrupt request as an interrupt request external circuit; and (b) performing an interrupt process for the interrupt request external circuit, c) clearing the interrupt request instruction of the interrupt request signal of the interrupt request external circuit, and clearing the interrupt request instruction of the stored data of the register corresponding to the interrupt request external circuit among the plurality of registers; Interrupt control system with. 3. The interrupt processing for the plurality of external circuits has priorities set in advance, and in the step (a), the interrupt request external circuits are specified in an order based on the priority. The interrupt control method described in 2. 4. The step (a) performs the specifying process of the interrupt request external circuit from the external circuit that is set next to the previously specified interrupt request external circuit based on a predetermined specifying process order. The described interrupt control method. 5. The interrupt control circuit according to claim 1, wherein when the CPU input interrupt request signal indicates an interrupt request, a plurality of interrupt processing tasks that perform actual interrupt processing for each of the plurality of external circuits, An interrupt control method for independently executing an interrupt handler for controlling execution of the interrupt processing task, wherein the interrupt handler is: (a) reading data stored in the plurality of registers of the storage means, Among the external circuits, a step of identifying the external circuit that has made an interrupt request as an interrupt request external circuit, and (b) making the interrupt processing task for the interrupt request external circuit ready to be executed among the plurality of interrupt processing tasks. And (c) an interrupt request instruction of the interrupt request signal of the interrupt request external circuit. Clearing, and clearing the interrupt request instruction of the stored data of the register corresponding to the interrupt request external circuit among the plurality of registers, the interrupt processing task for the interrupt request external circuit executes An interrupt control method in which, when enabled, an interrupt process for the interrupt request external circuit is executed. 6. The interrupt processing for an external circuit has priorities set in advance, and in the step (a), the interrupt request external circuit is specified in an order based on the priority. Interrupt control method. 7. The priorities of the plurality of interrupt processing tasks are set in advance, and when two or more interrupt processing tasks are simultaneously ready to be executed, the interrupt processing tasks are executed in the order based on the priority order. The interrupt control system according to claim 5, wherein 8. An interrupt input terminal for fetching a CPU input interrupt request signal, a plurality of general-purpose input / output circuits for exchanging input / output data, and a plurality of interrupt request signals from a plurality of external circuits. A CPU having a general-purpose input / output port and capable of executing interrupt processing for each of the plurality of external circuits; and a case in which at least one of the plurality of interrupt request signals receives an interrupt request. An interrupt request control means for outputting the CPU input interrupt request signal for instructing an interrupt request to the interrupt input terminal. 9. An interrupt control method using the interrupt control circuit according to claim 8, wherein the CPU input interrupt request signal indicates an interrupt request, and (a) is assigned to the plurality of general-purpose input / output ports. Reading the signal levels of the plurality of interrupt request signals, and specifying the external circuit that has made an interrupt request among the plurality of external circuits as an interrupt request external circuit, (b) for the interrupt request external circuit An interrupt control method comprising: (c) clearing an interrupt request instruction of the interrupt request signal of the interrupt request external circuit. 10. The interrupt processing for the plurality of external circuits has priorities set in advance, and in the step (a), the interrupt request external circuits are specified in an order based on the priority. 9. The interrupt control method described in 9. 11. The step (a) performs the specifying process of the interrupt request external circuit from the external circuit which is set next to the interrupt request external circuit specified last time based on a predetermined specifying process order. The described interrupt control method. 12. The interrupt control circuit according to claim 8, wherein when the CPU input interrupt request signal indicates an interrupt request, a plurality of interrupt processing tasks that perform actual interrupt processing for each of the plurality of external circuits, An interrupt control method for independently executing an interrupt handler for controlling execution of the interrupt processing task, wherein the interrupt handler includes: (a) a plurality of interrupt request signals assigned to the plurality of general-purpose input / output ports. Of the plurality of external circuits, the step of identifying the external circuit that has made an interrupt request as an interrupt request external circuit, and reading the signal level, (b) selecting the interrupt request external circuit from among the plurality of interrupt processing tasks. (C) the interrupt request external circuit of the interrupt request external circuit A step of clearing an interrupt request instruction of the interrupt request signal, wherein the interrupt processing task for the interrupt request external circuit executes an interrupt process for the interrupt request external circuit when the ready state is reached. . 13. The interrupt processing for an external circuit has a priority set in advance, and in the step (a), the interrupt request external circuit is specified in an order based on the priority. Interrupt control method. 14. The plurality of interrupt processing tasks have priorities set in advance, and when two or more interrupt processing tasks are simultaneously ready to be executed, the interrupt processing tasks are executed in an order based on the priority order. 14. The interrupt control system according to claim 13.