JPH061820B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to an improved semiconductor device and a method for manufacturing the same.

A semiconductor substrate that constitutes a semiconductor device may contain heavy metals such as iron (Fe), nickel (Ni), and chromium (Cr) in a very small amount even if they are dispersed in a small amount inside the semiconductor substrate, although the amount is very small. . Further, the heavy metal may be dispersed in at least a part of the inside of the semiconductor substrate due to various processing steps in the manufacturing process of the semiconductor device.

The heavy metal serves as a GR center (generation-recombination center), and serves as a supply source of unnecessary carriers that affect the characteristics of the semiconductor device.

2. Description of the Related Art A dynamic memory (hereinafter referred to as DRAM) having a storage function in a semiconductor device has a structure in which a capacity electrode for storing information is formed by a capacity electrode of a memory cell forming the dynamic memory and information is stored therein. However, if the GR center is present in the capacitance section or its peripheral section, the amount of accumulated charge may change due to unnecessary carriers emitted from the GR center. As a result, a change in information occurs in a part of the DRAM, which is one of the causes of malfunction of the DRAM.

In order to maintain such characteristics of the semiconductor device, it is becoming clear that providing a crystal defect in the semiconductor substrate is effective in capturing the GR center. Based on this, various semiconductor devices in which a crystal defect is provided on a semiconductor substrate have been conventionally proposed. The main ones are semiconductor devices equipped with extrinsic gettering in which a crystal defect layer is provided in the lower part of the semiconductor substrate, and intrinsic gettering intrineic in which a crystal defect layer is provided in the central part of the semiconductor substrate. It is a semiconductor device provided with gettering).

However, as a result of experiments and studies by the present inventors, in the semiconductor device having the extrinsic gettering, the distance between the crystal defect layer and the semiconductor element formation region is large, and the effect of trapping the GR center is obtained. Was found to be extremely small. In addition, in the semiconductor device having the intrinsic gettering, the heat treatment process for forming the crystal defect layer provided in the central portion of the semiconductor substrate is complicated, and the control of the crystal defect density and the formation of other defect-free regions are complicated. It has been found that the control of is extremely difficult.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device having a memory cell composed of a MISFET and an information storage capacitor, and in particular, the MISFET.
The present invention is to capture the GR center existing around the Stable stably and surely, and to capture the GR center with a simple technique.

In order to achieve such an object, the present invention provides a second conductivity type having a conductivity type opposite to the first conductivity type serving as a source region or a drain region of a MISFET on a part of a main surface of a first semiconductor of the first conductivity type. Type second semiconductor region, and an information storage part electrically connected to the second semiconductor region on the other part of the main surface of the first semiconductor, and the MISFET and the information storage part form a memory cell. A method of manufacturing a semiconductor device, comprising: introducing a second conductivity type impurity into a part of a main surface of the first semiconductor by ion implantation in a state where the first conductivity type first semiconductor is heated to a temperature of 100 ° C. or higher. Then, after that, a heat treatment is performed to form the second conductivity type second semiconductor region having a crystal defect density of 1 × 10 ² / cm ² or more.

Hereinafter, the present invention will be described in detail with reference to an example.

In all the drawings, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. This embodiment will be described using a semiconductor device including a DRAM.

1 is a cross-sectional view of an essential part showing a single memory cell portion of a semiconductor device for explaining an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG.

In FIGS. 1 and 2, reference numeral 1 denotes a p-type semiconductor substrate made of silicon single crystal, which is used to form a semiconductor device. Reference numeral 2 denotes an insulating film (field insulating film) provided between the semiconductor elements on the semiconductor substrate 1 for electrically separating the semiconductor elements. Reference numeral 3 is a p ⁺ type channel stopper region provided in the semiconductor substrate 1 below the insulating film 2 for more completely separating the semiconductor elements. Reference numeral 4 denotes an insulating film provided in the semiconductor element portion on the semiconductor substrate 1, which is necessary for forming a capacitor and a gate which will be described later. Reference numeral 5 denotes a capacitance electrode provided on the insulating film 4 on the left side of the semiconductor element portion and forms an information storage capacitance C. 6 was formed on the insulating film 4 in the right portion of the semiconductor element portion MISFET (M etal I nsulator S em
iconductor F ield E ffect T rabsistor) a gate constituting Q ₁ electrode (G), so as to form a channel in the vicinity of the semiconductor substrate 1 through the insulating film 4 thereto by applying a voltage. This channel electrically connects between semiconductor regions provided on the semiconductor substrate 1 on both sides of the gate electrode 6 which will be described later. The gate electrode 6 is connected to a gate electrode of another semiconductor element adjacent in one direction to form a word line (WL). Reference numeral 7 denotes an n ⁺ type semiconductor region (source and drain regions) provided on the semiconductor substrate 1 on both sides of the gate electrode 6 and has conductivity. Reference numeral 8 denotes an insulating film made of phosphosilicate glass (PSG) provided on the entire surface of the semiconductor substrate 1, which traps sodium (Na) ions that affect the characteristics of the semiconductor device and relaxes the bumps due to the multilayer structure. It is for. Reference numeral 9 is a connection hole (contact hole) provided in the insulating films 4 and 8 above the predetermined semiconductor region 7, and connects the semiconductor region 7 and the bit line (BL) 10 provided on the insulating film 8. It is for.

The semiconductor region 7 has more crystal defects than the conventional semiconductor region. In this example, the number of crystal defects is about 1 × 10 ⁶ / cm ² . This is because when the impurities for forming the semiconductor region 7 are introduced, the semiconductor substrate 1 is heated to a temperature of about 100 ° C. or higher, the impurities are introduced by the ion implantation method, and the impurities are introduced into the semiconductor region 7 by the introduction. A crystal defect may be formed. Further, as a result of this, the recovery of the crystal defects is extremely low because the semiconductor substrate 1 is heated to form crystal defects even in various heat treatment steps performed thereafter. Here, the relationship between the substrate temperature and the crystal defects at the time of ion implantation will be described with reference to FIG.

FIG. 3 is a diagram showing the relationship between the semiconductor substrate temperature and the number of crystal defects when impurities for forming a semiconductor region are introduced into the semiconductor substrate. The horizontal axis represents the semiconductor substrate temperature (° C.) when impurities are introduced, and the vertical axis represents 10 after the impurity introduction.
It shows the crystal defect density (number / cm ² ) after high temperature heat treatment for about 6 hours by steam oxidation at about 00 ° C. As a result, the defect density indicates the number of crystal defects per unit area. Here, the introduction of impurities is 1
Arsenic ion impurities of about 10 ¹⁶ atoms / cm ² are ion-implanted, and at the same time, a heavy metal (for example, iron, chromium, etc.) serving as a GR center is introduced, whereby forced contamination before the high temperature heat treatment is performed. I made a sample.
As is clear from the figure, by heating the semiconductor substrate to a temperature of about 100 ° C. or higher during ion implantation, the recoverability of crystal defects due to the introduction of impurities can be significantly reduced, and It was found that the number of crystal defects to be provided can be significantly increased.

In the present invention, the semiconductor region 7 is formed based on this fact so that the number of crystal defects is increased by heating the substrate temperature at the time of ion implantation to a predetermined temperature. In the present invention, the semiconductor substrate 1 may be present in the semiconductor substrate by subjecting the semiconductor substrate to high temperature heat treatment at about 1000 ° C. after forming crystal defects in the semiconductor region 7 by ion implantation. -It consists of a captured R center. G
By reducing the -R center, the generation of unfavorable minority carriers in the semiconductor substrate 1 is positively reduced. This high temperature heat treatment can also be used in a step such as an annealing treatment after the ion implantation.

The number of crystal defects provided in the semiconductor region 7 is not limited to the value shown in the above-mentioned embodiment, and as shown in FIG. 3, it is about 1 × 10 ² / cm ² or more and within a possible range. The larger the number of crystal defects, the better.

FIG. 4 shows the semiconductor substrate temperature (ion implantation temperature) when impurities are introduced into the semiconductor substrate for semiconductor region formation in the state where a crystal defect is formed by ion implantation and then a high temperature treatment of about 1000 ° C. is performed. And the life of minority carriers existing around the semiconductor region formed by this (hereinafter, life time (li
fe time)]]. The horizontal axis is the semiconductor substrate temperature (° C.) when impurities are introduced by ion implantation, and the vertical axis is the life of minority carriers existing in the substrate around the semiconductor region formed by the high temperature heat treatment after the impurities are introduced. It shows time on an arbitrary scale. As is clear from the figure, by heating the semiconductor substrate 1 to about 100 ° C. or higher during ion implantation, the lifetime of minority carriers existing around the semiconductor region 7 is significantly improved. Therefore, as shown in FIG. 3 and FIG. 4, the GR center existing around the semiconductor region 7 is remarkably improved in absorption degree by the crystal defects as the number of crystal defects in the semiconductor region 7 increases. However, the generation of minority carriers in the substrate can be reduced. It suffices that the semiconductor region 7 has the maximum number of crystal defects in a range that does not cause deterioration of electrical characteristics such as junction leak at the pn junction between the semiconductor region 7 and the semiconductor substrate 1. The range is a crystal defect density of 1 × 10 ² / cm ² or more,
The degree is such that the pn junction is not damaged. As described above, these can be achieved by heating the semiconductor substrate 1 to a temperature of about 100 ° C. or higher when introducing the impurities for forming the semiconductor region 7.

FIG. 5 is a diagram for explaining the influence of the crystal defects provided in the semiconductor region on the pn junction with the semiconductor substrate. The horizontal axis indicates the distance from the surface of the semiconductor substrate to the inside thereof, and the vertical axis indicates the impurity concentration for forming the semiconductor region or the number of crystal defects caused by the introduction thereof. The data (A) shows the concentration distribution of impurities when the impurities for forming the semiconductor region are introduced into the semiconductor substrate. The data (B) shows the distribution of the number of crystal defects caused by the introduction of the impurities.
The data (A) and the data (B) show a Gaussian distribution, and the range (maximum value) R _p2 of the data (B) is on the semiconductor substrate surface side with respect to the range R _p1 of the data (A). (R _p2 2 / 3R _p1 ). Generally, the diffusion rate of the impurities is significantly higher than the growth rate of crystal defects. That is, even if the semiconductor region is formed, the existence of crystal defects is extremely small in the pn junction. Therefore, even if a crystal defect is formed in the semiconductor region 7 by ion implantation, there is almost no damage to the pn junction due to the crystal defect, and a G-R center which causes unnecessary minority carriers due to the crystal defect formed therein is significantly formed. It can be reduced.

Next, a specific manufacturing method of the present invention will be described.

6 to 11 are cross-sectional views of essential parts of the semiconductor device in respective manufacturing steps for explaining the manufacturing method of the embodiment of the present invention shown in FIG.

First, as shown in FIG. 6, p made of silicon single crystal is used.
A mold semiconductor substrate 1 is prepared. LO of this semiconductor substrate 1
By COS (LOC al o xidation of S ilicon) technology,
An insulating film (field insulating film) 2 for electrically separating the semiconductor elements is formed. At this time, at the same time, a p ⁺ type channel stopper region 3 is formed in the semiconductor substrate 1 below the insulating film 2 in order to more completely separate the semiconductor elements.
After this, as shown in FIG. 7, the insulating film 4 is formed in the semiconductor element portion.

After the step shown in FIG. 7, the capacitor electrode 5 made of another crystalline silicon is formed on the left side of the semiconductor element portion as shown in FIG.

After the step shown in FIG. 8, as shown in FIG.
A gate electrode (G) 6 of polycrystalline silicon forming the FET Q ₁ is formed on the right side of the semiconductor element portion. The gate electrode 6 is connected to the gate electrodes of other semiconductor elements adjacent in one direction to form a word line (WL).

After the step shown in FIG. 9, the semiconductor substrate 1 is heated to a temperature of about 100 ° C. or higher, and the capacitor electrode 5 and the gate electrode 6 are used as a mask for implanting impurities. Impurities for forming a semiconductor region are implanted into the element portion. The implantation of this impurity is
Ion implantation may be performed with an energy of about 80 [KeV] using an arsenic (As) ion impurity having a concentration of about 1 × 10 ¹⁶ atoms / cm ² . At this time, the film thickness of the insulating film 4'in the opening of the polycrystalline silicon is determined in relation to the ion transmittance. Further, this insulating film 4'may be omitted. After that, the impurities are stretched and diffused by high-temperature heat treatment to form n ⁺ type semiconductor regions (source and drain regions) 7 by self alignment as shown in FIG. The crystal defect density of the semiconductor region 7 is about 1 × 10 ₆ defects / cm ² .

After the step shown in FIG. 10, the insulating film 8 is formed on the entire surface. The insulating film 8 is preferably made of phosphorus-silica case glass (PSG) that traps sodium (Na) ions that affect the characteristics of the semiconductor device and that alleviates the protrusion due to the multilayer structure. After that, the insulating films 4 and 8 above the semiconductor region 7 connected to the bit line formed in a later step are removed to form a connection hole (contact hole) 9. When the bit line (BL) 10 is formed so as to be connected to the semiconductor region 7 through the connection hole 9, it becomes as shown in FIG. The bit line 10 is preferably made of a low resistance wiring material such as aluminum.

Through these series of steps, the semiconductor device of this embodiment is completed. Further, after this, a treatment such as a protective film may be performed.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

As described above, according to the present invention, in forming a semiconductor region forming a semiconductor device, when introducing an impurity for forming the semiconductor region, the semiconductor substrate into which the impurity is introduced is about 100 ° C. or By heating to the above temperature, the recoverability of the crystal defects caused by the introduction of the impurities can be remarkably reduced and the number of crystal defects in the semiconductor region can be remarkably increased even if the heat treatment process performed thereafter is performed. The crystal defects can capture the GR centers in the semiconductor substrate according to the number thereof.
Therefore, the GR center in the semiconductor substrate that affects the characteristics of the semiconductor device as well as the number of crystal defects can be reduced by the heat treatment in the manufacturing process of the semiconductor device, and the reliability of the semiconductor device can be improved. .

In addition, since the semiconductor region can be easily provided by a normal manufacturing process, adverse effects due to complicated processing steps are reduced, and a stable semiconductor region can be provided.

Furthermore, since the semiconductor region can be held at a predetermined position, the trapping action at that portion can be stabilized. For example, the semiconductor region forming the MISFET of the DRAM memory cell is always held at a predetermined position, and the G-R center that causes unnecessary carriers that adversely affects the information storage capacity is reduced by the adjacent semiconductor region, It is possible to prevent malfunction of the DRAM.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a semiconductor device for explaining an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a relational diagram between the semiconductor substrate temperature and the number of crystal defects for explaining an example, FIG. 4 is a relational diagram between the semiconductor substrate temperature and lifetime for explaining one embodiment of the present invention, and FIG. FIG. 6 to FIG. 11 are views showing the relationship between the impurity concentration in a semiconductor substrate and the number of crystal defects in the semiconductor substrate for explaining an embodiment of the present invention, and FIGS. FIG. 6 is a cross-sectional view of a main portion of the semiconductor device in each manufacturing step for performing In the figure, 1 ... Semiconductor substrate, 2, 4, 8 ... Insulating film, 3 ... Channel stopper region, 5 ... Capacitance electrode, 6 ... Gate electrode,
7 ... Semiconductor region, 9 ... Connection hole, 10 ... Bit line.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-56-93367 (JP, A) JP-A-57-107074 (JP, A) JP-A-57-90973 (JP, A) JP-A-57- 194581 (JP, A)

Claims (2)

[Claims] 1. A MI on a part of a main surface of a first semiconductor of a first conductivity type.
The first region serving as the source region or the drain region of the SFET
A second semiconductor region of a second conductivity type having a conductivity type opposite to the conductivity type, and an information storage part electrically connected to the second semiconductor region in the other part of the main surface of the first semiconductor, The MIS
A method of manufacturing a semiconductor device comprising a memory cell with an FET and an information storage unit, wherein a part of the main surface of the first semiconductor is heated to a temperature of 100 ° C. or higher. The second conductivity type second impurity of the second conductivity type is introduced by ion-implanting the second conductivity type impurity and then heat-treated so that the crystal defect density is 1 × 10 ² / cm ² or more.
A method of manufacturing a semiconductor device, comprising forming a semiconductor region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the memory cell is a DRAM memory cell.