JPH06181319A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with which a read-out operation can be conducted accurately. CONSTITUTION:When a write operation is conducted, high voltage is applied to a source 2, and a channel 8 is formed by electrons jumped out to a drain 4 from the source 2. When low voltage is applied to a selection gate 20, an electric field is concentrated between a selection gate 14 and a substrate 1, a part of electrons are turned to hot electrons, and it is attracted toward a control gate 14 where high voltage is applied. The attracted hot electrons are trapped to the side of the source 2 of a nitrogen film 10, and information is written. When a read operation is conducted, a depletion layer 100 is spread in the vicinity of a drain 4 by the application of high voltage, but does not reach the point where information is written. Accordingly, whether electrons are trapped (information is written) by the nitrogen film 10 can be detected accurately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reading data from a semiconductor device. In particular, it relates to read accuracy.

[0002]

2. Description of the Related Art Generally, an ONO film (Oxide-Nitride) is used as a trap film of a trap type semiconductor memory.
e-Oxide) film is used. The O film of the ONO film is an oxide film and an insulating film. On the other hand, the N film is a nitride film and is a conductive film. Note that the N film which is a conductive film is sandwiched between O layers which are oxide films. During writing, electrons are guided to this N film.

Data writing and erasing will be described with reference to FIGS. 9A and 9B which are sectional views of a trap type memory using an ONO film. In the trap memory 200, the source 2 and the drain 4 are formed in the substrate 1. This sauce 2,
An ONO film (first O film 8, N (nitride) film 1 is provided between the drains 4.
0 and the second O film 12) are formed, and the control gate 14 is formed above them.

An outline of the write principle of the trap type memory 200 will be described with reference to FIG. 9A. Source 2 when writing
A channel is formed when electrons are emitted from the drain to the drain 4. Some of the emitted electrons are trapped in the N (nitride) film 10 near the drain as hot electrons. When the electrons are trapped in the N (nitride) film 10, the threshold voltage of the control gate voltage required to form the channel becomes large. In this way, the state in which the threshold value is increased is called the state in which "1" is written. On the other hand, a state in which electrons are not trapped and the threshold value remains small is called a state in which "0" is written.

On the other hand, in the case of erasing, a negative voltage is applied to the control gate 14 and a positive voltage is applied to the drain to guide holes to the N film and neutralize the injected negative electrons. (See Figure 9B). For reading, a sense voltage (a threshold voltage when electrons are trapped and an intermediate value when electrons are not trapped) is applied to the control gate, and if a channel is not formed, "1" is written. You can read what is rare. If a channel is formed, it can be read that "1" is not written ("0"). In this way, "1" can be freely written, erased and read in the trap type memory.

[0006]

However, the conventional trap type memory has the following problems. In the conventional device, as described with reference to FIG.
Electrons were trapped on the drain 4 side of the (nitride) film 10 by hot electron injection. Further, at the time of reading, a relatively high voltage was applied to the drain 4 to read the trapped electrons. However, when a high voltage is applied to the drain 4, the depletion layer 100 is formed in the substrate 1 around the drain 4 as shown in FIG. 9B.

When the depletion layer 100 spreads and reaches a position where electrons are trapped, the state is the same as when the channel is formed although the channel is not actually formed. I will end up. That is,
Even if electrons are trapped in the N (nitride) film 10 and a channel is not originally formed, the channel is formed, so that it is detected that "1" is not written. As described above, when the conventional device is used, the depletion layer 100 spreads during reading, and accurate reading cannot be performed.

Therefore, an object of the present invention is to provide a semiconductor device capable of performing accurate reading.

[0009]

According to another aspect of the present invention, there is provided a semiconductor device including a source region provided in a substrate, a source region provided in the substrate, and an electric path formable region formed between the source region and the source region. Drain region Trap film provided on the electric path formable region, control electrode provided on the trap film,
It is characterized in that it is provided on the source-side electric path formable region so as to be insulated from the electric path formable region, and has a side conductive layer provided on the side surface of the control electrode so as to be insulated from the control electrode.

[0010]

In the semiconductor device according to the present invention, the side conductive layer is provided on the source-side electric path formable region so as to be insulated from the electric path formable region and on the side surface of the control electrode so as to be insulated from the control electrode.

Therefore, since writing is performed on the source side, even if a high voltage is applied to the drain side and the depletion layer spreads, it does not reach the source side.

[0012]

EXAMPLE A structure of a trap type semiconductor memory according to the present invention will be described with reference to FIG. 2B. A source 2 as a source region and a drain 4 as a drain region are formed in a P-type substrate 1, and a first oxide film 8, an N (nitride) film 10 and a second dioxide film as a trap film are formed on the substrate 1. A film 12 is formed (this first oxide film 8, N
The three-layer film of the (nitride) film 10 and the second dioxide film 12 is turned on below.
O film 30). A control gate 14 which is a control electrode is formed on the ONO film 30, and the control gate 14
An oxide film 16 is formed so as to cover the substrate 1. The side surface of the control gate 14 has a select gate 2 as a side conductive layer.
0 is provided, and an interlayer film 18 is also formed so as to cover the control gate 14 and the substrate 1. Furthermore, the interlayer film 18
A bit line (drain line) 25 is formed on the top.

Next, an outline of the operation of the trap type semiconductor memory shown in FIG. 2B will be described with reference to FIG. FIG. 1A shows the operation state at the time of writing. In the trap type semiconductor memory according to the present embodiment, the drain 4 side and the control gate 1
By applying a high voltage to the source 4 and 0 V to the source 2, electrons are ejected from the source 2 to the drain 4 to form a channel 80 as an electric path formable region between the source 2 and the drain 4. Here, a voltage is applied to the select gate 20 provided on the source 2 side so that the substrate 1 is just turned on. By applying such a voltage, an electric field is concentrated between the substrate 1 and the selection gate 20. The electrons emitted from the source 2 become hot electrons due to the concentrated electric field. At this time, since a high voltage is applied to the control gate, some of the hot electrons are trapped on the source side of the N (nitride) film 10 in the ONO film. The state in which the electrons are trapped in the N (nitride) film 10 is the state in which "1" is written.

The case of reading out the electrons trapped in the N (nitride) film 10 will be described with reference to FIG. 1B. As described above, the electrons are trapped on the source 2 side of the N (nitride) film 10. Therefore, even when a high voltage is applied to the drain 4 at the time of reading, the depletion layer does not reach a portion where electrons are trapped. That is, as shown in FIG. 1B, even if the depletion layer 100 spreads in the vicinity of the drain 4, it does not spread to the source side of the N (nitride) film 10, and electrons are trapped in the N (nitride) film 10. ("
It is possible to accurately detect whether or not "1" has been written). Note that erasing is performed by emitting trapped electrons to the substrate 1.

Next, details of the operation of the trap type semiconductor memory of the present embodiment will be described using the equivalent circuit shown in FIG. Here, the cell C10 is a selected cell for writing, erasing and reading information, and other cells (cells C20, C
30 and C40) are non-selected cells (FIG. 8A). Figure 8
B shows the voltage applied to each row, column and part at each operation time point.

First, when writing information, 10V is applied to the control gate line CG1, 9V is applied to the bit line BL1, 1.5V is applied to the select gate line SG1, and 0V is applied to the others. At this time, in the selected cell C10, by applying 9V to the bit line BL1, electrons are ejected from the source 2 to the drain 4 and the channel 80 is formed (see FIG. 1A). Further, by applying a voltage of 1.5 V, at which the substrate is just turned on, to the select gate, an electric field is concentrated between the substrate 1 and the select gate 20. The electrons emitted from the source 2 due to this concentrated electric field become hot electrons. Further, since the control gate 14 channel is supplied with a high voltage of 10 V to the control gate 14, a part of the hot electrons is O 2.
It is trapped on the source side of the N (nitride) film 10 in the NO film. Thus, a part of hot electrons is trapped (“1” is written) in the N (nitride) film 10.

Thus, when "1" is written, the data shown in FIG.
The threshold value of the voltage required to form the channel 80 shown in FIG. By detecting the rise of this threshold value, it is detected that "1" has been written. That is, the sense voltage is applied to the control gate 14 as described above, and if a channel is not formed between the source 2 and the gate 4 and no current flows, it is detected that "1" is written.

Here, when the non-selected cell C20 is viewed, 10V is applied through the control gate line SG1 and 1.5V is applied through the select gate line CG1. However, since 0 V, which is the same potential as the source 2, is applied to the bit line BL2 and no channel is formed, there is no risk of erroneous writing. Further, with respect to the other non-selected cells C30 and C40, 0 V is applied to the selection gate line SG2 and the control gate line CG2, respectively, so that there is no risk of erroneous writing in cells other than the selected cell C10.

Next, the case of erasing the electrons trapped in the N (nitride) film 10 will be described. In this case, −15V is applied to each of the control gate lines CG1 and CG2, both the bit lines BL1 and BL2 are opened, and 0V is applied to the others. By applying a negative voltage to the control gate, an electric field opposite to the above-mentioned writing is generated. Therefore, the trapped electrons are FN (Fowler-Nor
heim) is drawn to the substrate 1 by tunneling and emitted. Thus, when the trapped electrons are extracted,
The threshold voltage required to form the channel 80 shown in FIG. 1A drops. By detecting the decrease in the threshold value, it is detected that the information "1" is not written from the N (nitride) film 10. That is, as described above, when the sense voltage is applied to form the channel 80 between the source 2 and the drain 4 and a current flows, the N (nitride) film 10 is formed.
Therefore, it is detected that the information "1" is not written.

Further, reading of information from the selected cell C10 will be described. When reading the information stored in the selected cell C10, 3V is applied to the control gate line CG1 as a sense voltage, 5V is applied to the select gate line SG1 and 2V is applied to the bit line BL1 to turn on the select gate. Here, the sense voltage is an intermediate value between the threshold value when electrons are trapped in the N (nitride) film 10 and the threshold value when electrons are not trapped. In addition to the above, 0V is applied.

When the selected cell C10 is in the written state, the channel 80 (see FIG. 1A) is not formed and no current flows between the source and the drain. Therefore, the bit line BL
The sense amplifier (not shown) connected to 1 cannot detect the current, and the selected cell C10 reads that it is in the written state. On the other hand, when the selected cell C10 is in the non-writing state, the above-mentioned channel 80 is formed between the source and drain. Therefore, a current flows between the source and drain, and this voltage is detected by the sense amplifier to read that the selected cell C10 is in the non-writing state.

Next, looking at the selected cell C20, a sense voltage of 3 V is applied to the control gate line CG1,
5V is applied to the select gate line SG1. However, since 0V is applied to the bit line BL2 and it is connected to the sense amplifier bit line BL1,
Reading is not performed in the non-selected cell C20.
Furthermore, in the other non-selected cells C30 and C40,
Since 0V is applied to each of the control gate line CG2 and the select gate line SG2, reading is not performed.

Thus, by writing information in the N (nitride) film 10 on the source side by the hot electron injection method and erasing by FN tunneling, accurate reading can be performed.

The structure and manufacturing method of the trap memory according to this embodiment will be described below with reference to the drawings. First, FIG.
A method of manufacturing the trap type memory shown in B will be described. The first O film 8 is formed on the substrate 1 (P well) by thermal oxidation. Next, N (nitridation) is performed on the first O film 8 by LPCVD.
Film 10 A film is formed. Next, the second O film 12 is formed on the N (nitride) film 10 by wet oxidation (FIG. 3A).
The first polysilicon film 13 is formed on the ONO film 30 thus formed (FIG. 3A). Next, the control gate 14 is formed by etching the first polysilicon film 13 as shown in FIG. 3B. When etching the first polysilicon film 13 to form the control gate 14, the ONO film 30 other than under the control gate 14 is removed (FIG. 3C). Thus, the ONO film 30 and the ONO film 30 formed on the substrate 1 are controlled. Gate 1
On the other hand, the oxide film 16 is formed by thermal oxidation so as to cover them (FIG. 3D). Next, a second polysilicon film 28 is formed on the oxide film 16 (FIG. 4A). The second polysilicon film 28 is etched back by reactive etching (RIE) which is anisotropic etching to form sidewalls 20 and 22 (FIG. 4B). Next, As (arsenic) is ion-implanted into the substrate 1 using the sidewalls 20 and 22 and the control gate 14 as a mask (FIG. 4B). After the implantation of As (arsenic), only the sidewall 22 is removed by etching.
Phosphorus is ion-implanted into the substrate using 0 and the control gate as a mask (FIG. 4C).

At this time, As which has already been imprinted on the substrate
(Arsenic) and phosphorus are almost duplicated in most places. However, only phosphorus exists in the substrate portion BS1 where the sidewalls 22 were (FIG. 5A). After phosphorus is injected, a BPSG film is formed as the interlayer film 18 (FIG. 5B). This BPSG is PSG (Ph
osoho-Silicate-Glass). Next, the interlayer film 1
Reflow 8. During this reflow, As (arsenic) and phosphorus implanted in the substrate 1 are thermally diffused, and as shown in FIG. 5B, the source 2 and LDD (Lightly-Doped-Drain).
The drain 4 of the structure is formed. That is, the substrate portion BS1 in which only phosphorus is implanted on the drain side has a lower concentration than the portion in which As (arsenic) and phosphorus are implanted, and is n-, and the other portion is n +, which is an LDD structure. Become. The LDD structure is a structure for relaxing the electric field near the drain 4.

After forming the source 2 and the drain 4 as described above, Al (aluminum) is deposited on the interlayer 18 and patterned to form a bit line (drain line) 25, and a passivation film (see FIG. Also formed on the bit line 25 (not shown) (FIG. 2).
B). In this way, the trap type semiconductor memory shown in FIG. 2B is manufactured.

Next, the structure of another embodiment of the trap type semiconductor memory according to the present invention is shown in FIG. 2A. Figure 2B above
2A, the memory of FIG.
The difference is that the NO film 30 is formed. However, both operate as a memory by performing the same operation. The manufacturing method of FIG. 2A will be described below.

The ONO film 30 is formed on the substrate 1 and
The steps up to the step of forming the first polysilicon film 13 on the film 30 and forming the control gate 14 by etching are the same as the above-described steps (see FIG. 3A and FIG. 6A). However, unlike the above-described manufacturing method, the ONO film 30 is not etched, and the oxide film 16 is formed on the ONO film 30 and the substrate 1 by thermal oxidation (FIG. 6A). Subsequent steps are the same as those in the method of manufacturing the trap type semiconductor memory shown in FIG.

A second polysilicon film 28 is formed on the formed oxide film 16 (FIG. 6B). The second polysilicon film 28 is etched back by reactive etching (RIE) which is anisotropic etching to form sidewalls 20 and 22 (FIG. 6C). Next, using the sidewalls 20 and 22 and the control gate 14 as a mask,
As (arsenic) is implanted into the substrate 1 (FIG. 6C).

After implanting As (arsenic), only the sidewall 22 is removed by etching (FIG. 7A).
Further, phosphorus is implanted into the substrate 1 by using the sidewall 20 and the control gate 14 as a mask (FIG. 7B). After implanting phosphorus, a BPSG film is formed as the interlayer film 18 (FIG. 7B). During the reflow of this BPSG film, the implanted A
S (arsenic) and phosphorus are thermally diffused, and the source 2 and the drain 4
Are formed (FIG. 7C). Also during this diffusion, the drain 4 side has the LDD structure as described above due to the difference in concentration between the portion containing only phosphorus and the portion into which phosphorus and arsenic have been implanted.

After forming the source 2 and the drain 4, the interlayer film 1
Al (aluminum) is deposited on 8 and patterned to form a bit line (drain line) 25, and a passivation film (not shown) is formed on the bit line 25 (FIG. 2A). Thus, FIG.
The trap type semiconductor memory shown in A is manufactured.

[0032]

In the semiconductor device according to the present invention, the side conductive layer is provided on the source-side electric path formable region so as to be insulated from the electric path formable region and at the side surface of the control electrode so as to be insulated from the control electrode. ing. That is, since writing is performed on the source side, even if a high voltage is applied to the drain side and the depletion layer spreads, it does not reach the source side.

Therefore, accurate reading can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing an operation outline of a semiconductor device (trap type semiconductor memory) according to the present invention.

FIG. 2 is a cross-sectional view showing a structure of a semiconductor device (trap type semiconductor memory) according to the present invention.

FIG. 3 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 2B.

FIG. 4 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 2B.

FIG. 5 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 2B.

FIG. 6 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 2A.

FIG. 7 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 2A.

8 is a diagram showing a state in which cells of the semiconductor device (trap type semiconductor memory) shown in FIG. 2 are combined. A is an equivalent circuit in which cells are combined, and B is a diagram showing an example of voltages at respective portions during writing, erasing, and reading.

FIG. 9 is a diagram showing an outline of write and read operations of a conventional semiconductor device.

[Explanation of symbols]

 1 ... Substrate 2 ... Source 4 ... Drain 10 ... N (nitride) film 14 ... Control gate 20 ... Select gate 80. .... Channel 100 ... Depletion layer

Claims (1)

[Claims] 1. A source region provided in a substrate, a drain region provided in the substrate so as to form an electric path formable region between the source region, and a trap film provided on the electric path formable region. , The control electrode provided on the trap film, the side conductive layer provided on the source-side electric path formable region and insulated from the electric path formable region, and on the side surface of the control electrode and insulated from the control electrode A semiconductor device comprising: