JPH06177341A - Mos type integrated circuit device having complementary inverter output stage - Google Patents

Abstract

PURPOSE:To repeat output signals different in output voltage level via the same port, by repeating an enable signal to one FET gate terminal of a first and a second complementary type inverters output stages corresponding with a first and a second driving stages, and repeating a data signal to the other FET gate terminal. CONSTITUTION:A high voltage supply circuit 26 consists of diodes 30, 31 to the anodes of which high voltages V3, VDD are supplied, and the cathodes connected output a voltage VH. A low voltage supply circuit 27 consists of diodes 32, 33. Low voltages V3, VSS are supplied to the respective cathodes. The anodes of the diodes 32, 33 are both connected and output a voltage VL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS integrated circuit device, and more particularly to an output stage (hereinafter simply referred to as a complementary inverter output stage) in which a pair of complementary FETs having mutually opposite conductive channels are connected in a push-pull manner. For short).

[0002]

2. Description of the Related Art FIG. 1 shows an example of a MOS integrated circuit device having a complementary inverter output stage. This MO
The S-type integrated circuit device has a function of relaying an LCD data signal for driving a liquid crystal display (hereinafter abbreviated as LCD) to a substrate terminal only in the presence of the LCD enable signal.

That is, the LCD data signal is a NAND
The LCD enable signal is supplied to one input terminal of the gate 1 and the NOR gate 2 directly to the other input terminal of the NAND gate, while being supplied to the other input terminal of the NOR gate 2 via the inverter 3. It The logic gate 4 including the NAND gate 1, NOR gate 2 and inverter 3 described above is driven by the high potential side power supply voltage VDD and the low potential side power supply voltage VSS supplied to this integrated circuit.

These power supply voltages VDD and VSS are converted by the power supply circuit 5 into power supply voltages V3 and V3SS having an absolute value three times larger than VDD and VSS, and FETs are converted.
It is supplied to the high potential side terminal and the low potential side terminal of the complementary inverter output stage constituted by 6 and 7, respectively. The output from the NAND gate 1 among the outputs from the logic gate 4 is supplied to the gate terminal of the FET 6 through the level shift circuit 8. The output of the NOR gate 2 is directly supplied to the gate terminal of the FET 7. In addition, the level shift circuit 8 uses the high voltage level VD from the NAND gate 1.
Convert D to V3.

The output line of the complementary inverter output stage is connected to a port (not shown) via a so-called pad or substrate terminal 9. An input terminal (not shown) of the LCD is connected to this port. The input terminal of the inverter 10 is connected to this board terminal, and the port is L
It is used not only as a CD output port but also as an input port.

[0006]

In such a conventional MOS type integrated circuit device, if the LCD output port is also used as the I / 0 output port, the LCD output voltage and the I / 0
Due to the voltage difference from the output voltage, the FET constituting the output stage is reverse-biased, which causes a problem.

Therefore, an object of the present invention is to provide an integrated circuit capable of relaying two output signals having different output voltage levels through the same port.

[0008]

According to a first aspect of the present invention, there is provided a MOS type integrated circuit device comprising a pair of FETs, each of which is provided on a substrate and has conductive channels of opposite conductivity.
A complementary inverter output stage and a pair of Fs each having a conductive channel provided on the substrate and having opposite conductivity.
A second complementary inverter output stage consisting of ET;
And a first independently driving a second complementary inverter output stage
And a second driving stage, wherein a single substrate output terminal to which output lines of the first and second complementary inverter output stages are commonly connected,
And a higher-potential power supply voltage among the first and second higher-voltage power supply voltages to be applied to the higher-potential-side power supply terminals of the second complementary type inverter output stage, respectively. Inverter output stage first bias voltage applying means for supplying to the conductive channel of the FET on the high potential side, and first and second low voltage sides to be applied to the low potential side power supply terminals of the first and second push-pull output terminals. Second bias voltage applying means for selectively supplying a power supply voltage having a lower potential of the power supply voltage to the conductive channel of the FET on the low potential side of the first and second complementary inverter output stages. It has a feature.

[0009]

In the MOS type integrated circuit device according to the present invention, independent information signals are relayed through two complementary inverter output stages in which output lines are connected to a common substrate terminal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiment circuit shown in FIG. 2 differs from the conventional circuit shown in FIG. 1 in the following points. That is, the logic gate 4
Output of the FET through the level shift circuits 8A and 8B.
It is relayed to gates 6 and 7. Level shift circuit 8
A and 8B respectively convert VDD input to V3 output,
Convert SS input to V3SS output. A logic gate 20 driven by the power supply voltages VDD and VSS is provided. The logic gate 20 is the logic gate 4
Similarly, the NAND gate 21, the NOR gate 22 and the inverter 23 are included. The output terminals of the NAND gate 21 and the NOR gate 22 are provided on the same substrate as the FETs 6 and 7 and have conductive channels of opposite conductivity types to form a second complementary inverter output stage F.
It is connected to the gate terminals of ETs 24 and 25.

Further, the FETs 6, 7, 24 and 25 are shown in FIG.
N provided P type substrate, as shown in ^-, p ^-, n ^-,
It is formed in each well region of p ⁻ . Therefore, FE
Conductive channel T6,24 each n ^- is in the form, FE
Conductive channel T7,25 each p ^- is a form. The voltage V is applied to the n ^-type conductive channels of the FETs 6 and 24.
H is applied as a bias voltage and p of FET7,25
^A voltage VL is applied to the negative conduction channel.

The above-mentioned power supply voltage VH is generated by the high voltage side power supply circuit 26 and is made equal to the higher one of the high potential side power supply voltages VDD and V3. Further, the power supply voltage VL is the low voltage side power supply circuit 27.
Generated by the low potential side power supply voltages VSS and V3S
It is made equal to the lower voltage of S.

4A and 4B show a high voltage side power supply circuit 26 and a low voltage side power supply voltage supply circuit 27.
The example of the concrete circuit of is shown. That is, the high voltage side power supply circuit 26 supplies the high voltage side power supply voltages V3 and V to the anodes, respectively.
The diodes 30 and 31 are supplied with DD, and the cathodes of the diodes 30 and 31 are connected together to output the voltage VH. That is, V3
When> VDD, VH = V3, and when V3 ≦ VDD, VH = VDD.

The low-voltage side power supply voltage supply circuit 27 is composed of diodes 32 and 33 whose cathodes are supplied with the low-power-side power supply voltages V3SS and VSS, respectively. The anodes of the diodes 32 and 33 are connected together to form a voltage. It is designed to output VL. That is, V3SS <VS
When S, VL = V3SS, and when V3SS ≧ VSS, VL = VSS.

By the action of the high voltage side power supply circuit 26, even if VDD is higher than V3, the FET6
There is no forward bias applied between the source and drain regions of 24 and the conductive channel. Similarly, due to the action of the low-voltage side power supply circuit 27, even when VSS has a lower potential than V3SS, there is no possibility that a forward bias is applied between the source and drain regions of the FETs 7 and 25 and the conductive channel. is there.

In the above-described embodiment, the substrate terminal which relays the LCD drive signal with V3 and V3SS as the output power supply voltage has the I / O with the power supply voltages VDD and VSS as the output power supply voltage.
This example is also used for relaying 0 data, but it is clear that the MOS integrated circuit device according to the present invention is effective if the output power supply voltages are different from each other.

[0017]

As is apparent from the above, the MOS type integrated circuit device according to the present invention is provided with two output stages, each of which is an FET having a pair of conductive channels of opposite conductivity type. Although the output line of the above is commonly connected to a single substrate terminal, the bias voltage to be applied to the conductive channel of each FET is the bias voltage of the high potential side of the complementary inverter output stage, whichever is higher. Since the lower low-side power supply voltage is the low-side bias voltage, the high-side power voltage and the low-side power voltage supplied to the two complementary inverter output stages are different from each other. However, no forward bias is applied between the conductive channel and the source / drain of the FET, and no problem occurs.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a conventional example.

FIG. 2 is a circuit diagram showing a MOS type integrated circuit device as an embodiment according to the present invention.

FIG. 3 is a cross-sectional view showing an example of a layout of FETs constituting a complementary inverter output stage of the MOS integrated circuit device of FIG. 2 in a substrate.

4 is a circuit diagram showing a specific circuit example of a high voltage side power supply circuit 26 and a low voltage side power supply circuit 27 of FIG.

[Explanation of symbols for main parts]

4,20 Logic gate 6,7 FE forming the first complementary inverter output stage
T 9 Common substrate terminal 24, 25 FET forming a second complementary inverter output stage 26 High-voltage side power supply circuit 27 Low-voltage side power supply circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication location H03K 19/0175 8941-5J H03K 19/00 101 F

Claims (4)

[Claims] 1. A first FET comprising a pair of FETs, each of which is provided on a substrate and has conductive channels of mutually opposite conductivity.
A complementary inverter output stage and a pair of Fs each having a conductive channel provided on the substrate and having opposite conductivity.
A second complementary inverter output stage consisting of ET;
And a first independently driving a second complementary inverter output stage
And a second driving stage, wherein a single substrate output terminal to which output lines of the first and second complementary inverter output stages are commonly connected, and the first and second driving stages are provided. The first and second complementary inverter output stages are alternatively selected from the first and second high-voltage side power source voltages to be applied to the high-potential-side power source terminals of the complementary inverter output stage. Bias voltage applying means for supplying to the conductive channel of the FET on the high potential side, and first and second low voltage side power sources to be applied to the low potential side power supply terminals of the first and second complementary inverter output stages The power source voltage having a lower potential among the voltages is alternatively selected.
And a second bias voltage applying means for supplying to the conductive channel of the FET on the low potential side of the complementary inverter output stage, the MOS integrated circuit device. 2. The first and second driving stages relay an enable signal to the gate terminal of one FET of the corresponding first and second complementary inverter output stages, respectively, and the gate terminals of the other FETs. The MOS type integrated circuit device according to claim 1, characterized by comprising a relay circuit for relaying a data signal to the memory. 3. The MOS type integrated circuit device according to claim 1, wherein each of the FETs is formed in a well region provided in the substrate. 4. The MOS integrated circuit device according to claim 1, further comprising a gate circuit provided in the substrate and having an input terminal connected to the substrate terminal.