JPH0616306B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and in particular, like a firing part of a data driven data processing device, one new data packet is generated from two data packets. The present invention relates to a data processing device.

(Prior Art) The Neumann type data processing device has drawbacks such as low speed and difficulty in parallel processing due to sequential processing. Therefore, recently, a data driven type (data flow type) data processing device has been proposed and realized. An example of such a data driven type data processing device is disclosed, for example, in Nikkei Electronics, pages 181 to 218, issued on April 9, 1984.

In a conventional system, a data packet is stored in a queuing memory from a data bus in order to detect a fire, and the identifier or identification data of the data packet stored in the queuing memory is searched to find a data packet of a partner to be a pair. I try to find.

(Problems to be Solved by the Invention) In a conventional system, it takes a very long time to store data in a queuing memory and search for identification data therein, and as a result, the speed of the entire data processing device is reduced. It was late.

Therefore, a main object of the present invention is to provide a data processing device which can find a partner's data packet to be paired faster.

(Means for Solving the Problems) In brief, the present invention is for transmitting a data packet including identification data including at least destination information, and is configured by using a shift register.
And the second data transmission line, the first and second data transmission lines, and the identification data detecting means for detecting the identification data included in the data packets transmitted respectively, and the identification data detecting means. The pair discriminating means for discriminating the data packet transmitted on the first and second data transmission paths and forming a pair by comparing the identification data, and the two data packets discriminated by the pair discriminating means for the first And a new data packet generating means for generating one new data packet by taking it out from the second data transmission path.

(Operation) Data packets are individually transmitted on the first data transmission line and the second data transmission line. The identification data detecting means extracts the identification data from the data packets transmitted on the respective data transmission paths. The pair discriminating means compares the two identification data thus extracted and finds a data packet to be paired when transmitted on the two data transmission paths. When the data packet of the other party to be a pair is detected, the data packet is given to the new data packet generating means from the first and second data transmission paths. The new data packet generation means processes the given two data packets in a predetermined manner to generate one new data packet. Then, this new data packet is introduced to the main data transmission line for subsequent processing such as arithmetic processing.

(Effect of the Invention) According to the present invention, since data packets to be paired with each other are detected while data is being transmitted on the first and second data transmission paths, the conventional queuing memory is used. In comparison, a new data packet can be generated faster. Therefore, the entire data processing device can be configured as a higher speed system.

If a self-propelled shift register is used as such a data transmission line, it can be easily coupled with an asynchronous main data transmission line, and the advantages thereof can be made even more effective when configured as a data-driven data processing device. Can be demonstrated.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

(Embodiment) FIG. 1 is a system conceptual diagram showing an example of a data processing apparatus in which the present invention can be embodied. The system 10 includes an asynchronous delay line ring 12 as a data transmission path. The asynchronous delay line ring 12 is provided with a data packet to be processed through a merging unit 14, and the processed data is output through a branching unit 16. To be done. Junction 1
The data packet given from No. 4 passes through the asynchronous delay line ring 12, is branched by the branching unit 18, and is given to the function storage unit 20. The data read from the function storage unit 20 is given to the asynchronous delay line ring 12 again via the merging unit 22.

The data packet provided from the function storage unit 20 includes, for example, as shown in FIG. 3A, a header HD and a plurality of data words DW _{1 to} DWn subsequent thereto. The header HD includes a processing code PC and a control code CC, and the processing code PC includes a code indicating the packet structure and a code indicating the processing content. As the code indicating the packet structure, for example, an order code indicating that it is a header or the last data word is given by the 17th and 16th 2 bits. The code indicating the processing content is particularly called an F code, and is used to specify the type of processing such as "+", "-", ... Or data replacement or insertion. The control code CC includes logical information such as physical destination information, node information due to the program structure, and color information.

The above-mentioned data packet transmitted by the asynchronous delay line ring 12 is given to the first loop-shaped data transmission line 28 forming the ignition unit 27 through the branching unit 24 and the merging unit 26, for example. Different data packets are taken into the second loop-shaped data transmission path 34 that constitutes the ignition unit 27 through different branching units 30 and merging units 32. The data packets provided to the first and second loop-shaped data transmission paths 28 and 34 are transmitted in the respective loops in opposite directions, and are provided to the ignition detection section 36 that constitutes the ignition section 27 together with these transmission paths. To be The firing detection unit 36 compares the control codes included in the respective data packets between the two data packets, and thereby the data packet existing on the first loop-shaped data transmission line 28 and the second data packet It is determined whether or not the data packet existing on the loop-shaped data transmission path 34 forms a pair, and one new data packet is generated based on the specific data packet detected as the data packet pair. The new data packet generated in this way is placed on the first loop-shaped data transmission line 28, for example, and is introduced again onto the asynchronous delay line ring 12 through the branching unit 38 and the merging unit 40.

The new data packet transferred on the asynchronous delay line ring 12 passes through the branch unit 42 and the arithmetic processing unit 44, for example.
The data to be processed included in the data packet is processed according to the processing code included in the header of the data packet. The data processed by the arithmetic processing unit 44 is merged into the asynchronous delay line ring 12 again via the merge unit 46. The processing result is either given to the function storage unit 20 again or output through the branching unit 16.

The system 10 is further provided with a control command processing unit and a color management unit.

The present invention is suitable as the ignition part 27 of the system 10 shown in FIG. However, the present invention is generally applicable to all data processing devices that need to find the other party's data to be paired and generate one new data from the paired data. I will point out that in advance.

FIG. 2 is a schematic block diagram for explaining the principle of the present invention. The first and second loop data transmission lines 28 and 34 are shift registers, preferably self-propelled shift registers. What is a self-propelled soft register?
As will be described in detail later, push-in and pop-out of data can be performed independently and simultaneously, and the pushed-in data will be automatically output if the register in the next stage is empty. In the output direction, therefore, in this and later-described embodiments, these first and second data transmission lines 2
8 and 34 are configured as asynchronous data transmission lines.

The two data transmission paths 28 and 34 have been described as constituting a loop in the system of FIG.
However, they do not necessarily have to be looped. However, as will be explained in detail later, it is desirable that at least one of them, and more preferably both of them, be configured as a loop.

Such first and second data transmission lines 28 and 3
Data packets having the configurations shown in FIG. 3 are transmitted to the respective 4 in the same direction or in the opposite directions. What is shown in FIG. 3 (A) is that one data word contains one processing target data, and what is shown in FIG. 3 (B) is that one data word has a plurality (two in this example). ) Processing target data is included.

A firing detection unit 36 is connected to the first and second data transmission paths 28 and 34, and the firing detection unit 36 includes a data packet pair detection circuit 48 and a new data packet generation circuit 50. Data packet pair detection circuit 48
Is a control code CC (FIG. 3) from the data packet transmitted through the first and second data transmission paths 28 and 34.
The identification data included in the above is extracted and the two extracted identification data are compared to detect the data packet of the other party to be a pair. When a data packet pair is detected, this data packet pair detection circuit 4
From 8, a signal is given to the new data packet generation circuit 50. Accordingly, the new data packet generation circuit 50
Then, each of the data packets including the detected identification data is captured. Then, one new data packet is generated from the two captured data packets and is output.

More specifically, as shown in FIG. 4, the data packets DP1 and DP2 having the configuration shown in FIG.
Are transmitted on the first and second data transmission paths 28 and 34, respectively. From these data transmission paths 28 and 34, identification data ID1 and ID
Data including 2 is provided to the data packet pair detection circuit 48. Then, the two identification data ID1 and ID2 are extracted and compared. These two identification data I
If D1 and ID2 have a certain relationship, for example, if the node information and the like in the program structure match, the fact is detected by the comparison circuit.
In the data packet pair detection circuit 48, in this way,
The data packets DP1 and DP2 are identified as being paired with each other. New data packet generation circuit 50
Then, the data packet DP1 thus identified
And DP2 are read from the first and second data transmission lines 28 and 34, respectively, and a new one data packet DP is generated. This new data packet is
It has a data packet structure as shown in FIG.

Further, as shown in FIG. 5, data packets DP1 and DP2 having a structure as shown in FIG. 3B are transmitted on the first and second data transmission paths 28 and 34, respectively. And As in the case of FIG. 4, when the identification data ID1 and ID2 included in the data packets DP1 and DP2 are compared and a certain relation therebetween is detected, the new data packet generation circuit 50
One new data packet DP as shown in FIG. 5 is generated. In the example shown in FIG. 5, the new data packet DP has the structure shown in FIG. 3 (B).

FIG. 6 is a block diagram showing an embodiment of the present invention.
In this embodiment, the first and second data transmission lines 28 and 34 are both configured as a self-propelled shift register. The self-propelled shift register that constitutes the first data transmission line 28 includes a plurality of continuously connected parallel data buffers B _{1 to} B ₅ and C elements (Coincident) corresponding to the respective parallel data buffers B _{1 to} B _5. Element) C
Including _{1 to} C ₅ . Similarly, the second data transmission line 34
The self-propelled shift register that comprises the parallel data buffers B _{11 to} B ₁₅ and C elements C _{11 to} C ₁₅ corresponding to the parallel data buffers B _{11 to} B ₁₅ are continuously connected.

Here, with reference to FIG. 7 and FIG. 8, the C element constituting the asynchronous self-propelled shift register will be described. C
Element C comprises six terminals _T 1 through T _6, the terminal _{T 1} is given a signal from the subsequent C element TRI (Transfer In), signal to the subsequent stage of the C-element from the terminal _{T 2} AKO (A
cknowledge Out) is output. From the terminal _{T 3} signal TRO (Transfer Out) is output to the preceding C-element, the signal from the preceding C-element from the terminal _{T 4} AKI (Ac
knowledge In) is given. The signal TRO is
It is given to the corresponding parallel data buffer as a transfer command signal. Then, the signal AKI is given as an empty signal of the preceding parallel data buffer.

The terminal T ₅ is supplied with the reset signal RESET, and the terminal T ₆ is supplied with the stop signal STOP.

In the circuit of FIG. 7, the reset signal RE is applied from the terminal T _5.
When SET is applied, it is inverted by the inverter and four NAND gates G ₁ , to which this signal is applied,
The outputs of G ₄ , G ₁₁ and G _{14 all} become high level. The outputs of the NAND gates G ₁ , G ₄ , G ₁₁ and G ₁₄ are at the high level, and therefore the outputs of the NAND gates G ₃ and G ₁₃ receiving it are both at the low level. Output signal AK high level of the NAND gate _{G 4}
It becomes O and is given as a signal AKI from the terminal T ₂ to the C element in the subsequent stage. This is a signal indicating the empty state of the preceding parallel data buffer. At this time, if the data has not arrived yet, the signal TRI to the terminal T ₁ is at the low level. When the reset signal RESET to the terminal T ₅ is released, the output of the inverter goes high,
Whereas the signal from the NAND gate G ₁₄ AK 'is also a high level, this state is the initial state.

In the initial state, therefore, the two inputs of each of the NAND gates G ₁ and G ₁₁ are at the high level, and one input of the OR gates G ₂ and G ₁₂ is at the high level. Therefore, the two inputs of the NAND gates G ₃ and G ₁₃ are both at the high level, and therefore the outputs of the NAND gates G ₃ and G ₁₃ are both at the low level. That is, the signal TR 'and the terminal T
The signal TRO from ₃ is at low level. The inputs of the NAND gates G ₄ and G ₁₄ are low level, high level and high level, respectively, and the outputs of the NAND gates G ₄ and G ₁₄ are high level, respectively.

When data is transferred and the signal TRI from the C element in the subsequent stage to the terminal T ₁ changes to high level as shown in FIG. 8, all three inputs of the NAND gate G ₁ become high level, and its output. Becomes low level. Then, in a high level as shown in output or signal TR 'is Figure 8 of NAND gate G _3, the NAND gate G
The output of ₄ becomes low level. 'When a high level, the output of the NAND gate _{G 11} goes low, the output TRO is high level of the NAND gate _{G 13,} the output AK of the NAND gate _{G 14'} signal TR becomes a low level. The output of the NAND gate _{G 4} and _{G 14} are returned to the input of the NAND gate _{G 3,} and _{G 13,} respectively, the output of NAND gate _{G 3,} and _{G 13} is locked in the high level state. In this way, the terminal T _2, as shown in FIG. 8
Signal AKO from LOW goes low, and the fact that the data has been transferred to the parallel data buffer corresponding to this C element C, that is, the transfer of data is no longer accepted in this state is transmitted to the C element in the subsequent stage. Further, the output of the NAND gate G ₁₃ is at a high level, and a high level signal TRO is given to the C element of the previous stage from the terminal T ₃ . This high level signal TRO is given as a transfer command to the corresponding parallel data buffer, and the data in the parallel data buffer is sent to the preceding stage.

When the signal AKO becomes low level, the signal TRI becomes low level as shown in FIG. 8, so that the output TR ′ of the NAND gate G ₁ returns to high level. Further, as described above, 'by changes to the low level, the output AKO of the NAND gate _{G 4} are returned to the high level, the output TR of the NAND gate _{G 3'} output AK of the NAND gate _{G 14} returns to the low level.

When the signal AKO from the C element in the previous stage, that is, the signal AKI given from the terminal T ₄ changes from the high level to the low level, that is, when the empty space of the parallel data buffer in the previous stage is extracted. , OR Gate G ₁₂
Input goes low, since calculation No. TR 'is also low, the output of the OR gate G ₁₂ also becomes a low level. At this time, since the output of the NAND gate G ₁₃ is at a high level, the output of the NAND gate G ₁₄ is changed to the high level. Therefore, Nand Gate G
The input of ₁₃ becomes high level and this NAND gate G
The output of ₁₃ changes to low level. In this way, the same state as the initial state is restored.

If the signal AKO from the C element in the previous stage, that is, the signal AKI from the terminal T ₄ remains at the low level, that is, if the parallel data buffer corresponding to the C element in the previous stage is not yet empty, the NAND gate NAND gate Since one input of G ₁₁ remains at low level, even if the signal TRI from the terminal T ₁ is given as high level and the signal TR ′ changes to high level, the NAND gate G
_{Since 11} does not operate and the signal TRO does not become high level, acceptance of data from the subsequent stage is rejected, so that data cannot be transferred to the parallel data buffer corresponding to this C element in that state.

In addition, the stop signal STOP is supplied to the C element C from the terminal T _6.
Is given, the high level signal is
₅ to the NAND gate G ₁₃ . Therefore, it is given to this NAND gate G ₁₃ . Accordingly, the output of the NAND gate G ₁₃ goes low, the signal TRO from the terminal T ₃ becomes a low level in this state, is transmitted to the front stage of the C elements, the data transfer is stopped.

Thus, as shown in FIG. 6, the parallel data buffers B _{1 to} B ₅ and the C elements C _{1 to} C ₅ and the parallel data buffers B _{11 to} B ₁₅ and the C elements C _{11 to} C ₁₅ respectively receive data. An asynchronous self-propelled shift register for the transmission lines 28 and 34 is configured.

Returning to FIG. 6, respective parallel data buffers B ₄ constituting the first and second data transmission lines 28 and 34.
And B ₁₄ to parallel data buffers B ₃ and B ₁₃
A data line extends from the data transmission path to the data packet to the identification data detecting circuits 52 and 54 included in the data packet pair detecting circuit 48. The identification data detection circuits 52 and 54
Then, the identification data is extracted from the header (FIG. 3) of the data packet and is supplied to the comparison circuit 56. The comparison circuit 56 compares the two pieces of identification data given to each other to determine whether they match or not. When the comparison circuit 56 detects the coincidence of the two identification data, the data packet to be paired is discriminated by the detection, and the control signal informing the fact is sent to the new data packet generation circuit 50.
Given to.

Transmission lines extend from the parallel data buffers B ₃ and B ₁₃ forming the first and second data transmission lines 28 and 34 to the parallel data buffers B ₂ and B ₁₂ to the new data packet generation circuit 50. . In the new data packet generation circuit 50, based on the coincidence signal or the control signal from the comparison circuit 56, a specific data packet to be a discriminated pair is fetched through the data packet line. Then, in the new data packet generation circuit 50,
The two data packets are combined to form one new data packet. The new data packet D generated by the new data packet generation circuit 50 in this way
P (FIG. 4 or FIG. 5) is transmitted through the new data packet line, for example, to the main data transmission line 12 for later processing.
(FIG. 1) to be sent to another processing circuit.

In the embodiment shown in FIG. 6, identification data detection circuits 52 and 54 provide identification data within a relatively short time during which data packets are sent from parallel data buffers B ₄ and B ₁₄ to parallel data buffers B ₃ and B _13. Once detected, the comparison circuit 56 must compare it within that time. Therefore, a detection error may occur depending on the data transmission rate of the data transmission paths 28 and 34.

Therefore, it can be considered that the identification data detection circuits 52 and 54 hold the identification data of the data packet for a certain period of time.

FIG. 9 is a schematic block diagram showing another embodiment of the present invention. The firing unit 27 of this embodiment includes a firing detection unit 36 connected to the first and second data transmission lines 28 and 34, as in the previous embodiment of FIG. The firing detection unit 36 includes a data packet pair detection circuit 48 and a new data packet generation circuit 50. The data packet pair detection circuit 48 includes an identification data detection circuit 52 for detecting identification data from a data packet transmitted on the first data transmission path 28 and a data packet transmitted on the second data transmission path 34. An identification data detection circuit 54 for detecting the identification data from is included. The two identification data thus detected are compared by the comparison circuit 56. In the comparison circuit 56, the new data packet generation circuit 50 detects when the two match or when there is a certain relationship.
Give a control signal to.

In this embodiment, the first and second data transmission lines 28 and 34 have a fixed length of data packet pair detection section 2.
8a and 34a, and the same identification data is taken out from the data packet pair detection sections 28a and 34a for a relatively long time so that the comparison in the comparison circuit 56 becomes easier.

FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to the embodiment shown in FIG. In this FIG.
First to detect identification data from the first data transmission line 28
It should be noted that, although only the identification data detection circuit 52 of No. 1 is shown and described, the identification data detection circuit 54 for detecting the identification data from the second data transmission line 34 has the same configuration.

The self-propelled shift register that constitutes the first data transmission path 28 includes parallel data buffers B ₀₁ and B ₀ that are vertically connected.
-B ₄ and their associated C elements C ₀₁ , C ₀ -C
Including ₄ . Each parallel data buffer B ₀₁ , B ₀
The 17th bit of .about.B _4, a header signal line HSL,
The tail signal line TSL is connected to the 16th bit. Parallel data buffers B ₀₁ and B ₀
Header signal line _{HSL 11} between is provided to the D terminal of the D flip-flop 60, the header signal line _{HSL 12} between the parallel data buffer _{B 3} and _{B 4} are OR gate 6
2 to the D input of the D flop 64. The tail signal line TSL ₁₂ between the parallel data buffers B ₃ and B ₄ is provided to the D input of the D flip-flop 68 through the OR gate 66.

C is used as the clock input of the D flip-flop 60.
A signal TRO from element C ₀₁ is provided. An OR gate 70 is connected to the reset input of the D flip-flop 60.
An initial reset signal is given to the output terminal through the output terminal Q and its output Q is given. The output Q of D flip-flop 60 is also provided, along with an initial reset signal, to the respective reset inputs of D flip-flops 64 and 68 through OR gates 72 and 74. The output Q of the D flip-flop 64 is applied to the other input of the above-mentioned OR gate 62 whose output is applied to its own D input, and is also applied to one input of the AND gate 76. The other input of the AND gate 76 is supplied with the output Q of the D flip-flop 68, and this output Q is further supplied with its output to its own D input.
6 is provided to the other input.

A header signal line is taken out from the transmission path from the parallel data buffer B ₄ to the parallel data buffer B ₃ , and this header signal line is given to the register 78. This register 7
The output Q of the D flip-flop 64 is given to the clock input of 8. The output of the register 78 is used as the detected identification data in the comparison circuit 56 (the sixth circuit).
Given).

In the initial state, a high level initial reset signal is applied. This initial reset signal is transmitted to the OR gate 70,
D flip-flops 60, 6 through 72 and 74
The D flip-flops 60, 64 and 68 are reset and the respective data Q are at a low level. This state is the initial state.

When free of the parallel data buffer B ₃ is detected by the C-element C ₃ of the relevant, from the parallel data buffer B _4, data bucket to the parallel data buffer B ₃ is started to be transferred. When a data packet, that is, its header, is transferred from the parallel data buffer B ₄ to the parallel data buffer B ₃ , the header signal line HSL ₁₂ between them becomes high level. With the start of such data packet transfer, the signal TRO from the C element C ₃ changes from low level to high level. Then, this high level signal is applied to the clock inputs of the D flip-flops 64 and 68, and the high level of the header signal line HSL _{12 applied} to the D input of the D flip-flop 64 is applied to the D flip-flop 64. When written, the output Q of the D flip-flop 64 changes from low level to high level. The high level output from the D flip-flop 64 is given as an enable signal for the register 78, and accordingly, the identification data included in the header output from the parallel data buffer B ₄ is latched in the register 78. Then, also, the header is transmitted to the parallel data buffer B _3.

After that, the D input of the D flip-flop 64 is fixed to the high level by the OR gate 62, and its output Q is held at the high level until the reset signal R comes next.

After that, data transfer between parallel data buffers progresses,
The last data word DW (FIG. 3) of the data packet begins to be transferred from parallel data buffer B ₄ to parallel data buffer B ₃ . At this time, the tail signal line TSL turns to a high level, and the C element C ₃ eventually becomes a high level signal T.
Output RO. This high level signal is applied to the clock inputs of the D flip-flops 64 and 68, and at this time, the high level of the tail signal line TSL is applied to the D input of the D flip-flop 68 through the OR gate 66. Therefore, the output Q of the D flip-flop 68 becomes high level at the timing when the signal TRO of the C element C ₃ becomes high level, and the last data word is given to the parallel data buffer B ₃ . Since the D input of the D flip-flop 68 is given the high level of its output Q, the D flip-flop 68 is held at the high level until the next reset signal is given.

At the moment when the outputs Q of the D flip-flops 64 and 68 both become high level, the output of the AND gate 76 becomes high level, and the stop signal STOP is given to the C element C ₃ .
(Fig. 7) is given. Therefore, the next data packet cannot be transferred from the parallel data buffer B ₄ to the parallel data buffer B ₃ until the next stop signal, that is, the output of the AND gate 76 returns to the low level.

After that, when the previous header is transferred to the parallel data buffer B ₀ , the header signal line HSL ₁₁ associated therewith becomes high level. When the signal TRO of the C element C ₀₁ becomes high level, the output Q of the D flip-flop 60
Changes from low level to high level, and its header is further transferred to the parallel data buffer B ₀₁ in the preceding stage.

When the output Q of the D flip-flop 60 becomes high level, a high-level reset signal is given to the D flip-flop 64 through the OR gates 72 and 74. Therefore, both the outputs Q thereof become low level, that is, the output of the AND gate 76, The stop signal for C element C ₃ also goes low. Therefore, the transfer is permitted in the new data packet to the parallel data buffer B ₃ at this point, D flip-flop 60 itself is reset through the next moment the OR gate 70, the circuit 48 returns to the initial state.

The identification data previously latched in the register 78 is until the header of the next data packet is output from the parallel data buffer B ₄ to the parallel data buffer B ₃ , that is, the header signal line HSL ₁₂ becomes high level again. Held up. Therefore, in the embodiment shown in FIG. 10, the identification data provided to the comparison circuit 56 (FIG. 9) is retained until the data is transferred between the parallel data buffers of four stages, and the identification data in the comparison circuit 56 are compared with each other. It becomes easier to compare.

FIG. 11 is a block diagram showing another example of the identification data detection circuit applicable to the embodiment of FIG. Similar to FIG. 10, FIG. 11 also shows and describes only the first identification data detection circuit 52 for extracting the identification data from the first data transmission line 28.

In FIG. 11, the identification data detection circuit 52 includes a parallel data buffer B ₂ , which is included in the first data transmission line 28.
It includes a multiplexer 58 that receives data from B ₃ , B ₄ and B ₅ . That is, the multiplexer 58 has
When a data packet is transferred from the subsequent parallel data buffer to the previous parallel data buffer, the outputs of the four parallel data buffers B _{2 to} B ₅ are input.

The header signal line HSL is connected to the 17th bit of each of the parallel data buffers B _{1 to} B ₅ , that is, one bit of the order code. The header signal line HSL ₁ between the parallel data buffers B ₁ and B ₂ is applied to the multiplexer 58, inverted by an inverter, and applied to one input of the AND gate G ₁ . Header signal line HSL ₂ connected between parallel data buffers B ₂ and B ₃ is applied to the other input of AND gate G ₁ . The output of the AND gate G ₁ is given to the multiplexer 58, inverted by an inverter and given to one input of the AND gate G ₂ . Header signal line HSL ₃ connected between parallel data buffers B ₃ and B ₄ is applied to the other input of AND gate G ₂ . The output of the AND gate G ₂ is given to the multiplexer 58, inverted by an inverter, and given to one input of the 2-input AND gate G ₃ .
The other input of the AND gate G ₃ has a header signal line HS connected between the parallel data buffers B ₄ and B _5.
The output of L ₄ is provided and its output is multiplexer 58.
Given to.

These header signal line HSL ₁ and AND gate G ₁ to
The output of G ₃ is applied as an enable signal to a corresponding latch circuit (not shown) included in multiplexer 52.

From the multiplexer 58, the identification data extracted from the first data transmission line 28 is given to the comparison circuit 56 (FIG. 6) through the identification data line.

In the initial state, all header signal lines HSL ₁ to
HSL ₄ is at low level. When the header of the data packet is transferred from the subsequent parallel data buffer to the parallel data buffer B ₅ , the header signal line HSL ₄ becomes high level. On the other hand, the header signal line HSL ₃ between the parallel data buffers B ₄ and B ₃ is still low level, and therefore the output of the AND gate G ₂ is low level. Since this low level is inverted and given to the AND gate G ₃ , at this time, a high level is output from this AND gate G ₃ .

When the output of the AND gate G ₃ becomes high level, the corresponding latch circuit included in the multiplexer 58 is enabled, and the identification data from the identification data line between the parallel data buffers B ₅ and B ₄ is latched in the latch circuit. It

After that, when the empty space of the parallel data buffer B ₄ is detected by the C element C ₅ , the header of the data packet is transferred from the parallel data buffer B ₅ to this parallel data buffer B ₄ . Accordingly, the header signal line HSL ₃ becomes high level, and the output of the AND gate G ₂ becomes high level in the same manner as the AND gate G ₃ . The high level output of the AND gate G ₂ is inverted and the AND gate G ₃
Therefore, the output of the AND gate G ₃ changes to the low level. On the other hand, the AND gate G ₂ functions as an enable signal for the corresponding latch circuit included in the multiplexer 58, and the identification data included in the header transferred from the parallel data buffer B ₄ to the parallel data buffer B ₃ is fetched at that timing.

By repeating this, the parallel data buffer B ₂
When the header of the data packet is transferred from the parallel data buffer B ₃ , the header signal line HSL ₁ becomes high level. Therefore, the output of the AND gate G ₁ becomes low level, like the AND gates G ₂ and G ₃ . When the header signal HSL ₁ goes high, the corresponding latch circuit included in the multiplexer 58 is enabled, and the identification data included in the data packet from the parallel data buffer B ₂ is written into the latch circuit.
That is, the same identification data is sequentially written in the four latch circuits (not shown) of the multiplexer 58 while the data packet is transferred in the four registers. Therefore, the same identification data continues to be output from the multiplexer 58 during that period. In this way, the multiplexer 58 can be used to hold the identification data for a certain period of time. Thus, in this embodiment, when one of the header signal line HSL ₁ ~HSL ₄ is in the high level, the identification data present in most pre-stage of which is selected.

Parallel data from the buffer B ₂ of data packet header is transferred to the parallel data buffer B ₁ at the first stage, the data word other than subsequent headers in parallel data buffer B ₂ is transferred, the header signal line HSL ₁ is low again level, and therefore, when one of the header signal line _HSL 1 _{~HSL 4} by the header of a subsequent data packet is at the high level, the header signal line _HSL 1 _{~HSL 4} by the circuit arrangement described so far Among them, the identification data existing in the frontmost stage is selected.

In the example of FIG. 10, while the identification data detection circuit holds the identification data in a certain data packet, the data transfer of another data packet in the data packet pair detection section of the corresponding data transmission path is stopped. Although time is wasted, the example of FIG. 11 is efficient because the data shift of the data transmission line is not stopped.

It should be noted that in the example of FIG. 11, the number of stages of the parallel data buffer in which the multiplexer 58 receives the data can be set arbitrarily according to the required time.

FIG. 12 is a block diagram showing another embodiment of the present invention. The firing unit 27 of this embodiment includes a data packet pair detection circuit 48 and a new data packet generation circuit 50,
In particular, the new data packet generation circuit 50 has a feature. The new data packet generation circuit 50 of this embodiment includes a stop circuit 80, a merging circuit 82, and a packet changing circuit 84. The stop circuit 80 includes a data packet pair detection circuit 48.
A match signal is supplied from the comparison circuit 56 (FIG. 6) included in FIG. The stop circuit 80 further includes a header signal line H from the parallel data buffers B ₃ and B ₄ included in the self-propelled shift register forming the first data transmission line 28.
The header signal line from the SL ₂₁ and the header signal line HSL ₂₂ between the parallel data buffers B ₁₃ and B ₁₄ of the self-propelled shift register forming the second data transmission path 34
The header signal from is given. Furthermore, the C element C ₃ corresponding to the parallel data buffers B ₃ and B ₁₃ respectively.
And the signal TRO from C ₁₃ is provided. The stop circuit 80 gives a stop signal STOP (FIG. 6) to the C elements C ₂ and C _{12 in the} preceding stage, and a merge control signal to the merge circuit 82. The packet combination circuit 84 is inserted in the first data transmission line 28,
First data transmission line 28 and second data transmission line 34
From the data packet pair given by the above, one new data packet is recombined, and the recombined new data packet is made to flow on the first data transmission line 28. The merging circuit 82 controls the merging of the new data packet into the first data transmission path 28 by the packet reassembling circuit 84.

Referring to FIG. 14, the stop circuit 80 includes an OR gate 86.
And a comparator circuit 5 for one input of this OR gate 86.
The match signal from 6 (Fig. 6) is given and its output is 2
Two AND gates 88 and 90 are applied to one input of each. The other input of the AND gate 88 is the 13th
The header signal from the header signal line HSL ₂₁ shown in the figure is applied, and the other input of the AND gate 90 is applied with the header signal from the header signal line HSL ₂₂ . The outputs of AND gates 88 and 90 are both provided as D inputs of D flip-flops 96 and 98 through OR gates 92 and 94, respectively. The clock input of the D flip-flop 96 is given the signal TRO from the C element C ₃ associated with the first data transmission line 28, and similarly the clock input of the D flip-flop 98 is supplied with the second signal. The signal TRO from the C element ₁₃ of the data transmission path 34 is given. The outputs Q of D flip-flops 96 and 98, respectively, are OR gates 92 and 94.
Is given as its own D input through
It is provided as the residual input to OR gate 86.

The output Q of the D flip-flop 96 is directly applied to one input of each of the AND gates 100 and 102, inverted by an inverter and applied to one input of the AND gate 104. The output Q of the D flip-flop 98 is the AND gate 100 as it is.
And the other inputs of 104 and 104, and inverted by an inverter and applied to the other input of AND gate 102. The output of the AND gate 102 is given to the C element C ₂ of the first data transmission line 28 as a stop signal,
The output of the AND gate 104 is given to the C element C ₁₂ of the second data transmission line 34 as the stop signal STOP. Further, the output of the AND gate 100 is given to the merging circuit 82 as a merging control signal.

The D flip-flop 98 has the first data transmission line 28
Signal AKI given to the above-mentioned C element C ₂ included in
Are applied to the reset inputs of the D flip-flops 96 and 98 as stop release signals.

The merging circuit 82 receives the merging control signal from the stop circuit 80, and the merging control signal is inverted and the AND gate 106,
Given to one input of 108 and 116,
It is given as it is to one input of the AND gate 114.
To the other input of the AND gate 106, the signal TRO from the C element C ₂ included in the first data transmission line 28 is given. The other input of the AND gate 108 has a second
The signal TRO from the C element C ₁₂ included in the data transmission path 34 of FIG. The output of the AND gate 106 is given to one input of the OR gate 112, and the other input of the OR gate 112 has C element C ₂ and C element C _2.
The signal TRO from ₁₂ and the output of the AND gate 110 to which the merge control signal is given are given. The output of the OR gate 112 is given to the C element further upstream of the first data transmission line 28. Similarly, AND gate 108
Is also given to the C element in the previous stage included in the second data transmission path 34. The signal AKO from the C element included in the first data transmission line 28 is given to the other input of the AND gate 114, and the signal AKO from the C element at the previous stage of the second data transmission line 34 is given. The outputs of these two AND gates 114 and 116 are both passed through the OR gate 118 and the second data transmission line 34.
C element C ₁₂ included in

When the header of the data packet is transferred to the parallel data buffer B ₄ of the first data transmission line 28, the header signal line H
When SL ₂₁ becomes high level and a high level coincidence signal is obtained from the comparison circuit 56 (FIG. 6) included in the data packet pair detection circuit 48 at this time, both inputs of the AND gate 88 of the stop circuit 80 become high. Level, D
The D input of the flip-flop 96 becomes high level. Then, when the signal TRO from the C element C ₃ corresponding to the parallel data buffer B ₃ becomes high level, that is, when this header is transferred to the parallel data buffer B ₃ ,
The D flip-flop 96 is set, and its output Q becomes high level. Further, when the header is transferred to the parallel data buffer B ₁₄ included in the second data transmission path 34, the header signal line HSL ₂₂ becomes high level, and when the above-mentioned coincidence signal is obtained at this time, the C element C ₁₃ The D flip-flop 98 is set according to the signal TRO from. That is, the D flip-flops 96 and 98
Is a parallel data buffer B _{3 of} the first data transmission line 28.
And the parallel data buffer B of the second data transmission line 34
_It is set to ₁₃ when the header of the data packet to be paired arrives, and is set from whichever comes first. Then, the D flip-flop that has not been set is set whenever the header arrives. That is, the D flip-flops 96 and 98 hold the coincidence signal from the comparison circuit 56 of the data packet pair detection circuit 48.

If one D flip-flop 96 is set and the other D flip-flop 98 is not yet set, that is, the corresponding header has not arrived at the parallel data buffer B ₁₃ of the second data transmission line 34, Both inputs of the AND gate 102 become high level, so that the stop signal STOP to the terminal T ₆ (FIG. 7) of the C element C ₂ becomes high level. Then, the C element C ₂ is stopped.

Conversely, when the D flip-flop 98 is set and the D flip-flop 96 is not set, that is, when the corresponding header has not arrived at the first data transmission path 28, the stop signal STOP is output from the AND gate 104. Therefore, the data transmission on the second data transmission path 34 is stopped.

In this way, the stop circuit 80 synchronizes the packets to be paired.

Next, in a state in which the two D flip-flops 96 and 98 are both set, that is, in a state in which the corresponding headers have both arrived at the parallel data buffers B ₃ and B ₁₃ ,
One of the inputs of the AND gates 102 and 104 becomes low level, and the stop signal STOP becomes low level. Then, the two inputs of the AND gate 100 both become high level, and the high level merge control signal is output to the merge circuit 82. Therefore, the merging circuit 8
One input of the AND gate 114 included in 2 becomes high level, and conversely, one input of the AND gate 116 becomes low level. Therefore, from the OR gate 118, the signal AK from the C element included in the first data transmission line 28, not from the C element of the second data transmission line 34.
O is output, and this signal is C of the second data transmission line 34.
Presented as signal AKI of element C ₁₂ . At the same time, one input of the AND gate 108 becomes low level, and the signal TR from the C element C ₁₂ to the C element in the previous stage is further increased.
O becomes low level. Further, since the merge control signal is at the high level, the output of the AND gate 110 is validated as the input of the OR gate 112. Therefore, when the signals TRO of both the C element C _{2 of} the first data transmission line 28 and the C element C ₁₂ of the second data transmission line 34 are both at the high level, the OR gate 112 causes the first data transmission line 28 to move. A high-level signal TRO is applied to the C element in the preceding stage. Therefore, after that, the data packet of the second data transmission path 34 is given to the packet reassembling circuit 84 provided in the first data transmission path 28,
It disappears from the second data transmission path 34.

In the data packet repacking circuit 84, the packet repacking is performed and a new data packet is first
Of the stop circuit 80 after being brought on the data transmission line 28 of
Is supplied with a high-level stop release signal, and both D flip-flops 96 and 98 are reset. Therefore, new data packet generation circuit 50 is disabled.
In this way, a match of the data packets to be paired is detected and one new data packet is generated.

FIG. 15 is a block diagram showing another embodiment of the present invention. This FIG. 15 embodiment is effective in preventing so-called "deadlock" in which the data packet to be paired is permanently not found.

More specifically, in both the embodiments shown in FIGS. 6 and 9, as shown in FIG. 16, one data packet pair detection section 28a is provided in each of the two data transmission lines 28 and 34. And 34a are only specified. When each has only one data packet pair detection section, as shown in FIG. 16, the respective data transmission paths 28 and 34 are data-shifted in mutually opposite directions, and the two data transmission paths 28 and 34 are provided. When the data packets are circulated at the same transfer rate and in the order shown in the drawing, each data packet pair detection section 2
The same identification data, for example "A ₁ ", cannot be detected simultaneously in 8a and 34a. Therefore, in such a case, "deadlock" occurs.

On the other hand, as shown in FIG. 17, if a plurality of data packet pair detection sections 28a ₁ , 28a ₂ , ... Are defined in at least one of the data transmission paths 28 (or 34), “deadlock” occurs. Is effectively avoided. Because
Even if the data are transferred in the opposite directions in the illustrated order at the same transfer rate in both the data transmission paths 28 and 34, the data packet pair detection section 34 of the data transmission path 34.
opportunity to present the other data packet pair detection section 28a ₁ and either the same identification data "A _2" of 28a ₂ is when there is identification data for example "A _2" in a is because necessarily occur. Therefore, by defining a plurality of data packet pair detection sections on either one of the data transmission paths, "deadlock" can be avoided.

In FIG. 15, a plurality of data packet pair detection sections 28a ₁ , 28a ₂ , ... Are provided on the _first data transmission line 28.
, 28an are provided, and one data packet pair detection section 34a is defined in the second data transmission path 34.
Data packet pair detection section 2 of the first data transmission line 28
8a ₁ to 28an are provided with a plurality of identification data detection circuits 52 _{1 to} 52n, while one identification data detection circuit 54 is provided corresponding to the data packet pair detection section 34a of the second data transmission path 34. It is provided. And the first
Identification data detection circuit 52 related to the data transmission path 28 of
The identification data from _{1 to} 52n are individually applied to one input of the corresponding comparison circuits 56 _{1 to} 56n. The identification data from the identification data detection circuit 54 of the second data transmission path 34 is commonly given to the other inputs of the comparison circuits 56 _{1 to} 56 n. Then, when the matching of the identification data is detected in each of the comparison circuits 56 _{1 to} 56 n, the new data packet generation circuit 5 is detected from the corresponding comparison circuit.
A control signal is given to 0. In response to the match signal, the new data packet generation circuit 50 creates one new data packet from the two matched data packets, for example, in the same manner as in the previous embodiment of FIG.

In the embodiment shown in FIG. 15, the two data transmission lines 28 and 34 are both shown and described as transmitting data in the same direction. However, this is configured as an inverse loop as shown in FIG. Of course, it is also good.

FIG. 18 is a block diagram showing the embodiment of FIG. 15, that is, the concrete example of FIG. In the embodiment of FIG. 18, one identification data detection circuit 52 is provided in association with one data transmission line 28, and two identification data detection circuits 54 ₁ and 54 ₂ are provided in association with the other data transmission line 34.
Is provided. That is, the identification data detection circuit 52 includes four parallel data buffers B that form the data transmission line 28.
_The identification data is extracted from the input data to _{1 to} B ₄ . Identification data detecting circuit 54 ₁ and 54 _2, respectively, in parallel to configure the data transmission line 34 data buffers _{B 11} ~
Identification data is extracted from the input data to B ₁₄ and the input data to B _{21 to} B ₂₄ . Identification data detection circuit 5
The identification data detected by 2 is stored in two comparison circuits 56.
Given common in ₁ and 56 _2. The identification data detected by the identification data detection circuits 54 ₁ and 54 ₂ are individually applied to the corresponding comparison circuits 56 ₁ and 56 ₂ , respectively.

Two comparison circuits 56 ₁ and 56 ₂ are compared whether identification data both given match, the match signal is respectively supplied to the stop signal 80 '. Stop circuit 8
0'is for synchronizing the data packets to be paired when transmitted on the two data transmission lines 28 and 34, and is very similar to that shown in FIG. Then, a control signal is given from the stop circuit 80 'to the merging circuit 82, and the merging circuit 82 cooperates with the packet reassembling circuit 84 to send a new data packet onto the data transmission path 28.

The stop circuit 80 ′ includes a header signal from the header signal line HSL ₁ between the parallel data buffers B ₃ and B ₄ forming the first data transmission line 28, and a parallel data forming the second data transmission line 34. Buffers B ₂₃ and B ₂₄
The header signal from the header signal line HSL ₂ between the _two is given. Furthermore, the signals T from the C elements C ₃ and C ₂₃ corresponding to the parallel data buffers B ₃ and B ₂₃ , respectively.
RO ₁ and TRO ₂ are given.

From stop circuit 80 ', preceding C-element _{C 4} and _{C 24}
To stop signals STOP ₁ and STOP ₂ respectively
And a merging control signal is supplied to the merging circuit 82.

Stop circuit 80 ', as shown in FIG. 19, the OR gate 86' includes a coincidence signal 1 from the OR gate 86 comparison circuit 56 ₁ and 56 ₂ the two inputs of each '
And a match signal 2 are applied, and the output is applied to one input of the AND gate 88. The other input of the AND gate 88 is supplied with the header signal from the header signal line HSL ₁ . A match signal 1 is applied to the two inputs of the AND gate 90.
And a header signal from the header signal line HSL ₂ . The outputs of these AND gates 88 and 90 are provided as D inputs of D flip-flops 96 and 98 through OR gates 92 and 94, respectively. The clock input of this D flip-flop 96 is the signal TRO from the C element C ₃ associated with the first data transmission line 28.
₁ is similarly given, and similarly, the C element C of the second data transmission line 34 is supplied to the clock input of the D flip-flop 98.
The signal TRO ₂ from ₂₃ is provided. The output Q of each of the D flip-flops 96 and 98 is the OR gate 9
It is provided as its own D input through 2 and 94.

The output Q of the D flip-flop 96 is directly applied to one input of each of the AND gates 100 and 102, and also inverted by an inverter and applied to one input of the AND gate 104. The output Q of the D flip-flop 98 is directly applied to the other inputs of the AND gates 100 and 104, inverted by an inverter and applied to the other input of the AND gate 102. The output of the AND gate 102 is the stop signal ST
It is given to the C element C ₄ of the first data transmission line 28 as OP ₁ , and the output of the AND gate 104 is the stop signal STOP.
₂ is given to the C element C ₂₄ of the second data transmission line 34. Further, the output of the AND gate 100 is given to the merging circuit 82 as a merging control signal.

A stop release signal is applied to the reset inputs of the D flip-flops 96 and 98.

The merging circuit 82 and the data packet reassembling circuit 84 are the same as those shown in FIG.

When the header of the data packet is transferred to the parallel data buffer B ₃ of the first data transmission line 28, the header signal line H
SL ₁ becomes high level, a match signal from the comparison circuit 56 ₁ or 56 ₂ from the high level at this time in the data packet pair detection circuit 48 is obtained, stop circuit 80 '
The two inputs of the AND gate 88 become high level, and the D input of the D flip-flop 96 becomes high level. At this time, the signal TRO ₁ from the C element C ₃ becomes high level, the D flip-flop 96 is set, and its output Q becomes high level. Also, when the header is transferred to the parallel data buffer B ₂₃ included in the second data transmission line 34, the header signal line HSL ₂ becomes high level, a match signal from the comparison circuit 56 ₂ at this time is obtained, C The D flip-flop 98 is set in response to the signal TRO ₂ from the element C ₂₃ . That is, the D flip-flops 96 and 98 are connected to the first data transmission line 28.
Parallel data buffer B ₃ and second data transmission line 3
4 parallel data buffer B _23, the header of the data packets to be paired are set from either faster as it arrives. Then, the D flip-flop that has not been set is set whenever the header arrives. That is, the D flip-flops 96 and 98 have the comparison circuits 56 ₁ and 56 ₂ of the data packet pair detection circuit 48.
Will hold the match signal from.

If one D flip-flop 96 is set and the other D flip-flop 98 is not set yet, that is, the corresponding header has not arrived at the parallel data buffer B ₂₃ of the second data transmission line 34. ,
The two inputs of the AND gate 102 of the stop circuit 80 'are both at the high level, and therefore the terminal T of the C element C ₄ is connected.
The stop signal STOP ₁ to ₆ (FIG. 7) becomes high level. Then, the C element C ₂ is stopped.

Conversely, when the D flip-flop 98 is set and the D flip-flop 96 is not set, that is, when the corresponding header has not arrived at the first data transmission line 28, the stop signal STOP ₂ is output from the AND gate 104. Therefore, the data transmission on the second data transmission path 34 is stopped.

With the two D flip-flops 96 and 98 set together, ie parallel data buffers B ₃ and B
_{When the} corresponding header arrives at ₂₃ , one input of both AND gates 102 and 104 becomes low level, and both stop signals STOP ₁ and STOP ₂ become low level. According to AND gate 100
The two inputs of both become high level, and the merging circuit 82
A high-level merging control signal is output to. Therefore, the AND gate 114 included in the merging circuit 82.
(Fig. 14) Both inputs become high level,
Conversely, one input of the AND gate 116 becomes low level. Therefore, from the OR gate 118 (FIG. 14), the signal AK from the C element included in the first data transmission line 28, not from the C element of the second data transmission line 34.
O is output, and this signal is C of the second data transmission line 34.
Presented as signal AKI of element C ₂₄ . At the same time, one of the inputs of the AND gate 108 (FIG. 14) becomes low level, and the signal TRO from the C element C ₂₄ to the C element at the previous stage becomes low level. Further, since the merging control signal is at the high level, the merging circuit 82 (first
As an input of the OR gate 112, the output of the AND gate 110 is validated. Therefore, the C element C _{4 of} the first data transmission line 28 and the second data transmission line 3
4 C elements C ₂₄ both signals TRO ₁ and TRO ₂
Is high level, the high gate signal TRO is applied from the OR gate 112 to the C element further upstream of the first data transmission line 28. Therefore, after that, the data packet of the second data transmission line 34 is given to the packet combination changing circuit 84 provided in the first data transmission line 28, and disappears from the second data transmission line 34.

In the data packet repacking circuit 84, the packet repacking is performed and a new data packet is first
Of the stop circuit 8 after being brought on the data transmission line 28 of
A high level stop release signal is applied to 0 ', D flip-flops 96 and 98 are both reset, and therefore new data packet generation circuit 50 is disabled. In this way, a match of the data packets to be paired is detected and one new data packet is generated.

FIG. 20 is a modification of the embodiment shown in FIG. 18, and is an example in which the embodiment shown in FIG. 15, that is, FIG. 17 is also embodied.
In this embodiment, a plurality of basic modules M ₁ , M ₂ ,
M _3, constructed by cascading .... The basic module M is shown in FIG. Basic module M is 18th
Since the circuit is very similar to the circuit shown in the figure, detailed description thereof is omitted here, but the identification data is extracted from two different data packet pair detection sections of the second data transmission path 34 by the two identification data detection circuits. It is made possible.

Focusing on a certain basic module M ₂ , the comparison circuit 56 ₂ (FIG. 21) finds a match when two data packets to be paired together are transferred to the module M _2. . On the other hand, the comparison circuit 56 ₁ can determine that the data packet on the first data transmission path (upper data transmission path in the figure) of the two data packets to be paired is within the module M ₂ . However, the data packet on the second data transmission line (the lower data transmission line in the figure) is in the next module M ₁ (on the left side in the figure). That is, the data packets existing in the four parallel data buffers forming the upper data transmission line are transferred to the 8-stage parallel data buffer including the adjacent module of the data packet of the other party existing on the lower data transmission line. If so, the data packet of the other party is kept waiting until it arrives at the module M ₂ . On the contrary, the data packet existing on the lower data transmission path waits until the partner data packet arrives at the module M ₂ only when the partner data packet is transferred into the same module M ₂ . Will be done.

As described above, according to the embodiment shown in FIG. 20, only by connecting a plurality of basic modules in cascade, two data packet pair detection sections on the lower data transmission path and one on the upper data transmission path are detected.
By comparing two data packet pairs with the detection section, the "deadlock" due to the data misalignment can be completely eliminated as in FIG.

[Brief description of drawings]

FIG. 1 is a system conceptual diagram showing an example of a data processing device in which the present invention can be implemented. FIG. 2 is a schematic block diagram for explaining the principle of the present invention. FIG. 3 is a diagram showing an example of a data packet, and FIGS. 3 (A) and 3 (B) show different examples. FIG. 4 and FIG. 5 are conceptual diagrams for explaining generation of one new data packet from data packets to be paired, respectively. FIG. 6 is a block diagram showing an embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of the C element. FIG. 8 is a timing chart for explaining the circuit of FIG. FIG. 9 is a block diagram showing another embodiment of the present invention. FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to the embodiment shown in FIG. FIG. 11 is a block diagram showing another example of the identification data detection circuit applicable to the embodiment of FIG. FIG. 12 is a block diagram showing still another embodiment of the present invention. FIG. 13 is a circuit diagram showing an example of the stop circuit of the FIG. 12 embodiment. FIG. 14 is a circuit diagram showing an example of the merging circuit of the FIG. 12 embodiment. FIG. 15 is a block diagram showing another embodiment of the present invention. 16 and 17 are schematic diagrams showing the flow of data for explaining the concept of the embodiment shown in FIG. FIG. 18 is a block diagram showing an example in which the embodiment of FIG. 15, that is, FIG. 17 is embodied. FIG. 19 is a circuit diagram showing the stop circuit of FIG. FIG. 20 is a block diagram showing another embodiment of the embodiment shown in FIG. 15, that is, FIG. FIG. 21 is a block diagram showing one basic module shown in FIG. In the figure, 27 is a firing unit, 28 is a first data transmission line, 34 is a second data transmission line, 36 is a firing detection unit, 4
8 is a data packet pair detection circuit, 50 is a new data packet generation circuit, 52, 54, 52 _{1 to} 52n are identification data detection circuits, 56, 56 _{1 to} 56n are comparison circuits, and 80, 8
Reference numeral 0'denotes a stop circuit, 82 a merge circuit, and 84 a reassembling circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kozo Terada, 52-3 Yamada Nishi, Suita City, Osaka Prefecture B-803 Senri Ichijoike B-803 (72) Katsuhiko Asada 4--11, Higashi-Nambacho, Amagasaki City, Hyogo Prefecture (72) Inventor Hiroaki Nishikawa 1-1255-1002 Esaka-cho, Suita City, Osaka Prefecture (72) Inventor Soichi Miyata 17-88 folding screen, Miyake-cho, Isojo-gun, Nara (72) Inventor Toshi Matsumoto, Nara 3-30, Tenmadai Nishi, Harubara-cho, Uda-gun, Japan 5 (72) Inventor Hajime Asano 1-5 28, Shonai-nishicho, Toyonaka City, Osaka Prefecture (72) Inventor Masahisa Shimizu 271 Shimomabushi, Kadoma City, Osaka Prefecture (72) Invention Hiroki Miura 10-49 Asahioka-cho, Hirakata-shi, Osaka Sanyo Denki Co., Ltd. No. 2 Tamiya Dormitory (72) Inventor Kenji Shima 3-16-411 Koshien-cho, Nishinomiya-shi, Hyogo (72) Nobufumi Komori Hyogo Kuniyo, Itami City, Japan This 14-7

Claims (6)

[Claims] 1. A first data transmission path for transmitting a data packet including identification data including at least destination information, the first data transmission path including a shift register, and data including identification data including at least destination information. A second data transmission line for transmitting a packet and configured by using a shift register; the identification data included in a data packet transmitted to each of the first and second data transmission lines Identification data detecting means for detecting the data packet, and comparing the identification data detected by the identification data detecting means to determine the data packet which is transmitted on the first and second data transmission paths and is to be paired. Pair discriminating means, and the two data packets discriminated by the pair discriminating means to the first data transmission path A data processing device, comprising: new data packet generating means for taking out from the second data transmission path and generating one new data packet. 2. The method according to claim 1, wherein at least one of the first and second data transmission paths is formed in a loop shape, and the data packet is circulated around the loop transmission path. Data processing device. 3. The first and second responsive to the identification data detecting means detecting specific identification data of a data packet transmitted through one of the first and second data transmission paths. 3. The data processing device according to claim 1 or 2, further comprising means for waiting for a data packet to be paired to arrive on the other data transmission path of the above. 4. The waiting means includes stop means for stopping the shift of the one data transmission path.
The data processing device according to claim 3. 5. The data processing device according to claim 1, wherein the data packets are transmitted in opposite directions on the first and second data transmission paths. 6. A shift register constituting the first and second data transmission lines is configured as a self-propelled shift register, respectively.
The data processing device according to any one of paragraphs.