JPH06161949A - Information processor - Google Patents

Abstract

PURPOSE:To attain the simultaneous use of a 2nd processor bus for plural processors by dividing the processor by a buffer. CONSTITUTION:A 2nd processor bus 4 is used by plural processors 1 to give the accesses to plural peripheral devices 3 and is divided by a buffer 6. Then one of processors 1 outputs a 2nd processor bus using request signal to a bus arbiter 5 via a 2nd processor bus 2. The arbiter 5 compares the received bus using request signal with that received from another processor 1 and accepts the request of the highest priority to control the buffer 6. Then the arbiter 5 releases the part of the bus 4 that is requested by the processor 1 and outputs the 2nd processor bus using permission signal to the processor 1. Other parts of the bus 4 are kept idle and the arbiter 5 partly opens the bus 4 in response to the using request of the bus 4 given from the processors 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor type information processing apparatus for controlling a plurality of peripheral devices by a plurality of processors.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional multiprocessor type information processing apparatus. Reference numeral 1 is a plurality of processors, and 2 is a first processor bus for the plurality of processors 1 to access a plurality of peripheral devices 3. Reference numeral 4 is a second processor bus for the plurality of processors 1 to access the plurality of peripheral devices 3. Reference numeral 5 denotes a first processor bus 2 and a second processor bus 4 use request signal output from a plurality of processors, and outputs a first processor bus 2 and a second processor bus 4 use permission signal to a plurality of processors 1. It is a bus arbiter.

The conventional multiprocessor type information processing apparatus is configured as described above. For example, when the processor 1 uses the second processor bus 4 to access the peripheral device 3, the processor 1 gives the bus arbiter 5 a second access. The processor bus 4 use request signal 2 is output. The bus arbiter 5 compares the usage request of the second processor bus 4 from another processor 1 and outputs the usage permission signal of the second processor bus 4 to the processor 1 having the highest priority. When the processor 1 is not given the right to use the second processor bus 4, it waits until the right to use is obtained.
When the processor 1 receives the use permission signal, the second processor bus 4 is used to access the peripheral device 3.

[0004]

In the information processing apparatus as described above, the second processor bus 4 is used in a time division manner, so that only one processor 1 can be used at a certain time. While one processor 1 is using the second processor bus 4, even if a request for using the second processor bus 4 is issued from another processor 1, a waiting time occurs,
There has been a problem that the waiting time becomes longer as the number of processors 1 and peripheral devices 3 increases.

The present invention has been made to solve such a problem, and when one processor 1 is using the second processor bus 4, another processor 1 is second
It is intended that the processor bus 4 of can be used.

[0006]

In the information processing apparatus according to the present invention, the second processor bus is divided by a plurality of buffers, and the second processor bus which is requested to be used by the bus arbiter is partially released to allow a plurality of processors to operate. It gives the right to use the second processor bus.

A system bus divided by buffers is arranged in a ring shape.

The second processor bus is divided by a plurality of multiplexers so that the plurality of processors and the plurality of peripheral devices can be connected to each other in a one-to-one manner, and the bus arbiter controls the plurality of multiplexers in accordance with a request for use of the plurality of processors.

[0009]

When a plurality of processors of the information processing apparatus as described above use the second processor bus to access a plurality of peripheral devices, the portion requested to be used by the second processor bus is partially released by the bus arbiter. However, a plurality of processors can use the second processor bus at the same time by giving the right to use this portion to the processor and allocating the other portion of the second processor bus to the other processor.

[0010]

【Example】

Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 is a plurality of processors, and 2 is a first processor bus for the plurality of processors 1 to access a plurality of peripheral devices 3. A second processor bus 4 is used by the plurality of processors 1 to access the plurality of peripheral devices 3, and is divided by the buffer 6. 5 receives a first processor bus 2 and a second processor bus 4 use request signal from a plurality of processors 1 and outputs a first processor bus use permission signal to the processor 1; Is a bus arbiter for controlling the buffer 6 of the processor bus 4 and outputting a second processor bus partial use permission signal to the processor 1.

In the information processing apparatus configured as described above, for example, when the processor 1 attempts to access the peripheral device 3 using the second processor bus 4, the processor 1 uses the second processor bus 2. Then, the second processor bus use request signal is output to the bus arbiter 5. The bus arbiter 5 compares this request with a request from another processor 1, accepts the request with the highest priority, controls the buffer 6, and releases the portion requested by the processor 1 of the second processor bus. 1st to 2nd
The processor bus use permission signal of is output. The other part of the second processor bus is free and the processor 1
The bus arbiter partially releases the second processor bus in response to a second processor bus use request from the.

Example 2. In the first embodiment, the processor bus is divided as the second processor bus 4 by the buffer 6, and the processor 1 accesses the peripheral device 3 after partially opening the second processor bus 4 by the bus arbiter 5. In this embodiment, as shown in FIG. 2, the data bus is divided by the buffer 6 as the second processor bus 4, and the second processor bus 4 is partially opened by the bus arbiter 5 and then synchronized with the synchronization signal B from the bus arbiter 5. Data transfer is performed so that a large amount of data can be transferred at high speed.

Embodiment 3. In the first embodiment described above, the second processor bus 4 was linearly divided, but in the present embodiment, the second processor bus 4 is annularly arranged as shown in FIG. At this time, there are two kinds of second processor buses 4 between the processor 1 and the peripheral device 3 to be accessed, and the bus arbiter 5 controls which one is selected.

Example 4. In the first embodiment, the second processor bus is divided by the buffer 6, but in the present embodiment, the second processor bus 4 is divided by the multiplexer 7 as shown in FIG. By controlling 7, the processor 1 and the peripheral device 3 are connected in a one-to-one manner, and the waiting time of the second processor bus can be reduced.

[0015]

The present invention is configured as described above, and since the second processor bus is partitioned by the buffer, a plurality of processors can use the second processor bus at the same time.

A large amount of data can be transferred at a high speed by using the second processor bus as a data bus and transferring the data in synchronization with the synchronization signal from the bus arbiter by the processor and the peripheral device.

By arranging the second processor bus in a ring shape and partitioning it by a buffer, when the number of divisions from the processor to be accessed to the peripheral device to be accessed is more than half of the total number of divisions, the reverse is done. The area of the second processor bus to be used can be reduced by opening the surrounding second processor bus.

When there is a second processor bus in use between the second processor buses to be used, the waiting second time can be reduced by opening the second processor bus in the reverse direction.

By dividing the second processor bus by a multiplexer and controlling it by a multiplexer control signal from the bus arbiter, the processor to be accessed and the peripheral device are connected in a one-to-one manner, and the waiting time of the second processor bus is reduced. Can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional information processing apparatus.

[Explanation of symbols]

 1 Processor 2 1st Processor Bus 3 Peripheral Device 4 2nd Processor Bus 5 Bus Arbiter 6 Buffer 7 Multiplexer

Claims (4)

[Claims] 1. A plurality of processors, a plurality of peripheral devices accessed by the plurality of processors, a first processor bus used by the plurality of processors to access the plurality of peripheral devices, and a plurality of processors. A second processor bus used for accessing peripheral devices of the processor and separated by a buffer, and a first processor bus use request signal from a plurality of processors, and a first processor bus use enable signal is output to each processor. Receiving a second processor bus use request signal from a plurality of processors, outputting a buffer control signal of the second processor bus,
An information processing device, comprising: a bus arbiter that outputs a processor part use permission signal to each processor. 2. A data bus which is a second processor bus and a second processor bus use request signal from a plurality of processors, outputs a buffer control signal of the second processor bus, and outputs a second processor bus portion. The information processing apparatus according to claim 1, further comprising: a bus arbiter that outputs a use permission signal to each processor and outputs a synchronization signal that controls data transfer between the plurality of processors and the plurality of peripheral devices. 3. The information processing apparatus according to claim 1, wherein the second processor bus is annularly arranged. 4. A multiplexer that divides the second processor bus and connects the plurality of processors to the plurality of peripheral devices in a one-to-one relationship, and a second processor bus use request signal from the plurality of processors, 2. The information processing apparatus according to claim 1, further comprising: a bus arbiter that outputs a multiplexer control signal for connecting the processor buses and the processor bus use permission signal.