JPH06151775A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, wherein a field oxide film is restrained from decreasing in thickness, and a semiconductor substrate is protected against damage caused by etching so as to prevent the semiconductor device from deteriorating in characteristics. CONSTITUTION:A first process wherein field oxide films 3a to 3c are formed on a semiconductor substrate through an element isolation method, a second process wherein a sacrifice oxide film 2 is formed on an element region, a third process wherein only the sacrifice oxide film 2 on the first element region is removed, and the sacrifice oxide film 2 formed on a second element region or a following element region is left unremoved, a fourth process wherein a gate oxide film 4 is formed on a first element region, a fifth process wherein a gate electrode of first conductive material film is formed, and a sixth process wherein an interlayer insulating film is formed on the first conductive material film, and the residual sacrifice oxide film 2 is removed, and a seventh process wherein a gate oxide film and a gate electrode of second layer or following layers are formed are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate electrode made of a conductive material having two or more layers.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been manufactured by VLSI (Very Lar
ge Scale Integration), ULSI (Ultra Large Scal)
e Integration) and the degree of integration has increased remarkably.
There is a multilayer wiring technique as one of the techniques for increasing the degree of integration. In the multilayer wiring, the wiring pattern layers and the interlayer insulating film are alternately stacked on each other on the semiconductor substrate so that the upper and lower wiring pattern layers can be overlapped, so that the circuit can be formed in a smaller area and the integration degree can be improved. Can be increased.

As an example of using multilayer wiring, SRAM (St
atic Random Access Memory).

FIG. 3 is a circuit diagram of the SRAM. Shown in Figure 3
SRAM is a 6-transistor (N-channel cell)
Cross-inverted to store 1-bit information
Data pair (flip-flop) (T₁~ T_Four) Is used.
Access transistor pair (T _FiveAnd T₆) Is the word line
53 and bit lines 50 and 51 were activated at the same time
Sometimes data is moved in and out of cells.

The load on the flip-flop is the depletion mode transistors T ₁ and T ₂ , whose sources and gates are connected together. Data is held in the cell by the positive feedback of the flip-flop. For example T ₄
The gate of the s high potential and its drain is at a low potential, the potential applied to the gate of T _3, turning off the T _3. T
The drain of ₃ is connected to high potential by T ₁ which is always on in dip mode, so T ₄
The drain of is maintained at a low potential. The state of this cell defines a logical 1 or 0 and is held by T ₅ and T ₆ until new data comes in.

FIG. 4 is a layout of a circuit diagram of the SRAM shown in FIG. As shown in FIG. 4, bit lines 51, 52
And Vss52 is formed of aluminum (Al),
Vcc 54 is formed of an N ⁺ diffusion layer, and has a transistor T ₁ ,
T ₄ is the first polysilicon film and its channel region is N
It is formed of a diffusion layer, and the transistors T ₂ and T ₃ and the word line 53 are formed of a second polysilicon film. Since the word line 53 and the transistors T ₁ and T ₄ are formed of polysilicon films of different layers, even if the first polysilicon film and the second polysilicon film which overlap the wiring pattern, for example, Vss 52, overlap. Since it is good, the degree of integration can be increased.

Next, the first half step of manufacturing the above SRAM will be described. 5 and 6 show the manufacturing process of the SRAM and are sectional views taken along the line I-I 'shown in FIG.

First, an N-type impurity such as phosphorus is doped into the P-type silicon substrate 1 to form a channel region (N diffusion layer 100), a source, a drain region and a Vcc diffusion region of a depletion transistor. Next, as shown in FIG. 5A, the LOCOS method is used to form 9
Field oxide films 103a to 103 in water vapor at 50 ° C.
c is formed to a thickness of 500 nm. Next, the sacrificial oxide film 2 is formed to have a thickness of 40 nm in water vapor at 900 ° C.

Next, as shown in FIG. 5B, the entire surface is etched by RIE to remove the sacrificial oxide film 2. At this time,
The thickness of the field oxide films 103d to 103f is about 460
nm.

Next, as shown in FIG. 5C, a gate oxide film 104 is formed to a thickness of 20 nm in water vapor at 900 ° C. At this time, the field oxide films 103d to 103f are hardly oxidized (since the square of the film thickness is proportional to time), and the film thickness is almost unchanged.

Next, a first-layer polysilicon film having a thickness of 200 nm is formed on the entire surface by a CVD (Chemical Vapor Deposition) method, and then phosphorus is doped in a POCl ₃ atmosphere to make the polysilicon film conductive. To have. Next, as shown in FIG. 6A, the polysilicon film is patterned by photolithography and RIE to form a first polysilicon film 105.

Next, the first polysilicon film 105 of the first layer.
After forming SiO ₂ to a thickness of 200 nm by a CVD method as an interlayer insulating film between the second polysilicon film and the second polysilicon film, patterning is performed by photolithography and RIE, and as shown in FIG. The interlayer insulating film 106 is formed. At this time, field oxide films 103g and 10
Part of the exposed surface of 3h is etched back and the film thickness is 440
nm.

Next, as shown in FIG. 6C, a gate oxide film 107 is formed on the silicon substrate 1 in water vapor at 900 ° C. Next, in the same manner as shown in FIGS. 6A and 6B, a second polysilicon film (hereinafter not shown) and an interlayer insulating film are formed on the gate oxide film 107,
After that, the bit lines 51 and 52 and Vss5 shown in FIG.
2 is opened, aluminum is sputtered and patterned to form the bit lines 50, 51 and Vss 52 shown in FIG. 4, and the SRAM is manufactured.

[0014]

In the above-described SRAM manufacturing process, the process shown in FIG.
Since the sacrificial oxide film 2 between the field oxide films 103b and 103c shown in (a) is removed, the field oxide films 103e and 103f are partially etched.
In the step shown in FIG. 6B, the interlayer insulating film 10
When patterning 6 the field oxide film 10
Since 3g and 103h are partially etched, the film thickness of the field oxide films 103g and 103h is reduced, and the insulation resistance is deteriorated. However, the field oxide film 103
Since g and 103h form a parasitic transistor between adjacent element regions, if the insulation resistance deteriorates, the parasitic transistor becomes conductive, and malfunction of the SRAM easily occurs, which is a problem.

Further, in the step shown in FIG.
Since the thin gate oxide film 104 is removed by IE, P
The surface of the type silicon substrate 1 is over-etched,
A crystal defect occurs, a leak current is likely to occur, and the characteristics and reliability of the transistor deteriorate, which is a problem.

Therefore, the present invention has an object to provide a method for manufacturing a semiconductor device, which suppresses the deterioration of the film thickness of the field oxide film, the damage to the semiconductor substrate due to etching, and the deterioration of the characteristics of the semiconductor device. And

[0017]

According to the present invention, the above object is to provide a field oxide film on a semiconductor substrate by an element isolation method in a method of manufacturing a semiconductor device having a gate electrode composed of two or more conductive material films. Forming step, forming a sacrificial oxide film on the element region, and removing only the sacrificial oxide film on the element region of the gate electrode formed on the first layer to form the second and subsequent layers. A step of leaving the sacrificial oxide film on the element region, a step of forming a gate oxide film on the element isolation region formed in the first layer, and the gate electrode made of the conductive material film of the first layer. A step of forming an interlayer insulating film on the first conductive material film and removing the remaining sacrificial oxide film, and forming a gate oxide film and a gate electrode of the second and subsequent layers. The process and It is solved by the method for manufacturing a semiconductor device according to claim.

[0018]

According to the present invention, as shown in FIG. 1B, only the sacrificial oxide film 2 on the element region formed on the first layer is removed to remove the sacrifice on the element regions formed on the second and subsequent layers. Since the oxide film 2 remains, one side of the field oxide film 3e is not removed by etching. Therefore, in patterning the interlayer insulating film 6 shown in FIG. 2B, the sacrificial oxide film 2 formed after the second layer is removed. In doing so, it is possible to suppress the decrease in the thickness of the field oxide film 3f.

The semiconductor substrate is formed by etching the sacrificial oxide film 2 shown in FIG. 2B by increasing the thickness of the sacrificial oxide film 2 shown in FIG. 1A to the thickness of the gate oxide films 4 and 7. The damage to 1 can be suppressed.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 show an embodiment in the first half step of manufacturing the SRAM according to the present invention, and are shown in a sectional view taken along the line I--I 'of the layout shown in FIG.

In this embodiment, first, an N-type impurity such as phosphorus is doped, and then the channel region (N diffusion layer 100) of the depletion transistor, the source and drain regions and Vc.
A c diffusion region is formed.

Next, as shown in FIG. 1 (a), field oxide films 3a to 3c are formed to a thickness of 500 nm on the P-type silicon substrate 1 by using the LOCOS method in water vapor at 950.degree. Then, the "white ribbon" defect due to LOCOS is removed by etching, and a sacrificial oxide film 2 having a thickness of 40 nm is formed in water vapor at 900 ° C. in order to form a uniform oxide film in the element region.

Next, photolithography and RIE
Then, only the sacrificial oxide film 2 in the region surrounded by the field oxide films 3a and 3b is removed as shown in FIG. 1B, and the sacrificial oxide film 2 in the region surrounded by the field oxide films 3b and 3c is removed. Let it remain. At this time, the film thickness of the field oxide film 3d is 460 nm, the film thickness on one side of the field oxide film 3e is 460 nm, the film thickness on the other side is 500 nm, and the film thickness of the field oxide film 3c is 500 nm.

Next, as shown in FIG. 1C, a gate oxide film 4 is formed with water vapor at 900 ° C. to a thickness of 20 nm.
At this time, the square of the oxide film thickness is proportional to time, and since the oxide film of the gate oxide film 4 is thin, the field oxide films 3d, 3e, 3
c and the sacrificial oxide film 2 are hardly oxidized.

Next, a buried contact hole is opened, then a first-layer polysilicon film is formed to a thickness of 200 nm on the entire surface by the CVD method, and heat treatment is performed in a POCl ₃ atmosphere to dope phosphorus, Make the silicon film conductive. Next, as shown in FIG. 2A, the polysilicon film is patterned by photolithography and RIE to form a first polysilicon film 5.

Next, as shown in FIG. 2B, this SiO ₂ film is formed to a thickness of 200 nm by the CVD method, and the SiO ₂ film is patterned by photolithography and RIE to form the first layer of the first layer. An interlayer insulating film 6 is formed between the polysilicon film 5 and the second polysilicon film. At this time, part of the field oxide films 3f and 3g is etched to a film thickness of 460 nm. On the other hand, FIG.
Since the film thickness of the conventional field oxide films 103g and 103h shown in (b) is 440 nm, the film thickness of the field oxide films 3f and 3g of this embodiment is 20 nm.
Since the thickness can be made thicker than before, the withstand voltage characteristic can be improved. In addition, the thickness of the sacrificial oxide film 2 (40n
Since m) is thicker than the gate oxide film (20 nm) shown in FIG. 7B, it is possible to suppress damage to the P-type silicon substrate 1 in etching by RIE more than before.

Next, as shown in FIG. 2C, a gate oxide film 7 is formed on the P-type silicon substrate 1 in water vapor at 900 ° C.
It is formed to a thickness of 0 nm. Next, FIG. 2A and FIG.
In the same manner as shown in (b), a second polysilicon film (not shown below) and an interlayer insulating film are formed on the gate oxide film 7, and then the bit lines 50 and 51 shown in FIG. A contact hole for Vss52 is opened, and aluminum is sputtered and patterned.
The bit lines 50, 51 and Vss52 shown in FIG.
Manufacture AM.

[0029]

As described above, according to the present invention, only the sacrificial oxide film in the element formation region of the first layer is removed and the element formation of the second and subsequent layers is performed in the semiconductor device including the multilayer gate wiring. By leaving the sacrificial oxide film in the region, it is possible to suppress the loss of the field oxide film adjacent to the element formation region of the second and subsequent layers and reduce the damage to the silicon substrate. The transistor characteristics and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view (I) of a first half step of manufacturing an SRAM showing an embodiment.

FIG. 2 is a sectional view of the first half step of manufacturing an SRAM showing an embodiment (I
I).

FIG. 3 is a circuit diagram of an SRAM.

FIG. 4 is a layout of SRAM.

FIG. 5 is a sectional view (I) of the first half step of manufacturing an SRAM showing a conventional example.

FIG. 6 is a sectional view of the first half step of manufacturing an SRAM showing a conventional example (I
I).

[Explanation of symbols]

 1 P-type silicon substrate 2 Sacrificial oxide film 3a to 3g Field oxide film 4 Gate oxide film 5 First polysilicon film 6 Interlayer insulating film 7 Gate oxide film 50, 51 Bit line 52 Vss 53 Word line 54 Vcc 100 N diffusion layer 103a -10 3 h Field oxide film 104 Gate oxide film 105 First polysilicon film 106 Inter-layer insulating film 107 Gate oxide film

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a gate electrode made of a conductive material film having two or more layers, the method comprising: forming a field oxide film on a semiconductor substrate by an element isolation method; and forming a sacrificial oxide film on an element region. A step of forming and a step of removing only the sacrificial oxide film on the element region formed in the first layer of the gate electrode and leaving the sacrificial oxide film on the element regions formed in the second and subsequent layers A step of forming a gate oxide film on the element region formed in the first layer, a step of forming the gate electrode made of the conductive material film in the first layer, and a conductive material film in the first layer A method of manufacturing a semiconductor device, comprising: a step of forming an interlayer insulating film thereon; removing the remaining sacrificial oxide film; and a step of forming the second and subsequent layers of gate oxide film and gate electrode. Method.