JPH0613488A - Circuit and its manufacture board - Google Patents

Circuit and its manufacture board

Info

Publication number
JPH0613488A
JPH0613488A JP4166360A JP16636092A JPH0613488A JP H0613488 A JPH0613488 A JP H0613488A JP 4166360 A JP4166360 A JP 4166360A JP 16636092 A JP16636092 A JP 16636092A JP H0613488 A JPH0613488 A JP H0613488A
Authority
JP
Japan
Prior art keywords
circuit
metal foil
circuit board
hole
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4166360A
Other languages
Japanese (ja)
Inventor
Masayuki Oi
政幸 大井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Fujifilm Microdevices Co Ltd
Original Assignee
Fujifilm Microdevices Co Ltd
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujifilm Microdevices Co Ltd, Fuji Photo Film Co Ltd filed Critical Fujifilm Microdevices Co Ltd
Priority to JP4166360A priority Critical patent/JPH0613488A/en
Publication of JPH0613488A publication Critical patent/JPH0613488A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To provide a thin type circuit board having good heat radiation characteristics and its manufacture at a low cost with respect to a circuit board and its manufacture for mounting a circuit elements containing semiconductor elements such as IC's. CONSTITUTION:A circuit board is produced by a process for forming a metal foil on the surface of a resin board 1; a process for forming a pattern of the heat radiating region of a circuit element 2 and a circuit pattern 4 by a metal foil on the metal foil; a process of irradiating laser light to the surface at the opposite side of the pattern in the radiating region of the resin board 1, of removing part of the resin board 1 of the heat radiating region, of forming a hole for housing the circuit element 2 and of exposing the metal foil in the heat radiating region; and a process for inserting the circuit element into the hole and for adhering the circuit element 2 to the exposed metal foil in the heat radiating region.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ICのような半導体素
子を含む回路素子を実装するための回路基板とその製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for mounting a circuit element including a semiconductor element such as an IC and a manufacturing method thereof.

【0002】[0002]

【従来の技術】回路基板は一般に樹脂製基板上に銅箔等
による回路パターンを形成し、ICチップや抵抗素子あ
るいはコンデンサ素子のような電気回路素子を回路パタ
ーンの上にハンダ等により接着して形成される。
2. Description of the Related Art In general, a circuit board is formed by forming a circuit pattern made of copper foil or the like on a resin board and bonding an electric circuit element such as an IC chip, a resistance element or a capacitor element on the circuit pattern by soldering or the like. It is formed.

【0003】近年、小型の電気製品や電卓あるいはIC
カード等に代表されるように回路基板の小型化、特に薄
形化の要求が強くなっている。回路基板を薄くするため
には樹脂製基板を薄くしたり、回路部品自体を小型にす
る方法が行われる一方、回路基板への回路部品の実装方
法も改良されねばならない。
In recent years, small electric appliances, calculators or ICs
There is an increasing demand for miniaturization of circuit boards, particularly thin ones, as represented by cards and the like. In order to reduce the thickness of the circuit board, a method of reducing the thickness of the resin board or reducing the size of the circuit component itself is performed, but the method of mounting the circuit component on the circuit board must be improved.

【0004】同時に、回路基板が小型化すると回路素子
とくに半導体素子のような発熱の大きな素子からの熱の
放出の問題も重要となるので、熱放散性の高い基板構造
が考えられねばならない。
At the same time, when the circuit board is downsized, the problem of heat dissipation from circuit elements, especially semiconductor elements, which generate a large amount of heat, becomes important. Therefore, a board structure having a high heat dissipation property must be considered.

【0005】図4に示すものは、従来の技術による回路
基板の断面図である。樹脂基板41の一方の面に半導体
素子42が入るような穴43を基板41の途中まで機械
加工によりあけて、その中に半導体素子42を配置して
熱伝導のよい接着材44で基板41と接着させる。そし
て半導体素子42の端子(ボンディングパッド)と回路
パターン45とをワイヤーボンディングする。穴43に
半導体素子42が入るので回路基板全体の高さが低くな
る。
FIG. 4 is a cross-sectional view of a conventional circuit board. A hole 43 is formed on one surface of the resin substrate 41 so that the semiconductor element 42 can be inserted into the middle of the substrate 41 by machining, and the semiconductor element 42 is arranged in the hole 43. Let it adhere. Then, the terminals (bonding pads) of the semiconductor element 42 and the circuit pattern 45 are wire-bonded. Since the semiconductor element 42 is inserted in the hole 43, the height of the entire circuit board becomes low.

【0006】図5の回路基板は従来の技術によるプラス
チック・ピン・グリッドアレイの断面図である。PCB
樹脂基板51に半導体素子52が配置される貫通孔53
が機械加工により形成される。
The circuit board of FIG. 5 is a cross-sectional view of a prior art plastic pin grid array. PCB
Through hole 53 in which semiconductor element 52 is arranged on resin substrate 51
Are formed by machining.

【0007】さらに貫通孔53の周囲に貫通孔53より
少し広い凹み部54を機械加工により形成し、そこに熱
伝導率の良い材料でできたヒートシンク55が接着さ
れ、ヒートシンク55に半導体素子52が熱伝導のよい
接着材56で接着される。
Further, a recess 54 which is slightly wider than the through hole 53 is formed around the through hole 53 by machining, and a heat sink 55 made of a material having a high thermal conductivity is adhered to the recess 54, so that the semiconductor element 52 is attached to the heat sink 55. It is adhered with an adhesive material 56 having good thermal conductivity.

【0008】その後、半導体素子52の端子と回路パタ
ーン57とをワイヤーボンディングし、半導体素子52
を覆うように樹脂モールド58を施す。59は回路パタ
ーン57と外部回路(図示せず)とを接続するためのリ
ードピンである。
Thereafter, the terminals of the semiconductor element 52 and the circuit pattern 57 are wire-bonded to each other to form the semiconductor element 52.
A resin mold 58 is applied to cover the. Reference numeral 59 is a lead pin for connecting the circuit pattern 57 and an external circuit (not shown).

【0009】図5の構造では機械加工による貫通孔53
によって回路基板の高さが押さえられ、かつヒートシン
ク55により半導体素子52からの熱放散が促進され
る。
In the structure of FIG. 5, a through hole 53 is formed by machining.
This suppresses the height of the circuit board, and the heat sink 55 promotes heat dissipation from the semiconductor element 52.

【0010】[0010]

【発明が解決する課題】図4の従来の技術における回路
基板構造では穴43を穿った分だけ半導体素子42によ
る高さが低くできるので薄形化には寄与するものの、機
械加工により穴43をあけるために穴の深さすなわち基
板の薄い部分の厚みのばらつきが大きくなる。
In the conventional circuit board structure shown in FIG. 4, although the height of the semiconductor element 42 can be lowered by the amount of the holes 43, the holes 43 can be machined to reduce the height. Since the holes are formed, the variation in the depth of the holes, that is, the thickness of the thin portion of the substrate increases.

【0011】しかも樹脂基板を介して放熱するために熱
放散性がそれほど良くならなかった。また、基板41の
機械的強度を保つためにある程度の基板の厚みを残して
穴を加工するために、その分、回路基板の薄形化には限
界があった。
Moreover, since the heat is dissipated through the resin substrate, the heat dissipation is not so good. Further, in order to maintain the mechanical strength of the board 41, the holes are machined while leaving a certain thickness of the board, and accordingly, there is a limit in thinning the circuit board.

【0012】また、図5の従来の技術における回路基板
構造では穴を穿った分だけ半導体素子52による高さが
低くできるのは図4の基板構造と同様であるが、別体の
ヒートシンク55を取り付けるためにヒートシンク55
の厚み分だけ回路基板の高さを低くできない。
Further, in the conventional circuit board structure of FIG. 5, the height of the semiconductor element 52 can be lowered by the amount of the holes, which is similar to the board structure of FIG. 4, but a separate heat sink 55 is used. Heat sink 55 for mounting
The height of the circuit board cannot be reduced by the thickness of the.

【0013】さらにヒートシンク55により熱放散性は
向上するものの、機械加工の工程が増加し、しかもヒー
トシンク部品を別に製造して基板51に接着しなければ
ならないために製造工程が複雑になりコスト増大とな
る。また、接着部分が多くなるので、その部分の信頼性
の確保がむずかしくなるといった問題が発生する。
Further, although the heat dissipation property is improved by the heat sink 55, the number of machining processes is increased, and since the heat sink component has to be separately manufactured and adhered to the substrate 51, the manufacturing process is complicated and the cost is increased. Become. Further, since the number of bonded portions increases, it becomes difficult to secure the reliability of the bonded portion.

【0014】本発明の目的は、低コストで薄形の熱放散
性の良い回路基板とその製造方法を提供することにあ
る。
An object of the present invention is to provide a low-cost, thin circuit board having good heat dissipation and a method for manufacturing the same.

【0015】[0015]

【課題を解決するための手段】本発明による回路基板の
製造方法は、樹脂基板の面の上に金属箔を形成する工程
と、前記金属箔に該金属箔による回路パターンと回路素
子の放熱領域のパターンとを形成する工程と、前記樹脂
基板の前記放熱領域のパターンの反対側の面にレーザ光
を照射して照射領域の前記樹脂基板部分を除去し、前記
回路素子が内包できるような穴を形成して前記放熱領域
の金属箔を露出させる工程と、前記穴に前記回路素子を
挿入して前記回路素子と前記放熱領域の露出した金属箔
とを接着する工程とを有する。
A method of manufacturing a circuit board according to the present invention comprises a step of forming a metal foil on a surface of a resin substrate, a circuit pattern formed by the metal foil on the metal foil, and a heat dissipation area of a circuit element. And the step of forming a pattern, and irradiating the surface of the resin substrate on the side opposite to the pattern of the heat dissipation region with laser light to remove the resin substrate portion in the irradiation region, and a hole that can be included in the circuit element. And exposing the metal foil in the heat dissipation area, and inserting the circuit element into the hole to bond the circuit element and the exposed metal foil in the heat dissipation area.

【0016】本発明による回路基板は、樹脂基板と、前
記樹脂基板の面に金属箔により形成された回路パターン
と回路素子の放熱領域と、前記樹脂基板の前記放熱領域
が形成された面と反対側の面に前記放熱領域の金属箔が
露出するように形成された前記回路素子を内包可能な穴
と、前記穴の底に露出した前記金属箔の面に接着された
前記回路素子とを有する。
The circuit board according to the present invention is opposite to the resin board, the circuit pattern formed by the metal foil on the surface of the resin board, the heat radiation area of the circuit element, and the surface of the resin board on which the heat radiation area is formed. A hole capable of containing the circuit element formed so that the metal foil in the heat dissipation area is exposed on the side surface, and the circuit element bonded to the surface of the metal foil exposed at the bottom of the hole. .

【0017】[0017]

【作用】金属箔の放熱領域を回路パターンと同時に形成
し、樹脂基板に設けた穴の中に回路素子を埋設して穴の
底の露出した金属箔と回路素子とを接着することによっ
て回路基板が薄くなり、しかもより直接的に金属箔を介
して回路素子からの熱の放散が行われる。
The circuit board is formed by forming the heat dissipation area of the metal foil at the same time as the circuit pattern, embedding the circuit element in the hole provided in the resin substrate, and adhering the exposed metal foil at the bottom of the hole to the circuit element. In addition, heat is dissipated from the circuit element more directly through the metal foil.

【0018】[0018]

【実施例】図1は本発明の実施例による回路基板の断面
図である。エポキシやポリイミド等の樹脂成分のみで形
成された樹脂基板1に半導体素子(IC)2が配置され
る穴すなわちデバイスホール3が形成されている。デバ
イスホール3はレーザにより樹脂基板1の樹脂を除去し
銅箔5の部分が露出するまで穴をあけて形成する。
1 is a sectional view of a circuit board according to an embodiment of the present invention. A hole for arranging a semiconductor element (IC) 2, that is, a device hole 3 is formed in a resin substrate 1 formed only of a resin component such as epoxy or polyimide. The device hole 3 is formed by removing the resin of the resin substrate 1 with a laser and making a hole until the portion of the copper foil 5 is exposed.

【0019】樹脂基板は一般的には熱膨張係数をSiに
近付ける目的でガラス布が含まれているが、本実施例で
は後で説明するレーザ加工を容易に施すためにガラス布
の含まれない樹脂成分のみの基板材料を用いる。
The resin substrate generally contains a glass cloth for the purpose of making the coefficient of thermal expansion close to that of Si. However, in this embodiment, the glass cloth is not included in order to easily perform the laser processing described later. A substrate material containing only resin components is used.

【0020】樹脂基板1の両面には回路パターン4が銅
箔により形成されており、同時に回路パターン4と同じ
銅箔により放熱板5も形成されている。さらに穴3内に
は半導体素子2が収納され熱伝導のよい接着材あるいは
ハンダ6により放熱板5と接着される。
A circuit pattern 4 is formed of copper foil on both sides of the resin substrate 1, and at the same time, a heat dissipation plate 5 is also formed of the same copper foil as the circuit pattern 4. Further, the semiconductor element 2 is housed in the hole 3 and is bonded to the heat dissipation plate 5 with an adhesive material or solder 6 having good thermal conductivity.

【0021】半導体素子2の端子(ボンディングパッ
ド)と回路パターン4とはワイヤーボンディングで接続
され、半導体素子2を覆うように樹脂モールド7が施さ
れている。図1の回路基板は図5の回路基板のようなリ
ードピンが不要なプラスチックリードレスチップキャリ
ア(PLCC)と呼ばれるものである。もちろん、本発
明は図5のようなプラスチック・ピン・グリッドアレイ
にも適用できることは言うまでもない。
The terminals (bonding pads) of the semiconductor element 2 and the circuit pattern 4 are connected by wire bonding, and a resin mold 7 is applied so as to cover the semiconductor element 2. The circuit board of FIG. 1 is called a plastic leadless chip carrier (PLCC) which does not require lead pins like the circuit board of FIG. Of course, the present invention can be applied to a plastic pin grid array as shown in FIG.

【0022】図1の回路基板においては、回路パターン
4と同じ工程で同じ銅箔材料により放熱板5が形成され
るので、図5の従来技術のようにわざわざヒートシンク
を別に用意して接着する必要がなく、ヒートシンクや樹
脂基板の厚みによって回路基板の高さが制限されない。
In the circuit board of FIG. 1, since the heat sink 5 is formed of the same copper foil material in the same process as the circuit pattern 4, it is necessary to separately prepare and bond the heat sink as in the prior art of FIG. The height of the circuit board is not limited by the thickness of the heat sink and the resin board.

【0023】したがって、回路基板の薄形化が効果的に
でき、しかも銅箔により半導体素子2の熱放散性が高め
られる。もちろん、熱放散が必要なのは半導体素子にか
ぎらないので、電流が流れることにより熱が発生する抵
抗素子や他の熱を多く発生して放熱が必要な回路素子を
図1の半導体素子2に置き換えても同様な効果が得られ
るであろう。
Therefore, the circuit board can be effectively thinned, and the heat dissipation of the semiconductor element 2 can be enhanced by the copper foil. Of course, it is not limited to the semiconductor element that needs to dissipate heat. Therefore, the resistance element that generates heat due to the flow of current and other circuit elements that generate a lot of heat and need to dissipate heat should be replaced with the semiconductor element 2 of FIG. Will have the same effect.

【0024】次に、図2を参照して図1の回路基板の製
造方法の実施例について工程順に説明する。図2(A)
で、樹脂基板1の全面に銅箔14を張り付ける。銅箔の
厚みは通常の回路基板では18μm程度であるが、本実
施例では放熱板としての機械強度を保つためにそれより
も厚く約35μm程度あるいはそれ以上とする。
Next, an embodiment of a method for manufacturing the circuit board of FIG. 1 will be described in order of steps with reference to FIG. Figure 2 (A)
Then, the copper foil 14 is attached to the entire surface of the resin substrate 1. The thickness of the copper foil is about 18 μm in a normal circuit board, but in this embodiment, it is about 35 μm or more, which is thicker than that in order to maintain the mechanical strength of the heat dissipation plate.

【0025】次に図2(B)に示すように、必要なエッ
チングやスルーホール(図示せず)の孔開けを行ない、
パネルメッキ法で回路パターン4を形成する。その際に
回路パターン4と同時に放熱板5も形成する。さらに回
路パターン4にチップ部品接着とリード線接着のための
ソルダーレジスト印刷とNi,Auメッキをそれぞれ施
す。デバイスホール3の部分は樹脂基板1の表面を露出
させる。
Next, as shown in FIG. 2B, necessary etching and through hole (not shown) are performed,
The circuit pattern 4 is formed by the panel plating method. At that time, the heat dissipation plate 5 is formed simultaneously with the circuit pattern 4. Further, the circuit pattern 4 is subjected to solder resist printing and Ni and Au plating for chip component bonding and lead wire bonding, respectively. The part of the device hole 3 exposes the surface of the resin substrate 1.

【0026】さらに、図2(C)で示すように、エキシ
マレーザ光を放熱板5と反対側の基板部に照射し、エキ
シマレーザ光10が照射された基板樹脂材に光化学反応
によって結合開裂(分解)を生じせしめる。
Further, as shown in FIG. 2 (C), the excimer laser light is applied to the substrate portion on the opposite side of the heat dissipation plate 5, and the substrate resin material irradiated with the excimer laser light 10 is subjected to photochemical reaction for bond cleavage ( Decomposition).

【0027】そして図2(D)で示すように、レーザ照
射領域に放熱板5が露出するまで基板樹脂を除去し、デ
バイスホール3を形成する。エキシマレーザによるデバ
イスホール3の形成は後でさらに説明する。
Then, as shown in FIG. 2D, the substrate resin is removed until the heat dissipation plate 5 is exposed in the laser irradiation region, and the device hole 3 is formed. The formation of the device hole 3 by the excimer laser will be further described later.

【0028】その後、図1に示すように、半導体素子2
を熱伝導の良い接着材6で放熱板5にダイボンディング
し、半導体素子2のアルミパッド8と基板の回路パター
ン4とをAuワイヤー9で結線し、半導体素子2及び結
線部分をトランスファー成形あるいは液状樹脂にて封止
する。また図示はしないが、半導体素子1以外の抵抗や
コンデンサといったチップ部品も回路パターン4に接着
される。
Then, as shown in FIG.
Is die-bonded to the heat sink 5 with an adhesive 6 having good thermal conductivity, the aluminum pad 8 of the semiconductor element 2 and the circuit pattern 4 of the substrate are connected by an Au wire 9, and the semiconductor element 2 and the connected portion are transferred or liquid-molded. Seal with resin. Although not shown, chip components such as resistors and capacitors other than the semiconductor element 1 are also bonded to the circuit pattern 4.

【0029】上記実施例においてデバイスホール3を形
成するのにはエキシマレーザを使用することが推奨され
る。エキシマレーザのような高強度の紫外線レーザを樹
脂のような有機高分子材料(ポリマ)表面に照射する
と、照射された部分が瞬間的に分解・飛散するアブレー
ションと呼ばれる現象が起こる。
It is recommended to use an excimer laser to form the device hole 3 in the above embodiment. When a high-intensity ultraviolet laser such as an excimer laser is irradiated on the surface of an organic polymer material (polymer) such as resin, a phenomenon called ablation occurs in which the irradiated portion is instantaneously decomposed and scattered.

【0030】エキシマレーザの波長と強度を基板材料の
種類に応じて適切に選択すれば、このアブレーションに
よって、樹脂基板にデバイスホール3を精度よくシャー
プにあけ、かつ銅箔の放熱板5にはダメージを与えるこ
とがないようにできる。
By appropriately selecting the wavelength and intensity of the excimer laser according to the type of the substrate material, this ablation allows the device hole 3 to be accurately and sharply formed in the resin substrate, and the heat sink 5 of the copper foil to be damaged. Can be given.

【0031】次に、図3(A),(B)を参照してエキ
シマレーザによるデバイスホール3の形成方法の実施例
について以下説明する。図3(A)において、エキシマ
レーザヘッド21は、たとえば、KrFレーザチューブ
を含み、レーザ駆動部22によって駆動される。エキシ
マレーザヘッド21から放射されるエキシマレーザビー
ムはミラー23,24によって光路(矢印)が調整され
マクス25に入射する。
Next, with reference to FIGS. 3A and 3B, an embodiment of a method of forming the device hole 3 by an excimer laser will be described below. In FIG. 3A, the excimer laser head 21 includes, for example, a KrF laser tube, and is driven by the laser driving unit 22. The excimer laser beam emitted from the excimer laser head 21 has its optical path (arrow) adjusted by the mirrors 23 and 24, and enters the max 25.

【0032】放熱板5の形状に対応する開口部38(図
3(B))を有するマスク25によって整形されたエキ
シマレーザビームは、ミラー26によって下方に曲げら
れ、イメージングレンズ27を通って図2(B)で示す
基板1のデバイスホール形成領域に結像する。
The excimer laser beam shaped by the mask 25 having the opening 38 (FIG. 3B) corresponding to the shape of the heat dissipation plate 5 is bent downward by the mirror 26, passes through the imaging lens 27, and passes through the imaging lens 27. An image is formed on the device hole formation region of the substrate 1 shown in FIG.

【0033】所望の倍率で基板上に結像するよう、マス
ク25、イメージングレンズ27の位置は、コントロー
ラ31からの制御信号により調整される。上方から撮像
モニタ29により基板1が観測され基板表面のパターン
情報が信号化されてコントローラ31に供給される。ま
た、高さモニタ32は、基板1の高さをモニタし、測定
結果を高さ信号としてコントローラ31に供給する。
The positions of the mask 25 and the imaging lens 27 are adjusted by a control signal from the controller 31 so that an image is formed on the substrate at a desired magnification. The board 1 is observed from above by the imaging monitor 29, and pattern information on the board surface is converted into a signal and supplied to the controller 31. Further, the height monitor 32 monitors the height of the substrate 1 and supplies the measurement result to the controller 31 as a height signal.

【0034】コントローラ31は、撮像モニタ29、高
さモニタ32から供給されたモニタ信号に基づき、各制
御部分を制御するための信号を発生する。コントローラ
31は、位置合わせ信号をXステージ33、Yステージ
34を含む加工ステージ35に送り、マスク25で整形
されたエキシマレーザ光が正確にデバイスホール領域に
照射されるように基板1の位置決めを行う。なお、加工
ステージ35はX,Y調整の他、Z調整やθ調整を行う
こともできる。
The controller 31 generates a signal for controlling each control portion based on the monitor signals supplied from the image pickup monitor 29 and the height monitor 32. The controller 31 sends an alignment signal to the processing stage 35 including the X stage 33 and the Y stage 34, and positions the substrate 1 so that the excimer laser light shaped by the mask 25 is accurately applied to the device hole region. . The processing stage 35 can perform Z adjustment and θ adjustment as well as X and Y adjustment.

【0035】エキシマレーザヘッド21は、KrFの場
合、たとえば8mm×25mmのレーザビームをパルス
繰り返し数200pps、出力エネルギ250mJ、平
均出力50W、パルス幅16nsで発生する。
In the case of KrF, the excimer laser head 21 generates a laser beam of, for example, 8 mm × 25 mm with a pulse repetition rate of 200 pps, an output energy of 250 mJ, an average output of 50 W, and a pulse width of 16 ns.

【0036】なお、KrFレーザの波長は約248nm
である。なお、エキシマレーザがArFの場合は、発振
波長は約193nmであり、XeClレーザの場合は、
発振波長は約308nmである。
The wavelength of the KrF laser is about 248 nm.
Is. When the excimer laser is ArF, the oscillation wavelength is about 193 nm, and when the excimer laser is XeCl laser,
The oscillation wavelength is about 308 nm.

【0037】次に、図3(B)にエキシマレーザビーム
の整形方法を概略的に示す。マスク25は、銅合金やモ
リブデン等の金属で形成され、所望パターンの開口38
を有する。マスク25に入射したエキシマレーザビーム
は、マスク25を新たな光源として、イメージングレン
ズ27によって基板1上に結像される。
Next, FIG. 3B schematically shows a method of shaping the excimer laser beam. The mask 25 is formed of a metal such as copper alloy or molybdenum, and has an opening 38 having a desired pattern.
Have. The excimer laser beam incident on the mask 25 is imaged on the substrate 1 by the imaging lens 27 using the mask 25 as a new light source.

【0038】マスク25とイメージングレンズ27の間
の距離をaとし、イメージングレンズ27と基板1との
間の距離をbとすると、1/a+1/b=1/f(fは
イメージングレンズ27の焦点距離)の関係が成立す
る。光学系の焦点距離、倍率を変更するときは、イメー
ジングレンズ27に設けられたZ調整機構36と、マス
ク25の駆動機構を用い、これらの位置を調整すること
によって行う。
When the distance between the mask 25 and the imaging lens 27 is a and the distance between the imaging lens 27 and the substrate 1 is b, 1 / a + 1 / b = 1 / f (f is the focus of the imaging lens 27) The relationship of (distance) is established. When changing the focal length and magnification of the optical system, the Z adjustment mechanism 36 provided in the imaging lens 27 and the drive mechanism of the mask 25 are used to adjust these positions.

【0039】以上説明した実施例ではデバイスホール3
の形成にエキシマレーザを用いた。理由は以下の通りで
ある。YAGレーザ、CO2 レーザあるいはArレーザ
等の他の加工用レーザでの加工はレーザ光の熱エネルギ
により材料を加工するものであるのに対し、エキシマレ
ーザでは先に説明したようにエキシマレーザ光による樹
脂材料の光化学変化を利用する。
In the embodiment described above, the device hole 3
An excimer laser was used to form the. The reason is as follows. Processing with other processing lasers such as a YAG laser, a CO 2 laser, or an Ar laser is to process a material with the thermal energy of laser light, whereas with an excimer laser, as described above, excimer laser light is used. Utilizing photochemical changes in resin materials.

【0040】そのため、加工部分の形状が他のレーザ加
工に比べ非常にシャープで所望の領域を正確に加工でき
る。しかも非加工物以外の材料例えば銅箔にはダメージ
を与えない。
Therefore, the shape of the processed portion is much sharper than that of other laser processing, and a desired region can be processed accurately. Moreover, it does not damage materials other than the non-processed material such as copper foil.

【0041】しかし、放熱板となる銅箔部分を損傷しな
いように加工制御できればエキシマレーザ以外のレーザ
でデバイスホールを形成することも可能である。また、
デバイスホールの加工制御が可能であればレーザ加工で
なく、ドリル等の機械加工も利用できる。
However, it is possible to form the device hole by a laser other than the excimer laser as long as the processing can be controlled so as not to damage the copper foil portion serving as the heat dissipation plate. Also,
If it is possible to control the processing of the device hole, mechanical processing such as drilling can be used instead of laser processing.

【0042】また、デバイスホールの大部分を機械加工
で行い、銅箔に近い部分の樹脂基板についてはレーザ加
工を行うといった2段階の加工工程を採用することもで
きる。
It is also possible to employ a two-step processing step in which most of the device holes are machined and laser processing is performed on the resin substrate near the copper foil.

【0043】本発明は上記開示の実施例に限るものでは
なく、当業者であれば開示にもとづきて様々な改良や変
更が可能であることは言うまでもない。
It is needless to say that the present invention is not limited to the embodiments disclosed above, and various modifications and changes can be made by those skilled in the art based on the disclosure.

【0044】[0044]

【発明の効果】金属箔の放熱領域を回路パターンと同時
に形成し、樹脂基板に設けた穴の中に回路素子を埋設し
て穴の底の露出した金属箔と回路素子とを接着すること
によって回路基板を薄く製造できる。
The heat dissipation area of the metal foil is formed at the same time as the circuit pattern, the circuit element is embedded in the hole provided in the resin substrate, and the exposed metal foil at the bottom of the hole is bonded to the circuit element. The circuit board can be manufactured thinly.

【0045】しかも回路パターンと同じ材料で同時に作
った金属箔の放熱板を介して回路素子からの熱の放散が
行われるので、わざわざヒートシンクを別に用意して基
板に接着する必要がなく、信頼性が高く薄形化と放熱性
の向上とを実現した回路基板を低コストで得ることがで
きる。
Moreover, since the heat is dissipated from the circuit element through the metal foil heat dissipation plate made of the same material as the circuit pattern at the same time, it is not necessary to separately prepare a heat sink and bond it to the substrate, which improves reliability. It is possible to obtain a circuit board having a high cost, a reduced thickness, and improved heat dissipation at a low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例による回路基板の断面図であ
る。
FIG. 1 is a cross-sectional view of a circuit board according to an exemplary embodiment of the present invention.

【図2】 図1の回路基板の製造工程を説明するための
図である。
FIG. 2 is a diagram for explaining a manufacturing process of the circuit board of FIG.

【図3】 エキシマレーザによるデバイスホールの加工
装置の外観図である。
FIG. 3 is an external view of a device hole processing apparatus using an excimer laser.

【図4】 従来の技術による回路基板の断面図である。FIG. 4 is a cross-sectional view of a conventional circuit board.

【図5】 従来の技術による回路基板の断面図である。FIG. 5 is a cross-sectional view of a conventional circuit board.

【符号の説明】[Explanation of symbols]

1・・・・・樹脂基板 2・・・・・半導体素子(IC) 3・・・・・デバイスホール 4・・・・・回路パターン 5・・・・・放熱板 6・・・・・接着材 7・・・・・封止樹脂 8・・・・・アルミパッド 9・・・・・Au線 1 ... Resin substrate 2 ... Semiconductor element (IC) 3 ... Device hole 4 ... Circuit pattern 5 ... Heat sink 6 ... Adhesion Material 7: Sealing resin 8: Aluminum pad 9: Au wire

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/00 N 6921−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/00 N 6921-4E

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 樹脂基板の面の上に金属箔を形成する工
程と、 前記金属箔に該金属箔による回路パターンと回路素子の
放熱領域のパターンとを形成する工程と、 前記樹脂基板の前記放熱領域のパターンの反対側の面に
レーザ光を照射して照射領域の前記樹脂基板部分を除去
し、前記回路素子が内包できるような穴を形成して前記
放熱領域の金属箔を露出させる工程と、 前記穴に前記回路素子を挿入して前記回路素子と前記放
熱領域の露出した金属箔とを接着する工程とを有する回
路基板の製造方法。
1. A step of forming a metal foil on the surface of a resin substrate; a step of forming a circuit pattern of the metal foil and a pattern of a heat dissipation area of a circuit element on the metal foil; A step of exposing the metal foil in the heat dissipation area by irradiating the surface of the heat dissipation area opposite to the pattern with laser light to remove the resin substrate part in the irradiation area and forming a hole in which the circuit element can be included. And a step of inserting the circuit element into the hole and adhering the circuit element and the exposed metal foil of the heat radiation area to each other.
【請求項2】 前記レーザ光がエキシマレーザの出力光
であり、前記樹脂基板の前記放熱領域のパターンの反対
側の面に該エキシマレーザの出力光を照射して照射領域
の前記樹脂基板部分を分解して除去する請求項1記載の
回路基板の製造方法。
2. The laser light is output light of an excimer laser, and the output light of the excimer laser is applied to a surface of the resin substrate opposite to the pattern of the heat radiation area to expose the resin substrate portion in the irradiation area. The method for manufacturing a circuit board according to claim 1, wherein the circuit board is disassembled and removed.
【請求項3】 前記回路素子が半導体素子である請求項
1ないし2記載の回路基板の製造方法。
3. The method for manufacturing a circuit board according to claim 1, wherein the circuit element is a semiconductor element.
【請求項4】 樹脂基板と、 前記樹脂基板の面に金属箔により形成された回路パター
ンと回路素子の放熱領域と、 前記樹脂基板の前記放熱領域が形成された面と反対側の
面に前記放熱領域の金属箔が露出するように形成され、
前記回路素子を内包可能な穴と、 前記穴の底に露出した前記金属箔の面に接着された前記
回路素子とを有する回路基板。
4. A resin substrate, a circuit pattern formed of a metal foil on the surface of the resin substrate, and a heat dissipation area of a circuit element, and the surface of the resin substrate opposite to the surface on which the heat dissipation area is formed. It is formed so that the metal foil in the heat dissipation area is exposed,
A circuit board having a hole capable of containing the circuit element and the circuit element bonded to a surface of the metal foil exposed at the bottom of the hole.
【請求項5】 前記回路素子が半導体素子である請求項
4記載の回路基板。
5. The circuit board according to claim 4, wherein the circuit element is a semiconductor element.
JP4166360A 1992-06-24 1992-06-24 Circuit and its manufacture board Withdrawn JPH0613488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4166360A JPH0613488A (en) 1992-06-24 1992-06-24 Circuit and its manufacture board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4166360A JPH0613488A (en) 1992-06-24 1992-06-24 Circuit and its manufacture board

Publications (1)

Publication Number Publication Date
JPH0613488A true JPH0613488A (en) 1994-01-21

Family

ID=15829950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4166360A Withdrawn JPH0613488A (en) 1992-06-24 1992-06-24 Circuit and its manufacture board

Country Status (1)

Country Link
JP (1) JPH0613488A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685102A (en) * 1992-08-31 1994-03-25 Nec Corp Semiconductor integrated circuit device
JPH09107167A (en) * 1995-10-09 1997-04-22 Hitachi Aic Inc Manufacture of printed wiring board
JPH09130038A (en) * 1995-10-31 1997-05-16 Hitachi Aic Inc Method for manufacturing printed wiring board
EP0756444A3 (en) * 1995-07-24 1997-11-05 International Business Machines Corporation Computer system peripheral cartridges with welded seams
US5826330A (en) * 1995-12-28 1998-10-27 Hitachi Aic Inc. Method of manufacturing multilayer printed wiring board
US5935399A (en) * 1996-01-31 1999-08-10 Denso Corporation Air-fuel ratio sensor
US6068746A (en) * 1996-09-04 2000-05-30 Denso Corporation Oxygen sensor having a solid electrolyte applicable to an internal combustion engine
KR20010058584A (en) * 1999-12-30 2001-07-06 마이클 디. 오브라이언 Semiconductor package
JP2015053465A (en) * 2013-08-05 2015-03-19 ローム株式会社 Semiconductor device
KR20180112480A (en) * 2017-04-04 2018-10-12 한국산업기술대학교산학협력단 Laser direct patterning system and method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685102A (en) * 1992-08-31 1994-03-25 Nec Corp Semiconductor integrated circuit device
EP0756444A3 (en) * 1995-07-24 1997-11-05 International Business Machines Corporation Computer system peripheral cartridges with welded seams
JPH09107167A (en) * 1995-10-09 1997-04-22 Hitachi Aic Inc Manufacture of printed wiring board
JPH09130038A (en) * 1995-10-31 1997-05-16 Hitachi Aic Inc Method for manufacturing printed wiring board
US5826330A (en) * 1995-12-28 1998-10-27 Hitachi Aic Inc. Method of manufacturing multilayer printed wiring board
US5935399A (en) * 1996-01-31 1999-08-10 Denso Corporation Air-fuel ratio sensor
US6068746A (en) * 1996-09-04 2000-05-30 Denso Corporation Oxygen sensor having a solid electrolyte applicable to an internal combustion engine
KR20010058584A (en) * 1999-12-30 2001-07-06 마이클 디. 오브라이언 Semiconductor package
JP2015053465A (en) * 2013-08-05 2015-03-19 ローム株式会社 Semiconductor device
KR20180112480A (en) * 2017-04-04 2018-10-12 한국산업기술대학교산학협력단 Laser direct patterning system and method

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