JPH06120835A - Voltage addition type a/d converter - Google Patents

Voltage addition type a/d converter

Info

Publication number
JPH06120835A
JPH06120835A JP27006992A JP27006992A JPH06120835A JP H06120835 A JPH06120835 A JP H06120835A JP 27006992 A JP27006992 A JP 27006992A JP 27006992 A JP27006992 A JP 27006992A JP H06120835 A JPH06120835 A JP H06120835A
Authority
JP
Japan
Prior art keywords
voltage
converter
power supply
addition type
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27006992A
Other languages
Japanese (ja)
Inventor
Hidenao Satou
英直 佐藤
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP27006992A priority Critical patent/JPH06120835A/en
Publication of JPH06120835A publication Critical patent/JPH06120835A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a voltage addition type D/A converter which can reduce its power consumption and never deteriorates its resolution despite the limited amplitude value. CONSTITUTION:A voltage addition type D/A converter consists of plural switches SW1 used got input, a pair of voltage follower type operational amplifiers 7 and 8 which hold the voltage generated by a resistance array 4 which generates the optional voltage, the CMOS transistors TR 9 and 10 of a source follower which inputs the outputs of both amplifiers 7 and 8 to the gates, and plural CMOS inverters 2 which are connected between both TR 9 and 10. These TR 9 and 10 the amplifiers 7 and 8 are used as the power supplies of the inverters 2. Thus the voltage is supplied to each inverter 2 to make it follow the change of the impedance of the D/A converter.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a D / A incorporated in an LSI.
More specifically, the present invention relates to a voltage addition type D / A converter.

[0002]

2. Description of the Related Art Conventionally, this type of voltage addition type D / A converter is constructed by using an input switch, an inverter, a resistance ladder and the like.

3A and 3B are a circuit diagram of a main part of a D / A converter and a configuration diagram when the most significant 1 bit is turned on, for explaining an example of the conventional art. As shown in FIG. 3A, the conventional voltage addition type D / A
The converter includes switches SW1 to SW9 that are switchably connected to the high-potential power supply 11 and the low-potential power supply 12, inverters 1a and 1b serially connected to these switches, resistors 2R and R, and an output of each inverter 1b. And a resistance ladder 3 for analog-outputting a value obtained by adding the voltage to the output terminal OUT. These switches S
The high side H of W1 to SW9 is connected to the high side power supply 11,
The low side L is connected to the low side power supply 12. The resistance ladder 3 is connected between the output terminal OUT and the low potential side power supply 12. In FIG. 3A, when the upper bit is turned on, that is, only the switch SW1 is connected to the H side,
It becomes like FIG.3 (b). As shown in FIG. 3B, the output terminal OUT generates a voltage that is half the potential difference between the high-potential power supply 11 and the low-potential power supply 12. For example, LS
When this voltage addition type D / A converter is used for I,
The higher power supply 11 is a system power supply for the LSI, and the lower power supply 12 is a ground. Further, if the amplitude value is made small at the output terminal OUT, all the bits cannot be used, so the resolution is lowered.

[0004]

In the above-mentioned conventional voltage addition type D / A converter, since the system power source of the LSI is connected to the high-potential side power source and the ground is connected to the low-level side power source, the power consumption becomes large during operation. If a high resistance is used to suppress this power consumption, the area of the D / A converter becomes large, which is not suitable for LSI technology. Further, if the amplitude value is limited even if the number of bits is increased, the resolution will be reduced.

It is an object of the present invention to provide a voltage addition type D / A converter which suppresses power consumption and does not reduce resolution even if the amplitude value is limited.

[0006]

DISCLOSURE OF THE INVENTION The voltage addition formula D / of the present invention
The A converter has a resistor array for generating an arbitrary voltage, a plurality of switches for input, a pair of voltage follower operational amplifiers for maintaining the generated voltage, and an output of the operational amplifier as gate inputs. Source follower CMOS transistor and CM
It is configured to include a plurality of CMOS inverters connected between OS transistors and a resistance ladder.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram of a main part of a voltage addition type D / A converter for explaining an embodiment of the present invention. As shown in FIG. 1, the main part of this embodiment is a plurality of switches SW1 to SW9 that are opened and closed by digital signals.
And the high side (H) is the system power supply VS (5V),
The lower side (L) is connected to the ground GND (0V), respectively. These switches SW1 to SW9 are connected to the CMOS inverter 2 via the inverter 1, respectively. Each of the CMOS inverters 2 has a high-side power source V
It is connected to H and the low side power supply VL, and the output is resistance 2
It is supplied to the resistance ladder 3 including R and the resistance R. The final analog output is output to the output terminal OUT as a voltage-added value. In this embodiment, the low-side power supply VL of the COM inverter 2 is used as the low-side power supply of the resistance ladder 3.

FIG. 2 is a circuit diagram of a voltage addition type D / A converter using the most significant bit in FIG. 1 for explaining one embodiment of the present invention. As shown in FIG. 2, in this embodiment, a resistor array 4 that is connected between the system power supply VS and the ground and that generates an arbitrary voltage, an inverting amplifier 5 that inverts the generated voltage by comparing it with a reference voltage VR, A pair of voltage follower operational amplifiers 7 and 8 for maintaining the inverted voltage and the normal voltage, CMOS transistors 9 and 10 of the source follower for supplying the outputs of the operational amplifiers 7 and 8 to the gates, respectively, and the CMOS described above.
Inverter 2, resistance ladder and input switch SW
1 and.

As described above, when the LSI system power supply VS is used as the high-potential power supply and the ground potential is used as the low-potential power supply, the arbitrary voltage obtained by the resistor array 4 is set to 1.9V. In addition, the reference voltage V of the inverting amplifier 5
When R is 2.4V, a voltage of 2.9V is generated at the output point 6. The obtained voltages are the high-side power supply VH and the low-side power supply VL of the CMOS inverter 2 in the voltage follower operational amplifiers 7 and 8 and the source follower CMOS transistors 9 and 10. Similarly, these voltages V
H and VL serve as power sources for the CMOS inverter 2 for all bits.

Therefore, the bits other than the most significant bit are also constructed as shown in FIG. 2, and the voltages of all the bits are combined by the "superposition principle" and output to the output terminal OUT of the D / A converter.

All bit switches SW1 to SW9
Is off, the P-type transistor of the CMOS inverter 2 is in a cut-off state, and the N-type transistor 9 that creates the high-side power supply VH of the CMOS inverter 2 loses the current path. At the same time, the P-type transistor 10 that creates the low-side power supply VL of the CMOS inverter 2 also has no current path.

In the above embodiment, the amplitude is 1 Vp-p.
When trying to obtain the sine wave of
Power supply voltage difference of 1V (2.9V-1.9V), C
The power supply for the MOS inverter 2 is the system power supply (5
Compared with the case of V), it can be operated with power consumption of about 1/20, and since all bits from MSB to LSB can be used, the resolution can be improved.

[0013]

As described above, the voltage addition type D / A converter of the present invention uses the CMOS inverter in the decoding section, and the power source of the CMOS inverter is the voltage follower operational amplifier and the source follower CM.
By using the OS transistor, a constant voltage can be obtained even if the impedance changes depending on the decoded value, so that there is an effect that power consumption can be suppressed.

Further, by turning off the switches of all the bits of the D / A converter, the CMOS of the source follower can be obtained.
Since the current path of the transistor can be stopped and power down can be performed, power consumption can be further suppressed. Furthermore, the present invention has the effect that the resolution can be improved by performing voltage addition using all bits from MSB to LSB.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a voltage addition type D / A converter for explaining an embodiment of the present invention.

FIG. 2 is a circuit diagram of a voltage addition type D / A converter using the most significant 1 bit in FIG. 1 for explaining one embodiment of the present invention.

FIG. 3 is a voltage addition type D / A for explaining a conventional example.
It is a circuit diagram showing an outline when the main part of the converter and the most significant 1 bit are turned on.

[Explanation of symbols]

 1 inverter 2 CMOS inverter 3 resistance ladder 4 resistance array 5 inverting amplifier 7,8 operational amplifier 9 source follower NchMOS transistor 10 source follower PchMOS transistor SW1 to SW9 switch VS LSI system power supply VH inverter high side power supply VL inverter low side power supply VR reference voltage OUT output terminal

Claims (1)

[Claims]
1. A resistor array for generating an arbitrary voltage,
A plurality of switches for input, a pair of voltage follower type operational amplifiers for maintaining the generated voltage, a CMOS transistor of a source follower having the output of the operational amplifier as a gate input, and a CMOS transistor connected between these CMOS transistors. Voltage summing equation D including a plurality of CMOS inverters and a resistance ladder
/ A converter.
JP27006992A 1992-10-08 1992-10-08 Voltage addition type a/d converter Pending JPH06120835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27006992A JPH06120835A (en) 1992-10-08 1992-10-08 Voltage addition type a/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27006992A JPH06120835A (en) 1992-10-08 1992-10-08 Voltage addition type a/d converter

Publications (1)

Publication Number Publication Date
JPH06120835A true JPH06120835A (en) 1994-04-28

Family

ID=17481094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27006992A Pending JPH06120835A (en) 1992-10-08 1992-10-08 Voltage addition type a/d converter

Country Status (1)

Country Link
JP (1) JPH06120835A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010288247A (en) * 2009-06-12 2010-12-24 Analog Devices Inc Digital-to-analog converters having circuit architectures to overcome switch loss
US20130120176A1 (en) * 2011-11-14 2013-05-16 Semtech Corporation Resistive digital-to-analog conversion

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010288247A (en) * 2009-06-12 2010-12-24 Analog Devices Inc Digital-to-analog converters having circuit architectures to overcome switch loss
DE102009058793B4 (en) * 2009-06-12 2015-09-17 Analog Devices Inc. Digital-to-analog converter with circuit architectures to eliminate switch losses
US20130120176A1 (en) * 2011-11-14 2013-05-16 Semtech Corporation Resistive digital-to-analog conversion
US8487800B2 (en) * 2011-11-14 2013-07-16 Semtech Corporation Resistive digital-to-analog conversion

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