JPH06112818A - Pll preset method and preset type pll circuit - Google Patents

Pll preset method and preset type pll circuit

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Publication number
JPH06112818A
JPH06112818A JP4261706A JP26170692A JPH06112818A JP H06112818 A JPH06112818 A JP H06112818A JP 4261706 A JP4261706 A JP 4261706A JP 26170692 A JP26170692 A JP 26170692A JP H06112818 A JPH06112818 A JP H06112818A
Authority
JP
Japan
Prior art keywords
data
preset
means
unlock
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4261706A
Other languages
Japanese (ja)
Inventor
Kazuhide Asada
和秀 浅田
Original Assignee
Icom Inc
アイコム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icom Inc, アイコム株式会社 filed Critical Icom Inc
Priority to JP4261706A priority Critical patent/JPH06112818A/en
Publication of JPH06112818A publication Critical patent/JPH06112818A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the C/N, simplify the circuit and to make preset data accurate. CONSTITUTION:The preset type PLL circuit comprising a phase comparator 1, a variable frequency divider 8, a VCO 2, a loop filter 4, a ROM 6, a RAM 7 and a CPU 5 is provided with a D/A converter 3 and an unlock detection means 9. Simultaneously at application of power, data corresponding to a preset frequency are read out and fed to a variable frequency divider 8, a VCO 2 is oscillated at a minimum frequency, then control data are changed by a specified value each and fed to the VCO 2 via D/A converter 3 and an unlock state is monitored by an unlock detection means. Then the data in unlock state are extracted and corrected by a data correction means and written in the RAM 7. The stored preset data are read out of the RAM 7 and inputted to the D/A converter 3 to control the VCO 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
More particularly, the present invention relates to a PLL preset method and a preset type PLL circuit.

[0002]

2. Description of the Related Art In a PLL circuit as shown in FIG. 7, when a phase is compared by a phase comparator 11 for each frequency division ratio (hereinafter referred to as N data) of a variable frequency divider 18, a control voltage corresponding to the phase difference is obtained. Goes out of the phase comparator 11, is smoothed by the loop filter 14, and then the voltage-controlled oscillator (hereinafter referred to as VCO) 12 is controlled by the voltage so that the frequency is locked.

Conventionally, as a method for switching the oscillation frequency of a PLL circuit at high speed, a microprocessor (hereinafter referred to as CP
U. ) 15 controls the variable frequency divider 18, and the digital / analog converter (hereinafter referred to as D / A converter) 13 is controlled by preset data from a random access memory (hereinafter referred to as RAM) 17 as storage means. In some cases, the operation of directly controlling the VCO 12 is switched through the preset data for each preset frequency.

In this type of PLL circuit, for example, at the time of manufacture and shipment, the input control voltage of the VCO 12 when the phase comparator is locked is read by an analog / digital converter (hereinafter referred to as A / D converter) 10 and digitalized. I fixed it to a signal,
Considering the error at the time of oscillation of the VCO 12 due to the influence of heat generation of the device in the CPU 15, after correcting it to a slightly lower value, the RAM 1
No. 7, stored in memory 7, taken out as needed, and used as preset data.

The above-mentioned control by the CPU 15 is performed by a control program and data of a read only memory (hereinafter referred to as ROM) 16.

[0006]

However, in the above-mentioned conventional method, V which has a high impedance at the time of locking.
Since the input control voltage of CO is A / D converted and the wiring is routed to take out the data, it is susceptible to disturbance, and rather the deterioration of the carrier / noise ratio (hereinafter referred to as C / N ratio) of the entire PLL circuit is caused. In addition to the cause, an A / D converter and a buffer amplifier accompanying it are also required, which complicates the circuit.

Further, considering the error at the time of oscillation of the VCO due to the influence of heat generation of the equipment, the preset data value is corrected to a slightly lower value, stored and then used, so that the preset data becomes inaccurate. Tended to.

The present invention has been proposed in view of the above problems, and an object thereof is to improve the C / N ratio and simplify the circuit, and to obtain more accurate preset data.

[0009]

In order to solve the above problems, in the PLL preset method of the present invention, a phase comparator, a variable frequency divider, and a storage means for storing data corresponding to each frequency division ratio. And a voltage controlled oscillator preset by the data, and an unlock detecting means for outputting an unlock signal when the phase comparator is in an unlocked state. Changing the input data to the voltage controlled oscillator while monitoring the signal, detecting the upper and lower limits of the lock range, and output the input data to the voltage controlled oscillator corresponding to the upper and lower limits of the lock range, A method of correcting the output data and writing the obtained data in the storage means was used.

Further, in the preset type PLL circuit of the present invention, a phase comparator, a variable frequency divider, a storage means for storing data corresponding to each frequency division ratio, and a voltage control type preset by the data. In a preset type PLL circuit including an oscillator, an unlock detecting unit that outputs an unlock signal when the phase comparator is in an unlocked state, a data changing unit that changes input data to the voltage controlled oscillator, and Data output means for outputting the data given to the voltage-controlled oscillator at the time when the unlock signal of the unlock detection means is no longer output and at the time when it is output again, and the both data output from the data output means And a correction means for writing the obtained data in the storage means.

Further, in a preset type PLL circuit including a phase comparator, a variable frequency divider, a storage means for storing data corresponding to each frequency division ratio, and a voltage controlled oscillator preset by the data. When the phase comparator is in the unlocked state, unlock detecting means for outputting an unlock signal, data changing means for changing input data to the voltage controlled oscillator, and rising of the unlock signal of the unlock detecting means Data output means for outputting the data given to the voltage controlled oscillator at the time point of
Correcting the data output from the data output means,
Data correction means for writing the data obtained thereby into the storage means are provided.

[0012]

In the PLL preset method and preset type PLL circuit of the present invention, first, N data corresponding to a desired frequency is input to the variable frequency divider, and the VCO receives the VC.
Data corresponding to the lowest oscillation frequency or the highest oscillation frequency of O is input. As a result, the VCO oscillates at the lowest frequency or the highest frequency, and the oscillating frequency is frequency-divided by the variable frequency divider and then compared in phase with the reference frequency by the phase comparator.

In this state, the lock range in which the phase comparator is locked due to variations in the constituent elements is unknown, but since the input data is far from the expected lock range, it is not locked. An unlock signal is output by the unlock detection means.

Next, when the input data to the VCO is changed by the data changing means, the lock range of the phase comparator is finally entered and the unlock signal is no longer output. Input data to the VCO at this time is output by the data output means and temporarily stored in the storage means.

Subsequently, when the input data to the VCO is changed from there, it goes out of the lock range of the phase comparator and the unlock signal is output again. Input data to the VCO at this time is output by the data output means and temporarily stored in the storage means. Next, the temporarily stored data is taken out and corrected by the data correction means to obtain new data, which is stored in the storage means. It will be used as preset data from the next time.

When the data changing means largely changes the input data to the VCO while monitoring the unlock signal, the lock range is eventually reached and the unlock signal is no longer output. From the time when the unlock signal is no longer output, if the input data to the VCO is changed to the increasing direction and the decreasing direction by the data changing means,
Unlock signals appear at two points, the upper end and the lower end of the lock range. The input data of the VCO at that time is output by the data output means and temporarily stored in the storage means.

Then, the temporarily stored data is taken out and corrected by the data correction means to obtain new data.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The PLL preset method and preset type PLL circuit of the present invention will be described in detail below with reference to an apparatus using the preset type PLL circuit and the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a preset type PLL circuit of this embodiment, FIG. 2 is a flow chart of a control program built in the ROM of FIG. 1, and FIG. 3 is FIG.
FIG. 6 is a time chart diagram of data and unlock signals output from the CPU to the D / A converter. Where C
The data of the data changing means, the data outputting means, and the data correcting means controlled by the PU are digital signals,
The data value of FIG. 3B is converted into an analog value and expressed.

In the figure, reference numeral 1 is a phase comparator, 2 is a VCO,
3 is a D / A converter, 4 is a loop filter, 5 is a CP
U and 6 are ROMs containing a control program including data changing means, data output means, and data correcting means and data, 7 is a RAM, 8 is a variable frequency divider, and 9 is an amplifier included in the phase comparator 1. It is a lock detecting means.

A description will be given mainly with reference to the flow chart of FIG. 2 and with reference to FIGS. 1 and 3. In step S1, the N data N1 corresponding to the preset frequency f1 is read out from the ROM 6 in order to preset the preset frequency f1 and input to the variable frequency divider 8. In FIG. 2, N data corresponding to the preset frequency f is data N,
Variable data for determining the preset frequency f is data D (N), and here, data corresponding to the first preset frequency f1 is data N1, data D (N1).
I am trying.

The data D (0) is a preset data initial value, which is a constant numerical value.

Next, in step S2, as shown in FIG.
At the timing T1, the preset data initial value D (0) corresponding to the oscillation minimum frequency peculiar to VCO2 is changed to the data D
(N1) is substituted. Then, in step S3, the prescribed value d is added to the data D (N1), and then in step S4, it is input to the D / A converter 3. Then, an output voltage corresponding thereto is output from the D / A converter 3 and applied to the VCO 2, and the VCO 2 oscillates according to the output voltage.

Here, when the input voltage of VCO2 rises,
The output frequency is also increased.

When the output frequency of the VCO 2 enters the variable frequency divider 8, it is frequency-divided according to the N data N1, and the phase of the frequency and the reference frequency is compared by the phase comparator 1. Since the data D (N1) is a value sufficiently lower than the lock range of the frequency f1, at this time, the unlock detecting means 9 incorporated in the phase comparator 1 detects the unlock state and outputs the unlock signal. . This is the stage of step S5.

When the unlock signal is output, as shown in step S3, the data changing means raises the data D (N1) by the specified value d according to the instruction of the CPU 5, and sets it as the updated data D (N1). , Is input to the D / A converter 3 again in step S4. When the output voltage of the D / A converter 3 rises and is applied to VCO2, the oscillation frequency of VCO2 rises. The oscillation frequency is again checked for the locked state by the phase comparator 1 through the above-mentioned path.

The above operation is repeated until the unlock signal is no longer output. Figure 3 shows how this data is added.
[B] of.

When the lock range is entered, the unlock detector 9 detects that the phase comparator 1 is in the locked state. Then, at the timing T2 in FIG. 3B,
The data output means reads and outputs the data D (N1 ') in the CPU 5. This is temporarily stored in the RAM 7 as the data L (N1) of the lower end frequency of the lock range. This is step S6.

Data L (N
Even after storing 1), the data is increased from the data D (N1 ') by the specified value d and input to the D / A converter 3. This state continues until the next unlock signal is detected. This is steps S7, S8 and S9. In the locked state, the phase comparator 1, the VCO 2, the loop filter 4, and the variable frequency divider 8 operate to bring the frequency close to the preset frequency.

After the above operation is repeated several times, when the unlock signal U2 is output at the timing T3,
The data output means which received it reads the data D (N1 ") in the CPU 5 at that time in step S10, and reads this data H (N) of the upper limit frequency of the lock range.
As 1), it is temporarily stored in the RAM 7.

At the timing T3, the value of the data H (N1) of the upper limit frequency of the lock range is obtained, and at the same time, the data change is stopped. Next, in step S11, a value obtained by subtracting the specified value d from the lower limit frequency data L (N1) of the lock range and the upper limit frequency data H (N1) are averaged to obtain an average value M.
(N1) is output and is written in the RAM 7 as preset data in step S12. Here, FIG. 3 (B)
RL is the actual lock range, and the above average value M
(N1) has almost no error from the center value of the lock range.

As described above, the writing of the N data N1 and the preset data M (N1) corresponding to one preset frequency f1 is completed.

Further, if the frequency to be preset remains, the process returns to the first step S1 in step S13, and at timing T4, the next preset frequency f
The data N2 corresponding to 2 is read and input to the variable frequency divider 8, and at almost the same time, the preset data initial value D (0) corresponding to the oscillation minimum frequency peculiar to VCO 2
Is assigned to D (N) at step S3, the specified value d is added at step S3, and the result is input to the D / A converter 3. The above operation is repeated.

Needless to say, if the surrounding environment is the same, the preset data initial value D (0) is always constant. The control of the above operation by the CPU 5 is executed by the control program and data written in the ROM 6.

As the data to be first input to the D / A converter 3, the preset data corresponding to the maximum oscillation frequency peculiar to VCO2 is used instead of the preset data initial value D (0) corresponding to the oscillation minimum frequency peculiar to VCO2. Initial values may be entered, in which case the data modification means will decrease the data rather than increase it. The upper end data and the lower end data are exchanged, but the other data output means and data correction means are the same.

Further, the preset data for controlling the VCO 2 is a digital value in the case of the embodiment, which is D /
Although it is converted into an analog value by the A converter 3, the preset data is converted into an analog value and directly converted into a VC value.
You may control O2. (Example 2)

A PLL presetting method and a preset type PLL circuit having the same configuration as that of the first embodiment but having a slightly different operation will be described with reference to FIGS. 4, 5 and 6.
The details will be described. 4 and 5 are a series of flowcharts of the second embodiment. The steps for performing the same operations as those in the first embodiment are slightly omitted.

In step S21, in order to preset the preset frequency f11, N data N11 corresponding to the preset frequency f11 is read from the ROM 6 and input to the variable frequency divider 8. Here, as in the first embodiment, the N data corresponding to the preset frequency f is set as the data N,
Variable data for determining the preset data are data S (N) and data D (N). Here, data corresponding to the first preset frequency f11 is data N11, data S (N11), data D (N11). I am trying. In addition,
The data S (0) is an initial value of preset data and is a constant numerical value.

Next, in step S22, the preset data initial value S (0) corresponding to the lowest oscillation frequency peculiar to the VCO 2 is set.
Is substituted into the data S (N11) and at the same time step S
The specified value h is added at 23 and input to the D / A converter 3 at step T24 at timing T11. VCO2
Since the peculiar oscillation minimum frequency is sufficiently away from the lock range, the unlock detection means outputs the unlock signal in step S25. Step S25, Step S2
3. In step S24, while the unlock signal is being output, the data changing unit increases the data by the specified value h, and this operation is repeated until the frequency is locked.

The specified value h is set to a value slightly smaller than the expected lock range width RL.

At timing T12, the first locked data S (N11 ') is transferred to data D (N) at step S26.
11), a prescribed value d smaller than the prescribed value h is added to it in step S27, and the result is input to the D / A converter 3 in step S28. After that, step S29 and step S2
7. In step S28, the unlock signal is monitored while adding data at intervals of the specified value d. Then, at the timing T13 when the unlock signal is output, the data D (N11 ') output by the data output means is set as the upper limit frequency data H (N11) of the lock range in step S30 to be R.
Temporarily store in AM7.

Subsequently, after the prescribed value d is subtracted from the data D (N11) in step S31, it is input to the D / A converter 3 in step S32 at timing T14, and then in steps S32, S33 and S3.
At 1, the data is subtracted by the prescribed value d and the state of the output of the unlock signal is checked. At the timing T15 when the unlock signal is output, the data D (N11 ") output by the data output means is temporarily stored in the RAM 7 as the lower limit frequency data L (N11) of the lock range in step S34.

Then, the data averaging process is performed in step S35, and the writing process is performed in step S36.
If there is another frequency to be preset, step S37.
Then, the process returns to step S21, and the above operation is repeated.

In the preset type PLL circuit of this embodiment, the amount of data change is set to be large at first and set to be small after finding the lock range, so that the lock range can be found quickly, and the upper and lower frequencies can be found. Is known, and the preset data becomes more accurate.

[0045]

According to the PLL preset method and the preset type PLL circuit of the present invention, V which has been conventionally required
Since the circuit of the A / D converter for measuring the input voltage of CO is unnecessary, the wiring and mounting parts are reduced, the cost is reduced, and the wiring is not drawn from the input of the VCO, which has high impedance. Therefore, the C / N ratio of the entire PLL circuit is improved.

Further, in manufacturing the preset type PLL circuit, even if there are variations in the VCO and other constituent elements, the data obtained by accurately detecting both ends of the lock range of the desired frequency are averaged to obtain the preset data. As
Since it is written in the RAM together with N data, the frequency to be preset can be oscillated more accurately, and a preset type PLL circuit having a short lockup time can be manufactured. Further, even in the case of mass production, defective products can be suppressed to a minimum and the performance can be improved.

[Brief description of drawings]

FIG. 1 is a preset type PLL according to first and second embodiments.
It is a block diagram of a circuit.

FIG. 2 is a flowchart of a control program stored in a ROM of the preset type PLL circuit according to the first embodiment.

FIG. 3 is a time chart diagram of output data and unlock signal of the CPU of the preset type PLL circuit of the first embodiment.

FIG. 4 is a flowchart of a control program stored in a ROM of a preset type PLL circuit according to a second embodiment and is a diagram showing a first half portion thereof.

FIG. 5 is a flow chart of a control program incorporated in the ROM of the preset type PLL circuit of the second embodiment, and is a diagram showing a second half portion connected to the first half portion of FIG. 4;

FIG. 6 is a time chart diagram of output data and unlock signal of the CPU of the preset type PLL circuit of the second embodiment.

FIG. 7 is a block diagram of an example of a conventional preset type PLL circuit.

[Explanation of symbols]

1 Phase Comparator 2 Voltage Controlled Oscillator (VCO) 3 Digital-Analog Converter (D / A Converter) 4 Loop Filter 5 Microprocessor (CPU) 6 Read Only Memory (ROM) 7 Random Access Memory (RAM) [Storage Means 8 variable frequency divider 9 unlock detection means S3, S7, S23, S27, S31 data change means S6, S10, S26, S30, S34 data output means S11, S35 data correction means

Claims (3)

[Claims]
1. A phase comparator, a variable frequency divider, storage means for storing data corresponding to each frequency division ratio, a voltage controlled oscillator preset by the data, and a phase comparator in an unlocked state. In the PLL preset method of the preset type PLL circuit, which includes an unlock detecting means for outputting an unlock signal at the time of, the lock range is changed by changing the input data to the voltage controlled oscillator while monitoring the unlock signal. Detecting the upper and lower limits of the lock range, outputting the input data to the voltage controlled oscillator corresponding to the upper and lower limits of the lock range, correcting the output data, and writing the obtained data in the storage means. A PLL presetting method characterized by the above.
2. A preset type PLL circuit comprising a phase comparator, a variable frequency divider, storage means for storing data corresponding to each frequency division ratio, and a voltage control type oscillator preset by the data. When the phase comparator is in the unlocked state, unlock detecting means for outputting an unlock signal, data changing means for changing the input data to the voltage controlled oscillator, and the unlock signal for the unlock detecting means are Data output means for outputting the data given to the voltage controlled oscillator at a time when the data is no longer output and a time when the data is output again, and the data output means corrects the data output from the data output means.
A preset type PLL circuit, comprising: a data correction means for writing the data obtained thereby into the storage means.
3. A preset type PLL circuit comprising a phase comparator, a variable frequency divider, a storage means for storing data corresponding to each frequency division ratio, and a voltage controlled oscillator preset by the data. In the case where the phase comparator is in the unlocked state, unlock detecting means for outputting an unlock signal, data changing means for changing input data to the voltage controlled oscillator, and unlock signal for the unlock detecting means. Data output means for outputting data given to the voltage controlled oscillator at the time of rising, and correcting the data output from the data output means,
A preset type PLL circuit, comprising: a data correction means for writing the data obtained thereby into the storage means.
JP4261706A 1992-09-30 1992-09-30 Pll preset method and preset type pll circuit Pending JPH06112818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4261706A JPH06112818A (en) 1992-09-30 1992-09-30 Pll preset method and preset type pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4261706A JPH06112818A (en) 1992-09-30 1992-09-30 Pll preset method and preset type pll circuit

Publications (1)

Publication Number Publication Date
JPH06112818A true JPH06112818A (en) 1994-04-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP4261706A Pending JPH06112818A (en) 1992-09-30 1992-09-30 Pll preset method and preset type pll circuit

Country Status (1)

Country Link
JP (1) JPH06112818A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7065668B2 (en) 2000-03-31 2006-06-20 Seiko Epson Corporation Apparatus for selecting and outputting either a first clock signal or a second clock signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7065668B2 (en) 2000-03-31 2006-06-20 Seiko Epson Corporation Apparatus for selecting and outputting either a first clock signal or a second clock signal

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