JPH06112810A - Digital ic device - Google Patents

Abstract

PURPOSE:To minimize the power consumption required for each mode by reducing the power consumption of a circuit block not in use. CONSTITUTION:A clock signal with a usual frequency from an oscillating circuit 10 or a clock signal with a frequency lower than the usual frequency resulting from frequency-dividing the signal from the circuit 10 at a frequency divider circuit 14 is selected by selectors 13A, 13B and fed to clock input terminals of circuit blocks 4A, 4B being different function blocks in a digital IC. The selectors 13A, 13B are selectively controlled with a signal from a clock frequency control logic circuit 12 receiving the signal from mode changeover switches 1, 2, and the clock signal with a lower frequency than the usual frequency is sent to the circuit block not in use depending on the mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital IC device whose inside is divided into several functional blocks.

[0002]

2. Description of the Related Art In recent years, various digital devices for recording / reproducing, transmitting / receiving digital signals obtained by digitizing audio signals and video signals have been developed and provided on the market. Many types of ICs (integrated circuits) for digital signal processing used in various digital devices are known.

Many such digital ICs have a plurality of functions and operation modes. For example, a recording / reproducing signal processing IC of a digital audio tape recorder (DAT) is roughly divided into a recording mode and a reproducing mode. This multi-function type IC is generally divided into a plurality of functional blocks in its interior, and some of these functional blocks may not be used depending on the operation mode. For example, in the case of the recording / reproducing signal processing IC, in the recording mode, the block used only for reproducing is unnecessary and does not operate substantially effectively.

[0004]

By the way, as described above, in a certain predetermined mode (for example, the recording mode),
If data is input or a clock is input to a block that is not used (for example, the block dedicated to the above reproduction), it means that the output of the block is operating even though it is not used at all. So-called CMO
In a digital IC using the S process, a current flows when the internal 1/0 state changes, so if the 1/0 state changes due to data input or clock input even in an unused block, the current will flow. It will be consumed.

The present invention has been made in view of the above circumstances, and regarding the functional blocks that are not used depending on the operation mode, the current consumption during the operation mode is suppressed to the minimum necessary, and the power consumption of the IC is reduced. An object is to provide a digital IC device that can be reduced.

[0006]

According to the digital IC device of the present invention, the inside is divided into a plurality of functional blocks, the first block used in a predetermined operation mode and the second block not used. In a predetermined operation mode, by supplying a clear signal to a clear terminal of a flip-flop of the second block, or fixing all input signals to the second block. Or by stopping the clock to the flip-flop of the second block, or changing the clock to the dynamic flip-flop of the second block to a clock of a frequency lower than usual and supplying the clock. Or a clear signal is supplied to the clear terminal of the flip-flop of the second block. By supplying a clock of a frequency lower than normal to the clock input terminal with, to solve the problems described above.

[0007]

With respect to the second block which is not used in the predetermined operation mode, the flip-flop is cleared, the input signal is fixed, or the clock is stopped or switched to a low frequency to flow through the second block. The amount of current is reduced, and the power consumption can be suppressed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments of a digital IC device according to the present invention will be described below with reference to the drawings. 1 to 4 are digital ICs according to the present invention.
It is a block diagram which respectively shows the schematic structure of the 1st-4th Example of an apparatus, and the changeover switches 1 and 2 and the circuit blocks 4A and 4B are used in any Example.

1 to 4, at least a first functional block inside the digital IC device is used.
The circuit block 4A and the second circuit block 4B are provided. These circuit blocks 4A and 4B are
For example, it may or may not be used depending on the operation mode, such as a recording-only circuit section and a reproduction-only circuit section in a recording / reproducing signal processing IC for a DAT (digital audio tape recorder). It corresponds to the resulting circuit block. The operation modes in this case are the first operation mode in which only the first circuit block 4A is used and the second circuit block 4B is not used, and the first circuit block 4A in which only the second circuit block 4B is used. The second operation mode which is not used is considered first, but in addition to this, the first circuit block 4A
Neither the second circuit block 4B is used
And the third operation mode in which both the first circuit block 4A and the second circuit block 4B are used together.

The circuit block dedicated to recording in the DAT recording / reproducing signal processing IC described above is the circuit block 4.
A specific example of the above-described four operation modes when the reproduction-only circuit is the circuit block 4B will be described. Although it is clear that the first operation mode corresponds to the recording mode and the second operation mode corresponds to the reproduction mode, the 0th operation mode further includes fast-forwarding and rewinding of the tape. When signal processing for recording and reproduction is not performed as described above, it can be said to be a standby mode for a circuit for recording and reproduction. The third operation mode is a mode in which both recording signal processing and reproduction signal processing are required at the same time, such as a recording (recording) simultaneous monitor mode.

The changeover switches 1 and 2 change the changeover state according to the operation modes as described above, and the four changeover modes may be represented according to the changeover states of the two changeover switches 1 and 2. it can. For example, changeover switch 1
When “L” is selected as “L” (low level) and the changeover switch 2 is selected as “H” (high level), “LH” is represented as “01” and corresponds to the first operation mode. The state "00" of the changeover switches 1 and 2 to the 0th operation mode, the state "10" to the second operation mode, and the state "11" to the third operation mode. Can be adapted. This changeover switch 1,
The state of No. 2 and the correspondence with the above-mentioned four operation modes are not limited to the above specific examples, and may be set arbitrarily.

First, FIG. 1 shows a digital IC according to the present invention.
It is a block circuit diagram which shows the schematic structure of the 1st Example of an apparatus. In FIG. 1, the output signals from the changeover switches 1 and 2 are sent to the clear control logic circuit 3 as a signal instructing the above-mentioned currently selected operation mode. The clear control logic circuit 3 includes circuit blocks 4 in the IC according to the current operation mode.
A clear signal is sent to each clear terminal of, for example, a flip-flop of A and 4B.

As a concrete configuration of the clear control logic circuit 3, the output signal from the changeover switch 1 is inverted to the clear terminal of the circuit block 4B, and the output signal from the changeover switch 2 is inverted to the circuit block 4A. It may be configured to send to the clear terminal of. In this case, in the 0th operation mode, “L” is selected by the changeover switches 1 and 2 from the state “00”, and these are inverted in the clear control logic circuit 3 to be “H”. ", And these are sent to the clear terminals of both circuit blocks 4A and 4B, and the respective flip-flops of each circuit block 4A and 4B are brought into a clear state. In the first operation mode,
From the state "01", the changeover switch 1 selects "L" and the changeover switch 2 selects "H", and the clear control logic circuit 3 inverts "L" from the changeover switch 1 to "H". Clear signal of circuit block 4
"H" from the changeover switch 2 is inverted to the clear terminal of B and a signal of "L" (a signal that is not cleared) is sent to the clear terminal of the circuit block 4A. Therefore, the circuit block 4B is in the clear state in the normal operation state of the circuit block 4A. Similarly, in the second operation mode (state "10"), the circuit block 4A is in the clear state and the circuit block 4B is in the normal operation state, and in the third operation mode (state "11"). , The circuit blocks 4A and 4B are in the normal operation state.

In these circuit blocks 4A and 4B, the blocks which are in the clear state and are not used depending on the operation mode as described above have no change in the state of 1/0. The power consumption of the entire circuit can be suppressed. This is a remarkable effect particularly in the case of an IC manufactured by a so-called CMOS process.

Next, FIG. 2 shows, as a second embodiment according to the present invention, an example in which the input to each circuit block 4A, 4B is fixed. That is, the signals from the changeover switches 1 and 2 are sent to the input enable control logic circuit 5, and one output signal from the input enable control logic circuit 5 is used to control n inputs to the circuit block 4A. N AND gates 6A ₁ , 6
A _2, · · ·, sent to 6A _n, input enable control logic circuit other output signal from the 5, the circuit of m AND gates 6B ₁ for controlling the m input to the block 4B, 6B ₂ , ..., sending to 6B _m . n
The AND gates 6A ₁ , 6A ₂ , ..., 6A _n are provided with n input signals sent to the circuit block 4A from other circuit parts or the outside of the IC or the like at the respective input terminals 7A ₁ , 7A ₂ ,.
.., m AND gates 6 supplied from 7A _n
B ₁ , 6B ₂ , ..., 6B _m have other circuit parts or ICs.
M input signals sent from the outside or the like to the circuit block 4B are supplied from the respective input terminals 7B ₁ , 7B ₂ , ..., 7B _m . n AND gates 6A ₁ , 6A ₂ , ...
The output signals from 6A _n are sent to the _n input terminals IA ₁ , IA ₂ , ..., IA _n of the circuit block 4A,
The output signals from the _m AND gates 6B ₁ , 6B ₂ , ..., 6B m are the m input terminals I of the circuit block 4B.
Sent to B ₁ , IB ₂ , ..., IB _m .

In this case, the AND gate to which the "H" signal is sent from the input enable control logic circuit 5 becomes conductive (ON), each input signal is supplied to the circuit block, and the "L" signal is sent to the AND gate. Is cut off (OFF), and each input signal to the circuit block is fixed to, for example, "L". For example, from the input enable control logic circuit 5 to the n AND gates 6A ₁
When "H" signal to ～6A _n is sent, these AND gates 6A ₁ ~6A _n are all conductive (ON) in a state, the input signal circuit block 4A from the input terminal 7A ₁ ~7A _n the n is respectively supplied to the input terminal IA ₁ ~IA _n, also for example, input enable control logic circuit 5 from the m aND gates 6B ₁ ~6B _m of
When the "L" signal is sent to
B ₁ ～6B _m becomes all blocking (off) state, is secured to all the input signals to the m input terminal IB ₁ ~IB _m circuit block B is "L" (or "0") .

As a concrete example of the input enable control logic circuit 5, the output signal from the changeover switch 1 is sent as it is to the m AND gates 6B _{1 to} 6B _m , and the output signal from the changeover switch 2 is sent as it is to the n AND gates. It may be configured to send to the gates 6A _{1 to} 6A _n . In this case, for example, in the first operation mode of the above state "01", the output of the changeover switch 1 is "L" and the output of the changeover switch 2 is "H". 6B ₁ input signal to ～6B _m is at "L" to the circuit block 4B is "L"
It is fixed to (“0”), the signals to the AND gates 6A ₁ to 6A _n are “H”, and the circuit block 4A has the input terminals 7A.
Each input signal from _{1 to} 7A _n will be supplied.
Since the other modes have similar operations, description thereof will be omitted.

According to the second embodiment as described above, since the input signal to the circuit block which is not used is fixed according to the operation mode, there is no change in the 1/0 state and the amount of current flowing is reduced. Thus, the power consumption of the entire IC circuit can be suppressed.

Next, FIG. 3 shows a third embodiment according to the present invention, showing an example in which a clock to a flip-flop or the like of an unused circuit block is stopped or cut off.
In FIG. 3, the signals from the changeover switches 1 and 2 are sent to the clock enable control logic circuit 8, and one output signal from the clock enable control logic circuit 8 controls the supply of the clock to the circuit block 4A. And the other output signal from the logic circuit 8 is sent to the AND gate 9B for controlling the supply of the clock to the circuit block 4B. The AND gates 9A and 9B are supplied with a clock signal from an oscillator circuit 10 for clock generation using a crystal oscillator 11. AND gate 9A
Is sent to the clock input terminal of the circuit block 4A, and the output signal from the AND gate 9B is sent to the clock input terminal of the circuit block 4B.

A concrete example of the clock enable control logic circuit 8 in this case is such that the output signal from the changeover switch 1 is directly sent to the AND gate 9B and the output signal from the changeover switch 2 is sent to the AND gate 9A. Good. Here, for example, the first of the above state “01”
In the operation mode of, the output of the changeover switch 1 is "L".
Since the output of the changeover switch 2 is "H", the signal from the clock enable control logic circuit 8 to the AND gate 9B is "L", the clock to the circuit block 4B is cut off (supply is stopped), and the AND gate 9A. When the signal to (2) is "H", it becomes conductive, and the clock from the oscillation circuit 10 is supplied to the circuit block 4A. Since the other modes have similar operations, description thereof will be omitted.

This is useful when the flip-flop inside the IC is of the so-called static type. Since the clock supply to the circuit blocks not used according to the operation mode is cut off, the operation is stopped, the amount of current is reduced, and the power consumption is suppressed.

By the way, when a so-called dynamic type flip-flop is used in the IC, the configuration of the third embodiment cannot be used, and the fourth embodiment as shown in FIG. It is preferable to use the example configuration. That is, in the fourth embodiment shown in FIG.
The signals from the changeover switches 1 and 2 are sent to the clock frequency control logic circuit 12, and one output signal from the clock frequency control logic circuit 12 is sent to the selector 13A for selecting the clock to be supplied to the circuit block 4A. , The other output signal from the logic circuit 12 is sent to the selector 13B for selecting a clock for the circuit block 4B. These selectors 1
3A and 13B, a clock signal of the first frequency from the oscillation circuit 10 for clock generation using the crystal oscillator 11 and a clock signal of the second frequency obtained by dividing the clock signal by the frequency dividing circuit 14. And both are supplied respectively. The output signal from the selector 13A is the circuit block 4A.
Of the selector 13B, and the output signal from the selector 13B is sent to the clock input terminal of the circuit block 4B. Here, while the clock signal of the first frequency from the oscillation circuit 10 is a signal for performing a normal operation, the clock signal of the second frequency divided by the frequency dividing circuit 14 is higher than usual. The signal has a low frequency and is of a frequency that prevents a large current from flowing through the dynamic flip-flop as described later.

As a concrete example of the clock frequency control logic circuit 12 in this case, the output signal from the changeover switch 1 is sent to the selector 13B as it is, and the output signal from the changeover switch 2 is sent to the selector 13A. Well, selectors 13A and 13B for this
In both cases, when the selection control signal is "H", the clock signal of the first frequency from the oscillation circuit 10 is selected, and when the control signal is "L", the second frequency from the frequency dividing circuit 14 is selected.
What selects the clock signal of the frequency of is used. Here, for example, in the first operation mode of the state "01", since the output of the changeover switch 1 is "L" and the output of the changeover switch 2 is "H", the clock frequency control logic circuit 12 transfers to the selector 13B. Becomes "L" and the clock signal of the second frequency from the frequency dividing circuit 14 is selected and supplied to the circuit block 4B, whereas the control signal to the selector 13A is "H".
Then, the clock from the oscillation circuit 10 is supplied to the circuit block 4A. Since the other modes have similar operations, description thereof will be omitted.

Here, the operating current in the case of using a so-called CMOS IC and the operating principle of the dynamic flip-flop will be described with reference to FIGS. First, FIG. 5 shows a schematic configuration of a main part of a so-called CMOS inverter, in which an input terminal 21 is a gate of a P-channel MOS transistor 22 and an N-channel M.
It is connected to the gate of the OS transistor 23. The source of the P-channel MOS transistor 22 is connected to the Vdd power supply terminal, the drain is connected to the drain of the N-channel MOS transistor 23 and is connected to the output terminal 24, and the source of the N-channel MOS transistor 23 is G.
It is connected to the nd (ground) terminal. P channel MOS
The transistor 22 is turned on when the gate becomes "L" (low impedance between the drain and the source), and the N-channel MOS transistor 23 is turned on when the gate is "H".

When the input of the input terminal 21 is "H", the N-channel MOS transistor 23 is turned on and the above-mentioned Gnd
While the (ground) level signal "L" is taken out from the output terminal 24, when the input is "L", the P channel MOS transistor 22 is turned on and the Vdd power supply level signal "H" is output. . Input is from "H" to "L"
There is a moment when both the P-channel MOS transistor 22 and the N-channel MOS transistor 23 are turned on to some extent in the middle of the change when changing from "L" to "H". At this time, the Vdd power supply terminal to the Gnd (ground) terminal A relatively large current flows through. This is the reason why the current consumption can be reduced as the 1/0 state change inside the IC is reduced.

Next, in the case of a dynamic flip-flop, for example, as shown in FIG.
The voltage is held by the capacitance (capacitor or stray capacitance) 36. That is, in FIG. 6, the input terminal 31
Is a P-channel MOS transistor 34 and an N-channel MOS transistor whose source and drain are connected in parallel with each other.
It is connected to one connection point with the transistor 35, and the other connection point a is connected to the capacitor 36. P channel M
An inverted clock signal CK from the terminal 32 is applied to the gate of the OS transistor 34, and a clock signal C from the terminal 33 is applied to the gate of the N-channel MOS transistor 35.
K is supplied respectively. The connection point a is connected to the gate of the P-channel MOS transistor 38 and the gate of the N-channel MOS transistor 39.
The source of the P-channel MOS transistor 38 is connected to the Vdd power supply terminal, the drain is connected to the drain of the N-channel MOS transistor 39 and is connected to the output terminal 37, and the source of the N-channel MOS transistor 39 is connected to the Gnd (ground) terminal. Has been done.

In the configuration of FIG. 6, the clock signal C
When K is "H" ( CK is "L"), both the P-channel MOS transistor 34 and the N-channel MOS transistor 35 are turned on, and the input terminal 31 is connected to the point a.
Then, when the clock signal CK becomes "L", the connection between the input terminal 31 and the point a is broken, and the voltage at the point a is held regardless of the input. This is because the point a has a high impedance, and the voltage is maintained by the charge being held in the capacitor 36 that is visible at the point a. However, even though it has high impedance,
The electric charge stored in the small capacitance 36 will be released soon,
The point a is settled at an intermediate potential between the Vdd power supply voltage and Gnd (ground). At this time, similarly to the description of FIG. 5 described above, the output side inverter (transistor 3) at the point a is
8, 39), a relatively large current flows from the Vdd power supply terminal to the Gnd (ground) terminal. In order to prevent this, it is necessary to set the clock CK to "H" again to give the input level to the point a before entering such a state.

7A to 7D are waveform charts for explaining the above-described operation. FIG. 7A shows the clock signal CK, FIG. 7B shows the input signal of the input terminal 31, and FIG. (C)
Shows the voltage (level) at the point a, and (D) shows the output signal of the output terminal 37. In FIG. 7, since the clock signal (A) is "H" at the time t ₁ , if the input (B) changes from "H" to "L", the voltage (level) (C) at the point a. Also changes from "H" to "L", and the inverter output (D) changes from "L" to "H". When the clock signal (A) becomes “L” at time t ₂ ,
When the electric charge stored in the capacitor 36 is gradually discharged and the voltage (C) at the point a approaches the intermediate potential between the Vdd power supply voltage and Gnd (ground), and becomes the intermediate potential at time t ₃ , for example. , The inverter output (D) becomes indefinite. Since this will flow a large current time, even at a time prior to time t ₃ the frequency of the signal as a clock signal CK "H" of the (A) if Shiteyare to obtain from the divider 14 Good.

Therefore, in the fourth embodiment of the present invention shown in FIG. 4, the clock signal of the original frequency (first frequency) during normal operation is supplied to the internal node (point a) of the dynamic flip-flop. It is sufficient to divide the voltage of 2 to a frequency as low as possible within the range where the voltage does not reach the intermediate potential (the second frequency), and supply the clock signal of this low frequency to the circuit blocks not used depending on the operation mode.

The present invention is not limited to the above embodiment, and for example, any two or more of the above first to fourth embodiments may be used in combination. However, it is particularly preferable to use the first embodiment and the fourth embodiment in combination. In addition, a digital I provided with three or more circuit blocks
Of course, the present invention can be applied to C.

[0031]

As is apparent from the above description, according to the digital IC device of the present invention, the inside is divided into a plurality of functional blocks, and the first block is used in a predetermined operation mode. In a digital IC device having a second block that is not used and a second block that is not used, a flip-flop is cleared, an input signal is fixed, a clock is stopped or a low frequency is set for the second block that is not used in a predetermined operation mode. By switching or switching, the amount of current flowing through the second block is reduced and power consumption can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a main part of a first embodiment of a digital IC device according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a main part of a first embodiment of a digital IC device according to the present invention. It is a waveform diagram for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing a schematic configuration of a main part of a first embodiment of a digital IC device according to the present invention.

FIG. 4 is a block diagram showing a schematic configuration of a main part of a first embodiment of a digital IC device according to the present invention.

FIG. 5 is a circuit diagram showing a main configuration of a CMOS inverter.

FIG. 6 is a circuit diagram showing a main configuration of a dynamic flip-flop.

7 is a waveform chart for explaining the operation of FIG.

[Explanation of symbols]

1,2 ..... switch 3 ----- clear control logic 4A, 4B ..... circuit block 5 ----- input enable control logic _{6A 1 ~6A n, 6B 1 ~6B} m , 9A, 9B ...
AND gate 7A _{1 to} 7A _n , 7B _{1 to} 7B _m ··· signal input terminal 8 · · clock enable control logic 10 · · clock oscillator circuit 11 · · crystal oscillator 12 ... Clock frequency control logic 13A, 13B ... Selector 14 ... Dividing circuit

Claims (5)

[Claims] 1. A digital IC device having an inside divided into a plurality of functional blocks and having a first block used in a predetermined operation mode and a second block not used, in the predetermined operation mode. A digital IC device, wherein a clear signal is supplied to a clear terminal of a flip-flop of the second block. 2. A digital IC device having an inside divided into a plurality of functional blocks and having a first block used in a predetermined operation mode and a second block not used, in the predetermined operation mode. A digital IC device characterized in that all input signals to the second block are fixed. 3. A digital IC device having an inside divided into a plurality of functional blocks and having a first block used in a predetermined operation mode and a second block not used, in the predetermined operation mode. A digital IC device characterized in that the clock to the flip-flop of the second block is stopped. 4. A digital IC device having an inside divided into a plurality of functional blocks and having a first block used in a predetermined operation mode and a second block not used, in the predetermined operation mode. A digital IC device, characterized in that a clock for a dynamic flip-flop of the second block is changed to a clock having a frequency lower than usual and is supplied. 5. A digital IC device having an inside divided into a plurality of functional blocks and having a first block used in a predetermined operation mode and a second block not used, in the predetermined operation mode. A digital IC device characterized in that a clear signal is supplied to a clear terminal of a flip-flop of the second block and a clock having a frequency lower than usual is supplied to a clock input terminal.