JPH06112150A - Method for forming wiring in connecting hole - Google Patents
Method for forming wiring in connecting holeInfo
- Publication number
- JPH06112150A JPH06112150A JP26126492A JP26126492A JPH06112150A JP H06112150 A JPH06112150 A JP H06112150A JP 26126492 A JP26126492 A JP 26126492A JP 26126492 A JP26126492 A JP 26126492A JP H06112150 A JPH06112150 A JP H06112150A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- connection hole
- forming
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 238000009832 plasma treatment Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N tin hydride Chemical compound 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[Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005755 formation reaction Methods 0.000 description 7
- 238000010899 nucleation Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound 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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は配線形成方法に係り、特
に高集積半導体装置の多層配線形成等において、微細化
された接続孔にメタルプラグを形成する方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method and, more particularly, to a method for forming a metal plug in a miniaturized connecting hole in forming a multi-layer wiring of a highly integrated semiconductor device.
【０００２】[0002]
【従来の技術】次世代以降の超々ＬＳＩ等の半導体集積
回路において、微細化、高集積化に伴い、多層配線の層
間を接続するビアホール（以下Ｖ／Ｈと記す）や、半導
体基板と配線とを接続するコンタクトホール（以下Ｃ／
Ｈと記す）等の接続孔の開口径が例えば０．３５μｍと
いうようにますます微細になってきている。従って、従
来Ａｌのバイアススパッタ法ではステップカバレージの
点から接続孔内に信頼性よく配線を形成することが不可
能になってきている。そこで、ステップカバレージを改
善する方法として、メタルプラグ技術が実用化されつつ
ある。この技術は、上述のＶ／ＨあるいはＣ／Ｈ等の接
続孔内に選択的にメタルを埋め込む方法である。このメ
タルプラグ技術では、接続孔のアスペクト比が大きくな
るに従いプラグ自体の抵抗も問題となるために、抵抗の
低い例えばタングステン（以下Ｗ）プラグが注目されて
いる。このＷプラグの形成においても、選択Ｗ ＣＶＤ
法とブランケットタングステン（以下ＢＬＫ−Ｗ）ＣＶ
Ｄ法の２つがあるが、プロセスの安定性と、深さの異な
る接続孔へのプラグ形成の面からＢＬＫ−Ｗが有利であ
り注目されている。2. Description of the Related Art In semiconductor integrated circuits such as ultra-high-speed LSIs in the next generation and later, via miniaturization and higher integration, via holes (hereinafter referred to as V / H) connecting layers of multi-layer wiring, semiconductor substrate and wiring, Contact hole (hereinafter C /
The opening diameter of connection holes such as H) is becoming finer, for example, 0.35 μm. Therefore, it has become impossible to form a wiring in the contact hole with high reliability by the conventional Al bias sputtering method from the viewpoint of step coverage. Therefore, metal plug technology is being put to practical use as a method for improving step coverage. This technique is a method of selectively burying metal in the above-mentioned V / H or C / H connection hole. In this metal plug technology, the resistance of the plug itself becomes a problem as the aspect ratio of the connection hole increases, and therefore, for example, a tungsten (hereinafter W) plug having a low resistance is drawing attention. Also in the formation of this W plug, selective W CVD is performed.
Method and Blanket Tungsten (BLK-W) CV
There are two methods, D method, but BLK-W is attracting attention because it is advantageous in terms of process stability and formation of plugs in connection holes having different depths.
【０００３】図５は上記メタル技術を用いて配線接続
（メタルプラグ形成）を行うようにした従来の方法を説
明するための工程断面図を示す。すなわち、従来のメタ
ルプラグ形成は、まず図５（ａ）に示すように、下層配
線例えばシリコン基板１に拡散層による下層配線２を形
成した後、上面にＳｉＯ2などの絶縁膜３を形成し、こ
の絶縁膜３にコンタクト用の接続孔４を形成した後、接
続孔４内を含むように絶縁膜３の上面全面に例えばＴｉ
／ＴｉＮ膜による密着層５を形成する。ここで、Ｔｉ／
ＴｉＮを密着層に用いるのは、コンタクト抵抗を低減さ
せるためである。FIG. 5 is a process sectional view for explaining a conventional method in which wiring connection (metal plug formation) is performed by using the above metal technique. That is, in the conventional metal plug formation, as shown in FIG. 5A, first, a lower layer wiring, for example, a lower layer wiring 2 made of a diffusion layer is formed on a silicon substrate 1, and then an insulating film 3 such as SiO 2 is formed on the upper surface. After forming the contact connection hole 4 in the insulating film 3, for example, Ti is formed on the entire upper surface of the insulating film 3 so as to include the inside of the connection hole 4.
/ Adhesion layer 5 of TiN film is formed. Where Ti /
The reason why TiN is used for the adhesion layer is to reduce the contact resistance.
【０００４】次に、図５（ｂ）に示すように接続孔４内
を含む全面に高融点金属、例えばＢＬＫ−Ｗ層６をＣＶ
Ｄ法によって被着形成する。Next, as shown in FIG. 5B, a refractory metal, for example, a BLK-W layer 6 is CVed on the entire surface including the inside of the connection hole 4.
Adhesion is formed by the D method.
【０００５】次に、図５（ｃ）に示すように、ＣＶＤ法
により被着したＢＬＫ−Ｗ層６をエッチバックして接続
孔４内にのみＷを残すようにして、メタルプラグ６ａを
形成する。その後、メタルプラグ６ａに接続する上層配
線７を形成する。なお、拡散層による下層配線２の表面
には耐熱層であるＳＩＴＯＸ（シリサイデーション・ス
ルー・オキサイド）法によるＴｉＳｉ2膜８を形成する
こともできる。Next, as shown in FIG. 5 (c), the BLK-W layer 6 deposited by the CVD method is etched back to leave W only in the connection holes 4 to form a metal plug 6a. To do. After that, the upper layer wiring 7 connected to the metal plug 6a is formed. It is also possible to form a TiSi 2 film 8 by the SITOX (Silicidation Through Oxide) method, which is a heat resistant layer, on the surface of the lower wiring 2 made of the diffusion layer.
【０００６】[0006]
【発明が解決しようとする課題】上述したようなＢＬＫ
−Ｗを用いたメタルプラグの形成は、接続孔内配線形成
の有望な技術ではあるが、実用にあたっては、種々の問
題がある。その一つの問題として、被着されたＷのグレ
インが大きいことがある。この理由は密着層としてのＴ
ｉ／ＴｉＯＮ上にＷの核が形成しにくいためであり、核
発生密度が低いため、グレインが大きくなり、図６に示
すようにＷ金属層の表面のモフォロジーが大きくなった
り、シームと呼ばれる潜在的な空隙部１０ができてしま
うという問題がある。前者は、Ｗを配線として残す場合
にフォトリソグラフィーのアライメント不良や、絶縁膜
の形成時にそのカバレージが劣化するという問題を引き
起こす。また、後者は、後でエッチバックして、Ｗを接
続孔内に選択的に残す場合、シームの拡大、ひいては上
層配線のカバレージの劣化という問題を引き起こす。そ
のため、こういった問題のない、メタルプラグ形成方法
が望まれていた。BLK as described above
The formation of a metal plug using -W is a promising technique for forming wiring in a connection hole, but there are various problems in practical use. One of the problems is that the deposited W has a large grain. The reason for this is that T as an adhesion layer
This is because it is difficult for W nuclei to form on i / TiON, and the nucleation density is low, so that the grains become large and the morphology of the surface of the W metal layer becomes large as shown in FIG. There is a problem that a general void portion 10 is formed. The former causes problems such as misalignment of photolithography when W is left as a wiring and deterioration of its coverage when an insulating film is formed. In the latter case, when W is selectively etched back and W is selectively left in the connection hole, the seam expands, and the coverage of the upper layer wiring deteriorates. Therefore, a metal plug forming method that does not have such problems has been desired.
【０００７】そこで、本発明は多層にわたり、電気的接
続をとるために微細化された接続孔に良好にメタルプラ
グ配線を形成することを目的とする。Therefore, an object of the present invention is to satisfactorily form a metal plug wiring in a finely-divided connection hole for electrical connection over a number of layers.
【０００８】[0008]
【課題を解決するための手段】上記課題は本発明によれ
ば、下層配線と上層配線とを接続孔を介して電気的に接
続するために該接続孔に導体層を形成する接続孔への配
線形成方法において、前記下層配線表面あるいは該下層
配線表面に形成された導体薄層表面にガスプラズマ処理
を施すことを特徴とする接続孔への配線形成方法によっ
て解決される。SUMMARY OF THE INVENTION According to the present invention, the above object is to provide a connection hole in which a conductor layer is formed in the connection hole for electrically connecting the lower layer wiring and the upper layer wiring through the connection hole. In the wiring forming method, there is provided a wiring forming method for a connection hole, which comprises subjecting the surface of the lower layer wiring or the surface of a thin conductor layer formed on the lower layer wiring surface to a gas plasma treatment.
【０００９】[0009]
【作用】本発明によれば、下層配線１２と上層配線１９
とをコンタクトホール等の接続孔１４を介して電気的に
接続するために、予め下層配線表面あるいはその表面に
形成された金属を含有する薄層表面にガスプラズマ処理
を施しているため、該下層配線表面あるいは薄層表面が
活性となり、金属核形成が発生し易くなる。According to the present invention, the lower layer wiring 12 and the upper layer wiring 19 are provided.
In order to electrically connect with the lower layer wiring through a connection hole 14 such as a contact hole, the lower layer wiring surface or the metal-containing thin layer surface formed on the surface is previously subjected to gas plasma treatment. The surface of the wiring or the surface of the thin layer is activated and metal nucleation is likely to occur.
【００１０】本発明では、ガスプラズマ処理として還元
性ガスを用いることが金属核形成をより促進させる上で
好ましい。In the present invention, it is preferable to use a reducing gas as the gas plasma treatment in order to promote the formation of metal nuclei.
【００１１】[0011]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図１〜図２は本発明の第１実施例を説明するため
の工程断面図である。Embodiments of the present invention will be described below with reference to the drawings. 1 to 2 are process cross-sectional views for explaining a first embodiment of the present invention.
【００１２】本発明に係るタングステンプラグ配線形成
の第１実施例は、まず図１（ａ）に示すように、下層配
線、例えばシリコン基板１１の面上に拡散層による下層
配線１２を形成する。この場合、拡散層表面に耐熱層で
あるＳＩＴＯＸ法によるＴｉＳｉ2膜１８を形成してお
く。またシリコン基板１１上にＳｉＯ2等の絶縁膜１３
を膜厚５００ｎｍにＣＶＤ法により形成し、次に絶縁膜
１３上にレジスト膜を形成した後、レジスト膜をパター
ニングしてレジストマスク１７を形成し、このレジスト
マスク１７を介してドライエッチングによって接続孔１
４を形成する（図１（ｂ））。In the first embodiment of forming a tungsten plug wiring according to the present invention, first, as shown in FIG. 1A, a lower layer wiring, for example, a lower layer wiring 12 by a diffusion layer is formed on the surface of a silicon substrate 11. In this case, a TiSi 2 film 18, which is a heat-resistant layer, is formed on the surface of the diffusion layer by the SITOX method. In addition, an insulating film 13 such as SiO 2 is formed on the silicon substrate 11.
Is formed to a film thickness of 500 nm by a CVD method, and then a resist film is formed on the insulating film 13, and then the resist film is patterned to form a resist mask 17, and a contact hole is formed through the resist mask 17 by dry etching. 1
4 is formed (FIG. 1 (b)).
【００１３】次に図１（ｃ）に示すように、レジストマ
スク１７を除去した後、接続孔１４内を含む絶縁膜１３
上に、例えばＴｉ／ＴｉＮ等の密着層１５をスパッタ法
等により被着形成する。スパッタ条件としては、通常条
件、すなわちＴｉの形成にはＴｉターゲットをＡｒガス
でスパッタし、一方ＴｉＮの形成は、Ｔｉターゲットで
ＡｒガスとＮ2ガスで形成する。Next, as shown in FIG. 1C, after removing the resist mask 17, the insulating film 13 including the inside of the connection hole 14 is removed.
An adhesion layer 15 of, for example, Ti / TiN is deposited and formed thereon by a sputtering method or the like. The sputtering conditions are normal conditions, that is, a Ti target is sputtered with Ar gas for forming Ti, while TiN is formed with Ar gas and N 2 gas for Ti target.
【００１４】次に、通常のプラズマ処理可能な装置で ガ ス ：ＮＦ3／Ｈ2＝１０／１０ＳＣＣＭ 圧 力 ：４０Ｐａ ＲＦパワー密度：０．５Ｗ／ｃｍ2 の条件でプラズマ照射等の処理を行った。この時、一部
のＴｉＮがＴｉ１５ａに還元された（図２（ａ））。Next, plasma irradiation or the like is performed under the conditions of gas: NF 3 / H 2 = 10/10 SCCM pressure force: 40 Pa RF power density: 0.5 W / cm 2 with an ordinary plasma processable apparatus. It was At this time, a part of TiN was reduced to Ti15a (FIG. 2 (a)).
【００１５】次に、図２（ｂ）に示すように、高融点金
属であるＢＬＫ−Ｗ層１６をＣＶＤ法によって形成す
る。このＣＶＤ条件は、例えば １ｓｔ Ｓｔｅｐ ＷＦ5／ＳｉＨ4＝２５／１０ＳＣＣＭ，１．０７×１０4Ｐａ（８０Ｔｏｒｒ） ，４７５℃ ２ｎｄ Ｓｔｅｐ ＷＦ5／Ｈ2＝５０／３６０ＳＣＣＭ，１．０７×１０4Ｐａ（８０Ｔｏｒｒ）， ４７５℃ で行うことができる。（ここで１ｓｔ Ｓｔｅｐは所謂
核形成プロセスである。）この時、前述のような作用で
グレインの小さいＷ膜が形成できた。また同じく、核発
生がし易くなったため、１ｓｔ Ｓｔｅｐを省略するこ
とができたり、その時間を短くすることもできた。Next, as shown in FIG. 2B, a BLK-W layer 16 which is a refractory metal is formed by the CVD method. The CVD conditions are, for example, 1st Step WF 5 / SiH 4 = 25/10 SCCM, 1.07 × 10 4 Pa (80 Torr), 475 ° C. 2nd Step WF 5 / H 2 = 50/360 SCCM, 1.07 × 10 4 Pa. (80 Torr), 475 ° C. (Here, the 1st Step is a so-called nucleation process.) At this time, the W film having a small grain could be formed by the above-described action. Similarly, since nucleation is facilitated, the 1st Step can be omitted or the time can be shortened.
【００１６】次に図２（ｃ）に示すように、ＢＬＫ−Ｗ
層１６をエッチバックする。これは、ＲＩＥ（反応性イ
オンエッチング）によって行うことができる。条件とし
ては、Ｇａｓ：ＳＦ6＝３０ＳＣＣＭ，圧力＝６．６７
Ｐａ，パワー＝０．０８Ｗ／ｃｍ2に設定して行うこと
ができる。この時、図２（ｃ）で示すように一部還元さ
れた密着層としてのＴｉ１５ａが露出した位置でエッチ
バックをとめることが望ましい。この時、グレーンサイ
ズが小さく、シームの継ぎ目が細かいため、シームがエ
ッチバックによって増大することがなく、良好なＷから
なるメタルプラグ１６ａを得ることができた。本実施例
では、この後、通常工程により上層配線１９を形成して
下層配線１２との接続がメタルプラグ１６ａで良好に実
施された。Next, as shown in FIG. 2C, BLK-W
Etch back layer 16. This can be done by RIE (Reactive Ion Etching). The conditions are Gas: SF 6 = 30 SCCM, pressure = 6.67.
It can be performed by setting Pa and power = 0.08 W / cm 2 . At this time, as shown in FIG. 2C, it is desirable to stop the etch back at the position where the partially reduced Ti 15a as the adhesion layer is exposed. At this time, since the grain size was small and the seam joint was fine, the seam did not increase due to the etch back, and the metal plug 16a made of good W could be obtained. In the present embodiment, thereafter, the upper layer wiring 19 was formed by the normal process, and the connection with the lower layer wiring 12 was satisfactorily performed by the metal plug 16a.
【００１７】次に図３〜図４は、本発明の第２実施例を
説明するための工程断面図である。本発明に係るプラグ
イン配線形成の第２実施例でもＳＩＴＯＸ法によるＴｉ
Ｓｉ 2膜２８までの形成は、第１実施例の図１（ａ）〜
図１（ｂ）と同様であり、その後、シリコン基板２１上
にＣＶＤ法によりＳｉＯ2等の絶縁膜２３を膜厚５００
ｎｍに形成し、その上に上層配線であるｎ+ｐｏｌｙ−
Ｓｉ２９を膜厚２００ｎｍに形成し、更にその上にＳｉ
Ｏ2等の第２の絶縁膜２７を膜厚５００ｎｍに形成す
る。その後、通常のリソグラフィー技術とドライエッチ
ングを用いて、図３（ａ）に示すように、接続孔２４を
形成する。Next, FIGS. 3 to 4 show a second embodiment of the present invention.
It is a process sectional view for explaining. Plug according to the present invention
Also in the second embodiment for forming the in-wiring, Ti formed by the SITOX method is used.
Si 2The formation up to the film 28 is performed according to the first embodiment shown in FIG.
Same as FIG. 1B, and then on the silicon substrate 21.
SiO by CVD method2The insulating film 23 such as
nm, and the upper layer wiring n+poly-
Si29 is formed to a film thickness of 200 nm, and Si is further formed thereon.
O2Forming a second insulating film 27 having a thickness of 500 nm.
It After that, normal lithography technology and dry etching
The connecting hole 24 as shown in FIG.
Form.
【００１８】次に図３（ｂ）に示すように、接続孔２４
内を含む絶縁膜２３に例えばＴｉ／ＴｉＮ等の密着層２
５をスパッタ法等で被着形成する。スパッタ条件として
は、通常条件、すなわちＴｉの形成にはＴｉターゲット
をＡｒガスでスパッタし、ＴｉＮの形成は、Ｔｉターゲ
ットでＡｒガスとＮ2ガスで形成する。Next, as shown in FIG. 3B, the connection hole 24
The adhesion layer 2 of, for example, Ti / TiN is formed on the insulating film 23 including the inside.
5 is deposited by sputtering or the like. The sputtering conditions are normal conditions, that is, a Ti target is sputtered with Ar gas for forming Ti, and TiN is formed with Ar gas and N 2 gas for Ti target.
【００１９】次に、通常のプラズマ処理可能な装置で、 ガ ス ：ＮＦ3／Ｈ2＝１０／１０ＳＣＣＭ 圧 力 ：４０Ｐａ ＲＦパワー密度：０．５Ｗ／ｃｍ2 の条件でプラズマ処理を行った。この時、一部のＴｉＮ
がＴｉ２５ａに還元された（図３（ｃ））。Next, plasma processing was carried out in the usual plasma processing apparatus under the conditions of gas: NF 3 / H 2 = 10/10 SCCM pressure: 40 Pa RF power density: 0.5 W / cm 2 . At this time, some TiN
Was reduced to Ti25a (FIG. 3 (c)).
【００２０】次に図４（ａ）に示すように、高融点金属
である例えばＢＬＫ−Ｗ層２６をＣＶＤ法によって形成
する。このＣＶＤ条件は、例えば １ｓｔ Ｓｔｅｐ ＷＦ5／ＳｉＨ4＝２５／１０ＳＣＣＭ，１．０７×１０4Ｐａ（８０Ｔｏｒｒ） ，４７５℃ ２ｎｄ Ｓｔｅｐ ＷＦ5／Ｈ2＝６０／３６０ＳＣＣＭ，１．０７×１０4Ｐａ（８０Ｔｏｒｒ）， ４７５℃ で行うことができる（ここで１ｓｔ Ｓｔｅｐはいわゆ
る核形成プロセスである）。この時前述したような作用
により、グレインの小さいＷ膜が形成できた。また同様
に核発生がし易くなったため、１ｓｔ Ｓｔｅｐを省略
することができ、処理時間の短縮に寄与する。Next, as shown in FIG. 4A, a refractory metal such as a BLK-W layer 26 is formed by the CVD method. The CVD conditions are, for example, 1st Step WF 5 / SiH 4 = 25/10 SCCM, 1.07 × 10 4 Pa (80 Torr), 475 ° C. 2nd Step WF 5 / H 2 = 60/360 SCCM, 1.07 × 10 4 Pa. (80 Torr), 475 ° C. (1st Step is a so-called nucleation process). At this time, the W film having a small grain could be formed by the above-described action. Similarly, since nucleation is facilitated, the 1st Step can be omitted, which contributes to shortening the processing time.
【００２１】次に図４（ｂ）に示すように、ＢＬＫ−Ｗ
層２６をエッチバックする。このエッチバックは、第１
実施例と同様にＲＩＥによって行う。このＲＩＥ条件
は、Ｇａｓ：ＳＦ6＝３０ＳＣＣＭ，圧力＝６．６７Ｐ
ａ，パワー＝０．０８Ｗ／ｃｍ2に設定した。このエッ
チバックでは、図４（ｂ）に示すように一部還元された
密着層としてのＴｉ２５ａが露出した状態でエッチバッ
クを止めることが好ましい。このようにして接続孔２４
にＷをプラグイン縦配線を実現することができた。この
工程でも、上記実施例と同一の理由により、シームがエ
ッチバックにより増大しなかった。Next, as shown in FIG. 4B, BLK-W
Etch back layer 26. This etch back is the first
RIE is performed as in the example. The RIE conditions are Gas: SF 6 = 30 SCCM, pressure = 6.67P.
a, power = 0.08 W / cm 2 . In this etch back, as shown in FIG. 4B, it is preferable to stop the etch back with the partially reduced Ti 25a as an adhesion layer exposed. In this way, the connection hole 24
It was possible to realize the vertical wiring of the W plug-in. Even in this step, the seam did not increase due to the etch back for the same reason as in the above-mentioned example.
【００２２】[0022]
【発明の効果】以上説明したように、本発明によれば下
層配線と接続孔のプラグ配線との接続部の密着層がプラ
ズマ処理により、活性金属となり核発生が容易になされ
るため、良好な接続孔配線を得、従って下層配線と上層
配線との接続がストレス緩和もなされて良好な多層配線
を得ることができる。As described above, according to the present invention, the adhesion layer at the connecting portion between the lower layer wiring and the plug wiring of the connection hole becomes an active metal by the plasma treatment to facilitate the generation of nuclei. The connection hole wiring is obtained, and therefore, the stress between the lower layer wiring and the upper layer wiring is relieved, and a good multilayer wiring can be obtained.
【図１】本発明に係るメタルプラグ配線形成方法の第１
実施例を示す工程断面図（Ｉ）である。FIG. 1 is a first method of forming a metal plug wiring according to the present invention.
It is process sectional drawing (I) which shows an Example.
【図２】本発明に係るメタルプラグ配線形成方法の第１
実施例を示す工程断面図（II）である。FIG. 2 is a first method of forming a metal plug wiring according to the present invention.
It is process sectional drawing (II) which shows an Example.
【図３】本発明に係るメタルプラグ配線形成方法の第２
実施例を示す工程断面図（Ｉ）である。FIG. 3 is a second method of forming a metal plug wiring according to the present invention.
It is process sectional drawing (I) which shows an Example.
【図４】本発明に係るメタルプラグ配線形成方法の第２
実施例を示す工程断面図（II）である。FIG. 4 is a second method of forming a metal plug wiring according to the present invention.
It is process sectional drawing (II) which shows an Example.
【図５】従来のメタルプラグ配線形成方法を説明するた
めの工程断面図である。FIG. 5 is a process cross-sectional view for explaining a conventional metal plug wiring forming method.
【図６】従来例の問題点を示す模式断面図である。FIG. 6 is a schematic cross-sectional view showing a problem of the conventional example.
１，１１，２１ シリコン基板 ２，１２，２２ 下層配線 ３，１３，２３ 絶縁膜 ４，１４，２４ 接続孔（開孔部） ５，１５，２５ 密着層 １５ａ，２５ａ 一部還元された密着層 ６，１６，２６ ブランケットタングステン（ＢＬＫ−
Ｗ） ６ａ，１６ａ，２６ａ メタルプラグ ７，１９ 上層配線 ８，１８，２８ ＴｉＳｉ2膜（ＳＩＴＯＸ法によるシ
リサイド層） １０ シーム １７ レジストマスク ２０ 第２の絶縁膜 ２９ 上層配線ｎ+ｐｏｌｙ−Ｓｉ層1,11,21 Silicon substrate 2,12,22 Lower layer wiring 3,13,23 Insulating film 4,14,24 Connection hole (opening) 5,15,25 Adhesion layer 15a, 25a Adhesion layer partially reduced 6,16,26 Blanket Tungsten (BLK-
W) 6a, 16a, 26a Metal plug 7, 19 Upper wiring 8, 18, 28 TiSi 2 film (silicide layer by SITO X method) 10 Seam 17 Resist mask 20 Second insulating film 29 Upper wiring n + poly-Si layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/90 Ａ 7514−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication H01L 21/90 A 7514-4M
Claims (4)
電気的に接続するために該接続孔に導体層を形成する接
続孔への配線形成方法において、 前記下層配線表面あるいは該下層配線表面に形成された
導体薄層表面にガスプラズマ処理を施すことを特徴とす
る接続孔への配線形成方法。1. A method of forming a wiring in a connection hole, wherein a conductor layer is formed in the connection hole for electrically connecting the lower layer wiring and the upper layer wiring through the connection hole. A method of forming a wiring in a connection hole, which comprises subjecting a surface of a thin conductor layer formed on the surface to a gas plasma treatment.
拡散層を含む層であり、該下層配線上に形成した接続孔
にメタルプラグを形成することを特徴とする請求項１記
載の接続孔への配線形成方法。2. The connection hole according to claim 1, wherein the lower layer wiring is a layer including a diffusion layer formed on a semiconductor substrate, and a metal plug is formed in the connection hole formed on the lower layer wiring. Forming method for the wiring.
配線との密着性を向上させるための密着層であることを
特徴とする請求項１記載の接続孔への配線形成方法。3. The wiring forming method for a connection hole according to claim 1, wherein the thin conductor layer is an adhesion layer for improving the adhesion between the upper layer wiring and the lower layer wiring.
いて行われることを特徴とする請求項１〜３のいずれか
１記載の接続孔への配線形成方法。4. The method of forming a wiring in a connection hole according to claim 1, wherein the gas plasma treatment is performed using a reducing gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26126492A JP3208608B2 (en) | 1992-09-30 | 1992-09-30 | Wiring formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26126492A JP3208608B2 (en) | 1992-09-30 | 1992-09-30 | Wiring formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06112150A true JPH06112150A (en) | 1994-04-22 |
| JP3208608B2 JP3208608B2 (en) | 2001-09-17 |
Family
ID=17359413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26126492A Expired - Fee Related JP3208608B2 (en) | 1992-09-30 | 1992-09-30 | Wiring formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3208608B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100413890B1 (en) * | 1995-03-02 | 2004-03-19 | 동경 엘렉트론 주식회사 | Manufacturing method and manufacturing apparatus of semiconductor device |
| DE19752637B4 (en) * | 1996-12-24 | 2005-12-29 | LG Semicon Co., Ltd., Cheongju | Method for producing a line arrangement of a semiconductor device |
-
1992
- 1992-09-30 JP JP26126492A patent/JP3208608B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100413890B1 (en) * | 1995-03-02 | 2004-03-19 | 동경 엘렉트론 주식회사 | Manufacturing method and manufacturing apparatus of semiconductor device |
| DE19752637B4 (en) * | 1996-12-24 | 2005-12-29 | LG Semicon Co., Ltd., Cheongju | Method for producing a line arrangement of a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3208608B2 (en) | 2001-09-17 |
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