JPH06104937A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce useless power consumption by providing a standby circuit receiving an output signal of a line receiver and outputting a standby signal to inactivate the line receiver and a line driver in the case of non-signal. CONSTITUTION:The semiconductor integrated circuit 1 is provided with a standby circuit 15 which receives a signal at an output terminal of a line receiver 13 and outputs a standby signal STBY. Furthermore, an operating state control circuit controlling power on/off by the signal STBY is added to a line receiver 13 and a line driver 14. When an INFO/frame detection circuit 17 detects INFO0, i.e., non-signal from an output signal of the receiver 13, the circuit 17 outputs an INFO0 signal 30 to the circuit 15. The circuit 15 outputs the signal STBY to the receiver 13 and the driver 14 to inactivate them through power interruption. Thus, useless power consumption when the transmission line has no signal is saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having a line driver and a line receiver.

[0002]

2. Description of the Related Art CCITT Recommendation I. In the basic interface defined by 430, the signal when communicating at the S point or the T point (described as the majestic or S point), which is the specified point, is an AMI (Alternate Mark Inve) signal.
region) code is used. In this AMI code, no signal on the line represents a binary "1", and a binary "0" represents a positive or negative pulse. A dedicated line driver and line receiver are required to transmit and receive such signals.

Conventionally, this type of semiconductor integrated circuit line
The driver and line receiver and the internal logic circuit are composed of blocks as shown in FIG. In FIG.
The integrated circuit 1 includes a line receiver 41 which receives a reception signal from the reception S bus 37 through a reception transformer 31, and
A DPLL (Digital Ph) that inputs the output signal
as Locked Loop) 16 and INFO /
The output signals of the frame detection circuit 17, the bit string conversion circuit 19, the state transition control circuit 18, the control circuit 20, and the bit string conversion circuit 19 are input and a transmission signal is output to the transmission SBus 38 via the transmission transformer 34. And a line driver 42.

Here, 2 is a general output terminal, 3 is a general input terminal, 4 is a transmission input terminal, 5 is a reception output terminal, 6 is a reset signal input terminal, 7 is a clock output terminal, and 8 is a master clock signal input. It is a terminal.

The LIN of the line receiver input terminal 9 is connected to one terminal of the coil 33 of the receiving transformer 31,
The REF of the line receiver reference terminal 10 is connected to the other terminal of the coil 33, and the coil 32 of the receiving transformer 31 has a receiving S having a point S which is a specified point on the transmission line.
It is connected to the bus 37.

Further, the line driver positive output terminal 11
Is connected to one terminal of the coil 35 of the transmission transformer 34, and LO of the line driver negative side output terminal 12 is connected to
The − is connected to one terminal of the coil 35, and the coil 36 of the transmission transformer 34 is connected to the transmission S bus 38 at the S point.

The circuit of the line receiver 41 is composed of the circuit shown in FIG. In FIG. 10, reference numerals 56 to 60 are resistors and 61 is an analog comparator. The threshold voltages of the analog comparator 61 having the line receiver positive side output terminal 52 are resistors 56, 57 and resistors 58, 59,
The voltage of 60 is set higher than that of the terminal 55. Similarly, the threshold voltage of the analog comparator 61 having the line receiver negative output terminal 53 is
7 and resistors 58, 59 and 60 to set the voltage lower than the voltage at the terminal 55. The analog comparator 61 is shown in FIG.
The differential amplifier of is used.

In FIG. 11, this differential amplifier is a P-type M
OS transistors 85, 87, 88, 89, 92 and N
Type MOS transistors 86, 90, 91, 93, inverters 94, 95, a power supply terminal 80, and a ground terminal 81.
A non-inverting (+) input terminal 82, an inverting (-) input terminal 83, and an analog comparator output terminal 84.

The line receiver 41 converts the AMI code received from the S bus into a binary value of "L" and "H". The line driver 42 converts the binary data into AMI code. Digital Phase Lock Loop (DPLL) 1
Reference numeral 6 extracts a clock from the AMI code string received from the S bus and supplies the clock internally or externally. INF
The O / frame detection circuit 17 identifies INFO0, INFO2, and INFO4 from the binary-converted data, and detects the framing bit of the frame. The state transition control circuit 18 determines one of the state values F2 to F8 based on the data converted to binary and the signal from the control circuit 20. The bit string conversion circuit 19 performs speed conversion between the binary converted data and the external interface. Control circuit 20
Sends an instruction to the bit string conversion circuit and the state transition control circuit.

CCITT I.D. If the integrated circuit 1 is for a terminal device (hereinafter referred to as TE) as defined by 430, the received signal at the point S is INFO0, INFO2, I.
NFO4, the transmission signal is INFO0, INFO1,
It is INFO3. INFO0 is no signal, INF
O1 and INFO2 are activation request frames, and INFO3 and I
NFO4 is a general data frame. Normally, when the TE is communicating with the network terminating device (hereinafter referred to as NT), INFO4 is used in the direction from NT to TE, and TE to NT.
Direction is transmitting INFO3. On the other hand, in the stopped state, no signal INFO0 is transmitted from the NT to the TE direction and from the TE to the NT direction.

The above S bus frame structure is shown in FIG.
The definition of the INFO signal is shown in FIG.

In FIG. 12, an S bus frame structure is shown. As framing bit F, DC balanced bit, D channel bit D, echo bit E, auxiliary frame bit FA, channel bit as 48 bits (for 250 μs). There are B1, B2, spare bits or S channel bits S, multi-framing bits M and the like.

In FIG. 13, the definition of the INFO signal is shown. The signal from the NT to the TE direction and the signal from the TE to N are shown.
Signal in the T direction, and each signal is shown.

[0014]

Conventionally, the above-described line driver, line receiver and internal logic circuit of the semiconductor integrated circuit are receiving INFO0 and INFO0.
Since it is in the operating state even while sending
It has a drawback of wasting power.

[0015]

The semiconductor integrated circuit according to the present invention is disclosed in CCITT Recommendation I.S. In a semiconductor integrated circuit that transmits and receives a transmission signal and a reception signal between an external transmission line having a defined point S of 430 and an internal logic circuit via a line driver and a line receiver, respectively. Select a single signal from the received signals,
A standby circuit for inputting and supplying a standby signal to the operation state control terminals of the line driver and the line receiver and the internal logic circuit is configured.

The standby circuit of the semiconductor integrated circuit according to the present invention uses the received signal as the first clock source, M (1, 2,
3, ...) stage asynchronous type binary counter, and sets the final stage output of M stage asynchronous type binary counter.
It is connected to the set terminal of the reset type flip-flop and uses the frame synchronization signal as the second clock source N (1, 2,
3, ...) Asynchronous binary counter with N stages, and sets the final stage output of N-stage asynchronous binary counter.
Connected to the reset terminal of the reset flip-flop,
The output of an OR gate that receives a plurality of state transition control signals is connected to the reset terminal of the M-stage asynchronous binary counter, and the state transition control signals are connected to the reset terminal of the N-stage asynchronous binary counter. It is configured by connecting the output of an OR and gate that receives the INFO detection signal as an input and outputting the output of the set / reset type flip-flop as a standby signal.

The line of the semiconductor integrated circuit of the present invention
The receiver circuit is composed of two analog comparators and a resistor network. The output of the first analog comparator is the line receiver positive side output terminal, and the output of the second analog comparator is the line receiver negative side output. The line receiver positive side output terminal is connected to the first clock source of the standby circuit, and the standby signal of the standby circuit is input to the control input terminal of the second analog comparator.

Alternatively, the line receiver circuit of the semiconductor integrated circuit of the present invention is composed of three analog comparators and a resistor network, and the output of the first analog comparator is used as the line receiver positive side output terminal. The output of the second analog comparator is used as the line receiver negative side output terminal, the output terminal of the third analog comparator is connected to the first clock source of the standby circuit, and the first analog comparator and the second analog are connected. It is configured by inputting the standby signal of the standby circuit to the control input terminal of the comparator.

[0019]

1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the standby circuit in FIG.

In FIG. 1, the line driver and line receiver and the internal logic circuit of this embodiment are shown.

The integrated circuit 1 includes a line receiver 13 for receiving a reception signal from a reception S bus 37 through a reception transformer 31, and a standby circuit 15 for inputting an output signal thereof.
, DPLL 16, and INFO / frame detection circuit 17
A bit string conversion circuit 19 and a state transition control circuit 18
The control circuit 20 and the line driver 14 which receives the output signal of the bit string conversion circuit 19 and outputs the transmission signal to the transmission SBus 38 via the transmission transformer 34.

Here, 2 is a general output terminal, 3 is a general input terminal, 4 is a transmission input terminal, 5 is a reception output terminal, 6 is a reset signal input terminal, 7 is a clock output terminal, and 8 is a master clock signal input. It is a terminal.

Signals 22 and 23 are line receiver output signals LI1 and LI2, signals 24 and 25 are line driver input signals LO1 and LO2, signal 26 is an INFO detection signal, signal 27 is a state transition control signal, and signal 28 is standby. Signal STBY and signal 29 are frame synchronization signals FSYN
C (8 kHz), signal 30 is an INFO0 detection signal.

LIN of the line receiver input terminal 9 is
Connect to one terminal of the coil 33 of the receiving transformer 31,
The REF of the line receiver reference terminal 10 is connected to the other terminal of the coil 33, and the coil 32 of the receiving transformer 31 is connected to the receiving S bus 37 having the S point which is the specified point on the transmission line.

The line driver positive side output terminal 11
LO + is connected to one terminal of the coil 35 of the transmission transformer 34, and LO− of the line driver negative side output terminal 12 is connected.
Is connected to the other terminal of the coil 35, and the transmission transformer 34
The coil 36 is connected to the transmission S bus 38 at the S point.

In FIG. 2, the standby circuit 15 is
Eight binary counters 121 to 128, a set / reset (SR type) flip-flop 129, an OR gate 130, an OR and gate 131, an S bus reception detection input terminal 110, and an FSYNC frame synchronization signal input terminal 111. And STBY standby signal output terminal 1
12 and F2 and F3 state transition control signal terminals 113 and 11
4 and F6, F7, F8 state transition control signal terminals 115,
116 and 117, and INFO0 detection signal input terminal 118
It has and.

The circuit of the line receiver 13 is composed of the circuit shown in FIG. In FIG. 3, 56 to 60 are resistors,
Reference numeral 61 is an analog comparator, and 62 is an analog comparator 2. The thread threshold voltage of the analog comparator 61 having the line receiver positive side output terminal 52 is
7 and the resistors 58, 59, 60 set the voltage higher than the voltage at the terminal 55. Similarly, the threshold voltage of the analog comparator 62 having the line receiver negative side output terminal 53 will be described as being lower than the voltage of the terminal 55 by the resistors 56, 57 and the resistors 58, 59, 60. The analog comparator 61 uses the differential amplifier shown in FIG. 11, and the analog comparator 62 uses the differential amplifier with a standby transistor shown in FIG.

In FIG. 4, the present differential amplifier is a P-type MO.
S transistors 85, 87, 88, 89, 92, 98
And N-type MOS transistors 86, 90, 91, 93,
99, inverters 94, 95 and 97, an STBY input terminal 96, a power supply terminal 80, a ground terminal 81, a non-inverting input terminal 82, an inverting input terminal 83, and an analog comparator output terminal 84.

STBY input terminal 9 of the analog comparator 62
When the level of 6 is set to "H", an N-type MOS that becomes a current source
The transistor 86 is turned off, and the P-type MOS transistor 9
8 turns on, and P-type MOS transistors 85, 87, 92
Turns off. Further, since the N-type MOS transistor is turned on, the input of the inverter 94 becomes "L" and the inverters 94 and 95 are stable. From the above, the current consumption of the analog comparator 62 becomes almost zero.

Next, the operation of the semiconductor integrated circuit of FIGS. 1 and 2 will be described with reference to the timing charts of FIGS.

1, FIG. 2, FIG. 5 (A), and (B), the LIN of the line receiver input terminal 9 is DC-connected to the line receiver reference terminal 10 via the coil 33 of the receiving transformer 31. Since it is connected to REF, the same DC voltage (approximately VDD / 2) as that of the terminal REF is applied. Therefore, the AMI code is applied with reference to the voltage of the terminal REF.

When the positive polarity pulse is "+0" and the negative polarity pulse is "-0" in binary "0", the line receiver positive side output terminal signal becomes "L" at the time of receiving INFO0, and I
When NFO2 is received, only the pulse of the "+0" signal becomes "H".

In FIG. 5A, the transition state is F3 (stop state, CCITT Recommendation I.4 immediately before INFO2 reception).
30 Table 6-2), the output of the OR gate 130 becomes "H", and the four-stage asynchronous binary counters 121 to 124 start counting after the start of INFO2 reception. The set / reset flip-flop is set at the 8th count in order to enter the operating state after 13 bits or more have passed from the F bit which is the period for detecting the code violation. That is, the standby signal STBY of the terminal 112 becomes "L" and the operation state is established.

Further, in FIG. 4 (B), INFO
2, or when INFO0 is suddenly received while receiving INFO4, the transition states are F6 (synchronous state) and F7.
Since it is (starting state) or F8 (out of synchronization), the output of the OR and gate 131 becomes "H", and the 4-stage asynchronous binary counters 125-128.
Start counting. The number of out-of-sync protection stages is required to guarantee three S bus frames, so the set / reset flip-flop is reset at the 8th count of the frame sync signal (8 KHz) FSYNC at the terminal 111. That is, the standby signal S of the terminal 112
TBY becomes "H", and it is in a non-operating state.

FIG. 6 is a block diagram showing a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 6, the integrated circuit 1 includes a reception transformer 3 for receiving a reception signal from the reception S bus 37.
1, a line receiver 41 for inputting the output signal, a standby circuit 15 for inputting the output signal thereof, and a DPLL 16
An INFO / frame detection circuit 17, a bit string conversion circuit 19, a state transition control circuit 18, and a control circuit 20.
And the line driver 14 which receives the output signal of the bit string conversion circuit 19 and outputs the transmission signal to the transmission SBus 38 via the transmission transistor 34.

Here, 2 is a general output terminal, 3 is a general input terminal, 4 is a transmission input terminal, 5 is a reception output terminal, 6 is a reset signal input terminal, 7 is a clock output terminal, and 8 is a master clock signal input terminal. Is.

Signals 22 and 23 are line receiver output signals LI1, LI2, 24, signal 25 is line driver input signals LO1 and LO2, signal 26 is INFO detection signal, signal 27 is state transition control signal, and signal 28 is standby. The signal STBY and the signal 29 are the frame synchronization signal (8 kHz).
z), the signal 30 is the INFO0 detection signal, and the signal 40 is the S bus reception detection signal.

LIN of the line receiver input terminal 9 is
Connect to one terminal of the coil 33 of the receiving transformer 31,
The REF of the line receiver reference terminal 10 is connected to the other terminal of the coil 33, and the coil 32 of the receiving transformer 31 is connected to the receiving S bus 37 having the S point which is the specified point on the transmission line.

The line driver positive output terminal 11
LO + is connected to one terminal of the coil 35 of the transmission transformer 34, and LO− of the line driver negative side output terminal 12 is connected.
Is connected to the other terminal of the coil 35, and the transmission transformer 34
The coil 36 is connected to the transmission S bus 38 at the S point.

The circuit of the line receiver 39 is composed of the circuit of FIG. In FIG. 7, 56 to 60 are resistors,
Reference numerals 62 and 64 are analog comparators, and 65 is a comparator.

The threshold voltage of the analog comparator 64 having the line receiver positive output terminal 52 is determined by the resistors 56, 57 and the resistors 58, 59, 60, and the terminal 5
Set higher than the voltage of 5. Similarly, the threshold voltages of the analog comparator 62 having the line receiver negative side output terminal 53 are resistor 56, 57 and resistor 58, 59,
The voltage is set lower than the voltage of the terminal 55 by 60 and. Although the analog comparator 65 has the same configuration as the analog comparators 62 and 64, it does not matter if the delay time is long. Therefore, the gm of the MOS transistor can be reduced and the power consumption can be minimized. The output 66 of the analog comparator 65 is connected to the terminal 110 of the standby circuit (FIG. 2). The operation timing is exactly the same as that of the first embodiment.

FIG. 8 is a characteristic diagram showing a comparison of power supply current values of transmission / reception signals of semiconductor integrated circuits according to the conventional example, the first embodiment, and the second embodiment. In FIG. 8, INFO3 / IN
When transmitting / receiving FO4, when transmitting / receiving INFO1 / INFO0, the power supply current value does not change, but INFO0 / I
When sending and receiving NFO0, it consumes about 5mA in the conventional example,
The first embodiment consumes about 1 mA, and the second embodiment consumes about 200 μA.

[0043]

As described above, according to the present invention, the INF
At the time of receiving O0, the line driver and the line receiver are brought into a non-operating state and their current consumptions are made substantially zero, so that there is an effect of reducing the power consumption of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a standby circuit of FIG.

FIG. 3 is a circuit diagram showing a line receiver circuit used in the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a comparator with a standby transistor used in the first embodiment of the present invention.

5A and 5B are timing charts of respective signals for explaining the operation of the standby circuit of the first exemplary embodiment of the present invention.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a line receiver circuit used in a second embodiment of the present invention.

FIG. 8 is a characteristic diagram showing comparison of power supply current values by transmitting / receiving signals of the first and second examples and the conventional example.

FIG. 9 is a block diagram of an example of a conventional semiconductor integrated circuit.

FIG. 10: Lines used in a conventional semiconductor integrated circuit
It is a circuit diagram which shows a receiver circuit.

FIG. 11 is a circuit diagram showing a comparator used in a conventional semiconductor integrated circuit.

FIG. 12 is a timing diagram showing an SBus frame structure.

FIG. 13 is a diagram showing the definition of an INFO signal.

[Explanation of symbols]

1 integrated circuit 2 general control output terminal 3 general control input terminal 4 transmission input terminal 5 reception output terminal 6 reset signal input terminal 7 clock output terminal 8 master clock signal input terminal 9 LIN line receiver input terminal 10 REF line receiver reference Terminal 11 LO + Line driver positive side output terminal 12 LO− Line driver negative side output terminal 13, 39, 41 Line receiver 14, 42 Line driver 15 Standby circuit 16 DPLL 17 INFO / frame detection circuit 18 State transition control circuit 19 bit string conversion circuit 20 control circuit 21 control signal 22 LI1 line receiver output signal 23 LI2 line receiver output signal 24 LO1 line driver input signal 25 LO2 line driver input signal 26 INFO Output signal 27 State transition control signal 28 STBY Standby signal 29 Frame synchronization signal (8 kHz) 30 INFO0 detection signal 31 Reception transformer 32 Reception transformer Primary side 33 Reception transformer Secondary side 34 Transmission transformer 35 Transmission transformer Primary side 36 Transmission transformer 2 Next side 37 Reception S bus 38 Transmission S bus 40 S bus Reception detection signal 50,80 Power supply terminal 51,81 Ground terminal 52 LI1 line receiver positive side output terminal 53 LI2 line receiver negative side output terminal 54 LIN line receiver input Terminal 55 REF Line Regiver Reference Terminal 56-60 Resistor 61, 62, 64 Analog Comparator 63 STBY Signal Input Terminal 65 Analog Comparator 3 66 S Bus Reception Detection Signal 82 Non-Inverted Input Terminal 83 Inverted Input Terminal 84 Analog Ratio Output terminal 85,87,88,89,92,98 P-type MOS transistor 86,90,91,93,99 N-type MOS transistor 94,95,97 Inverter 96 STBY input terminal 110 S bus reception detection input terminal 111 FSYNC Frame sync signal input terminal 112 STBY Standby signal output terminal 113 to 117 State transition control signal input terminal 118 INFO0 detection signal terminal 119, 120 Reset signal 121 to 128 Binary counter 129 Set reset flip flop 130 OR gate 131 OR OR And gate

Claims (4)

[Claims] 1. CCITT Recommendation I. A semiconductor integrated circuit, which transmits and receives a transmission signal and a reception signal between an external transmission line having a defined point S or T of 430 and an internal logic circuit via a line driver and a line receiver, respectively. A standby circuit for selecting and inputting a single signal from a plurality of received signals of the line receiver and supplying a standby signal to the operation state control terminals of the line driver and the line receiver and the internal logic circuit. And a semiconductor integrated circuit. 2. The standby circuit has M (= 1, 2, 3, ...) Asynchronous binary counters using the received signal as a first clock source, and the M stage asynchronous binary counters. · N (= 1, 2, 3, ...) Using the frame sync signal as the second clock source by connecting the final stage output of the counter to the set terminal of the set / reset flip-flop
A non-synchronous binary counter, and the final stage output of the N-stage asynchronous binary counter is
Connected to the reset terminal of the reset flip-flop,
A plurality of state transition controls of the reset terminals of the N-stage asynchronous binary counter are connected to the reset terminals of the M-stage asynchronous binary counters and the outputs of the OR gates to which a plurality of state transition control signals are input. 2. The semiconductor integrated circuit according to claim 1, wherein the output of the OR-and-gate which receives the signal and the INFO detection signal is connected, and the output of the set / reset flip-flop is output as a standby signal. 3. The line receiver circuit is composed of two analog comparators and a resistor network, and the output of the first analog comparator is a line receiver positive side output terminal.
The output of the analog comparator is used as a negative output terminal of the line receiver, the positive output terminal of the line receiver is connected to the first clock source of the standby circuit, and the standby input is provided to the control input terminal of the second analog comparator. The semiconductor integrated circuit according to claim 1, wherein a standby signal of the circuit is input. 4. The line receiver circuit is composed of three analog comparators and a resistor network, and the output of the first analog comparator serves as a line receiver positive-side output terminal.
The output of the analog comparator is used as the line receiver negative side output terminal, the output terminal of the third analog comparator is connected to the first clock source of the standby circuit, and the first analog comparator and the second analog are connected. 2. The semiconductor integrated circuit according to claim 1, wherein the standby signal of the standby circuit is input to the control input terminal of the comparator.