JPH06102535A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To improve the durability of a TFT by optimizing the pixel potential of an (n)th scan line when an (n-1)th scan line is displayed. CONSTITUTION:Pixel electrodes 14n and 14n-1 of liquid crystal cells 12(n, m) and 12(n-1, m) are connected to the intersections of gate bus lines 10n and 10n-1 and a data bus line 11 which are arrayed crossing each other through thin film transistors 13n and auxiliary capacitors CS are formed between parts of pixel electrodes 14n and 14n-1 and parts of gate bus lines 10n and 10n-1 which are one scan line before. This liquid crystal display device is provided with a clamping means 15n which clamps the potentials of the pixel electrodes 14n and 14n-1 to specific potentials in response to the potentials of the gate bus lines 10n and 10n-1 which are one scan line before.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, it relates to an active matrix type TFT liquid crystal display device. TFT (thin film transistor: thin film transi)
The liquid crystal display device using the stor element has good responsiveness and is capable of multi-gradation display, so it is used for displays of televisions and various information terminal devices.
Of the pixel electrode (specifically, the parasitic capacitance C _gs between the gate and source electrodes) and the liquid crystal capacitance C _LC (which is a variable capacitance) easily cause the level shift of the pixel electrode. _Since the value of _gs varies greatly due to errors in the lithography process and variations in film thickness, it is necessary to devise measures to absorb such variations and improve image quality.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional liquid crystal display device. 1 _n and 1 _n-1 are gate bus lines arranged in the order of scan lines (scan lines), and 2 is a data bus line. . Liquid crystal cells 3 _{(n, m)} 3 _{(n-1, m)} are provided at the respective intersections of the gate bus lines and the data bus lines arranged in a cross shape, and each liquid crystal cell is a thin film transistor. (TFT) 4 _n , 4 _n-1 and pixel electrodes 5 _n , 5 _n-1 are provided, and between the pixel electrode 5 _n and the gate bus line 1 _n-1 one scan line before (n-1). An auxiliary capacitance C _S (also called a storage capacitance) is formed.

It should be noted that the auxiliary capacitance C _S has a part of the pixel electrode 5 _n and 1 as shown in the plan layout of its main portion in FIG.
A part of the gate bus line 1 _n-1 before the scan line is overlapped, and a storage capacitor called a C _{S on-} gate system is formed in the overlapping part (hatched part). According to this system, a high aperture is formed. The rate can be secured.

In order to display the specific pixel of the n-th scan line in such a structure, first, the potential of the gate bus line 1 _n (gate potential) is raised to +10 several V and connected to the gate bus line 1 _n . When all the TFTs (typically 4 _n in the figure) are turned on, and then the potential of the data bus line (for example, 2) is set to a size according to the display data, the potential is turned on from the TFT 4 _n to the liquid crystal. Written to cell 3 _{(n, m)} . That is, the potential (pixel potential) of the pixel electrode 5 _n of the liquid crystal cell 3 _{(n, m)} which is a specific pixel
Becomes a size corresponding to the display data, the transmittance of the liquid crystal material interposed between the pixel electrode 5 _n and the common electrode (also referred to as the counter electrode or the common electrode) changes, and the gray scale corresponding to the inter-electrode voltage. Is displayed.

Here, the capacitance fluctuations of C _gs of the TFT 4 _n and the liquid crystal capacitance C _LC (not shown) which is a variable capacitance are absorbed by the auxiliary capacitance C _S having a relatively large capacitance, so that the image quality caused by the capacitance fluctuation is reduced. Deterioration is avoided.

[0006]

However, in such a conventional liquid crystal display device, an auxiliary device is provided between the pixel electrode and the gate bus line one scan line before (see reference numeral 1 _n-1 in FIG. 7). Since the capacitor C _S is formed, for example, when the potential of the gate bus line 1 _n-1 is raised to +10 number V, in other words, when the n-1 scan line is displayed, the gate bus line 1 n-1 is displayed. 1
_A change in the potential of _n-1 (gate potential) is transmitted to the pixel electrode 5 _n via the auxiliary capacitance C _S , the potential of the pixel electrode 5 _n (pixel potential) temporarily rises, and the gate bus line 1 _n and the pixel An excessive voltage is applied between the electrode 5 _n , that is, between the gate and the source of the TFT 4 _n , and as a result, the durability of the TFT 5 _n is impaired.

FIG. 9 is a diagram showing the time relationship between the potential of the gate bus line 1 _n (gate potential) and the pixel potential. The potential of the gate bus line 1 _n is raised to +10 several V in the vicinity of 33.45 ms, and the potential of this 33.4 is increased.
In the vicinity of 5 ms, the pixel potential also changes according to the display data. Here, the gate potential indicated by the broken line is the (n-1) th scan line, that is, the gate bus line 1 _n-1 immediately before the 1st scan line.
The pixel potential fluctuates in the rising direction in response to this potential change. In this case, the maximum value of the gate-source voltage of the TFT 5 _n is +10
It is given by the difference from the pixel potential of about 17V and is about 30V.
An excessive voltage will be applied. [Object] Therefore, an object of the present invention is to optimize the pixel potential of the nth scan line when displaying the (n-1) th scan line to improve the durability of the TFT.

[0008]

According to the present invention, a pixel electrode of a liquid crystal cell is connected via a thin film transistor to each intersection of a gate bus line and a data bus line arranged in a cross shape, and the pixel electrode of the pixel electrode is connected. In a liquid crystal display device in which an auxiliary capacitance C _S is formed between a part of a gate bus line before one scan line and a part of a gate bus line before one scan line, the potential of the pixel electrode is set to a predetermined potential in response to the potential of the gate bus line before one scan line. It is characterized in that a clamp means for clamping is provided.

[0009]

According to the present invention, in the display period of the (n-1) th scan line, the pixel potential of the nth scan line is clamped to a predetermined potential. Therefore, the auxiliary capacitance C _S
The influence of the gate voltage of the (n-1) th scan line transmitted via the TFT is avoided, and the durability of the TFT is improved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are views showing a first embodiment of a liquid crystal display device according to the present invention. First, the configuration will be described. In FIG. 1, 10 _n , 10 _n-1 are gate bus lines arranged in scan line order, 11 is a data bus line,
These typically show a part of a large number of gate bus lines and data bus lines arranged in a cross shape.

Gate bus line 10_n10,_n-1And day
A liquid crystal cell 1 is provided at each intersection of the tabas lines 11.
Two_{(n, m)}, 12_{(n-1, m)}Is provided for each liquid crystal cell
Is a thin film transistor (TFT) 13_n, 13_n-1as well as
Pixel electrode 14_n, 14_n-1And the pixel electrode 1
Four_nAnd (n-1) gate bus line one scan line before
10 _n-1Auxiliary capacitance C between_STo form an image
Elementary electrode (typically 14_n) And the data bus line 11
In addition, a clamp hand that uses a thin film transistor (TFT)
Step 15_nConnect and configure.

In such a configuration, the (n-1) th scan
When displaying the can line, the gate bus line 10
_n-1Potential (gate potential VG_(n-1)) Is pulled to +10 number V
To display the next nth scanline.
If the gate bus line 10 _nPotential (gate potential VG
_(n)) Is also raised to +10 and several volts. Sanawa
The gate bus line 10 along the scan direction_n1
0_n-1The potential of is raised in a line-sequential manner.

When either gate potential is raised,
TFT connected to the gate bus line (eg 13 _n )
Is turned on, the potential of the data bus line 11 at that time is written into the liquid crystal cell 12 _{(n, m)} through the TFT 13 _n , and becomes the pixel potential VD. Here, when the (n-1) th scan line, that is, the previous scan line is displayed, the potential VG _{(G-1) of the} gate bus line 10 _n-1 is raised to +10 number V. Because
The clamp means 15 _{n of the nth} scan line (in this case, the scan line after one) is turned on.

Therefore, according to this embodiment, the data bus line 11 and the pixel electrode 14 _n of the liquid crystal cell 12 _{(n, m)} are connected to each other through the minute ON resistance of the clamp means 15 _n , and the pixel electrode 14 _n potential (pixel potential VP)
However, as a result of being clamped to the potential of the data bus line 11 at that time, the maximum value of the gate-source voltage of the TFT 13 _n can be lowered as compared with the above-mentioned conventional example, and TF
The durability of T13 _n can be improved.

FIG. 2 shows the gate potential VG in this embodiment.
It is a figure which shows the time relationship between _(n) and pixel potential VP. In this figure, in the period A corresponding to the display period of the (n-1) th scan line, the clamp means 15n of the _nth scan line is in the ON state, so that it depends on the size of this clamp means (TFT). Efficiency, pixel potential V
P is suppressed. FIG. 3 is an enlarged view of period A in FIG.
The characteristic line "a" is obtained by setting W of the size parameter of the TFT used for the clamp means to 5 .mu.m. Also,
The characteristic line "B" is the same as when W is 10 μm, the characteristic line "C" is the same when W is 15 μm, and the characteristic line "D"
Also has W of 20 μm, and the characteristic line “e” has W of 25 μm. However, in each case L
Is 12 μm. As can be understood from this figure, the larger the size of the TFT used for the clamp means, in other words, the smaller the on-resistance, the more the maximum value of the pixel potential VP can be suppressed, and the durability can be improved. it can.

The present invention is not limited to the above embodiment, and various modifications can be considered within the intended range. The preferred modifications are listed below,
The same reference numerals are given to the circuit elements common to the above-mentioned embodiments, and the description thereof will be omitted. FIG. 4 is a diagram showing a second embodiment of the liquid crystal display device according to the present invention, in which the potential (pixel potential) of the pixel electrode (typically 14 _n ) is set to the pixel electrode 14 _n-1 one scan line before. This is an example in which the electric potential (pixel electric potential) is clamped.

That is, 20 _n is a clamp means provided in one liquid crystal cell 21 _{(n, m)} of the _nth scan line, and this clamp means 20 _n uses a thin film transistor (TFT). The drain and the source are respectively connected to two pixel electrodes 14 _n and 14 _n-1 which are adjacent to each other in the scanning direction, and the gate thereof is connected to the gate bus line 10 _n-1 of the (n-1) th scan line. .

According to this, in the display period of the (n-1) th scan line, the clamp means _20n is turned on, and the pixel electrode 14 of the (n-1) th scan line is turned on.
The potential (pixel potential) of the pixel electrode 14 _n of the n-th scan line can be reduced by a value corresponding to the potential of _n−1 (pixel potential).
Therefore, similarly to the first embodiment, the gate-source voltage of the TFT 13 _n can be lowered and the durability can be improved.

FIG. 5 and FIG. 6 are views showing a third embodiment of the liquid crystal display device according to the present invention.
In this example, the potential (pixel potential) of 4 _n ) is clamped by the potential of the common electrode (counter electrode or common electrode) (hereinafter, common potential). That is, 30 _n is a clamp means provided in one liquid crystal cell 31 _{(n, m)} of the _nth scan line, and this clamp means 30 _n is
A thin film transistor (TFT) is used, and its drain (or source) is connected to the pixel electrode 14 _n , and its source (or drain) is connected to the common electrode 33 via the bump 32.

According to this, as shown in FIG.
In the display period B of the _nth scan line, the clamp means 30 _n is turned on, and the potential (pixel potential) of the pixel electrode 14 _n of the _nth scan line can be reduced to a common potential. Therefore, similarly to the first embodiment, the gate-source voltage of the TFT 13 _n can be lowered and the durability can be improved.

[0021]

As described above, according to the present invention, the pixel potential of the n-th scan line when displaying the (n-1) -th scan line can be optimized and T
It is possible to improve the durability of the FT.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of a first embodiment.

FIG. 2 is a diagram showing a time relationship between a gate potential and a pixel potential according to the first embodiment.

FIG. 3 is a partially enlarged view of FIG.

FIG. 4 is a configuration diagram of a main part of a second embodiment.

FIG. 5 is a configuration diagram of a main part of a third embodiment.

FIG. 6 is a diagram showing a time relationship between a gate potential and a pixel potential according to the third embodiment.

FIG. 7 is a configuration diagram of a main part of a conventional example.

FIG. 8 is a plan layout view of a main part of a conventional example.

FIG. 9 is a diagram showing a time relationship between a gate potential and a pixel potential in a conventional example.

[Explanation of symbols]

C _S : auxiliary capacitance 10 _n , 10 _n-1 : gate bus line 11: data bus line 12 _{(n, m)} , 12 _{(n-1, m)} , 21 _{(n, m)} , 31 _{(n, m)} :
Liquid crystal cell 13 _n : TFT (thin film transistor) 14 _n , 14 _n-1 : Pixel electrode 15 _n , 20 _n , 30 _n : Clamping means

Claims (1)

[Claims] 1. A pixel electrode of a liquid crystal cell is connected via a thin film transistor to each intersection of a gate bus line and a data bus line arranged in a cross shape, and a part of the pixel electrode and a gate one scan line before. In a liquid crystal display device which forms an auxiliary capacitance (C _S ) with a part of a bus line, a clamp means for clamping the potential of the pixel electrode to a predetermined potential in response to the potential of the gate bus line one scan line before is provided. A liquid crystal display device characterized by being provided.