JPH0594299A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:To prevent processing content data written in a programmable ROM from being read by the third person and to hold the secrecy of system specification. CONSTITUTION:Based on read inhibit data '0' stored in a read inhibit information area 16 allocated into a PROM 3, an AND circuit 18a regulates the output of the processing content data from a PROM 3 to a general-purpose PROM data input/output circuit 7, and an AND circuit 18b regulates the output of test mode signals due to a CPU 1 for selectively outputting the processing content data, which are inputted from the PROM 3 to the CPU 1, to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general-purpose PROM.
The present invention relates to a semiconductor circuit device having a built-in (Programmable read only memory).

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration of a conventional semiconductor circuit device. As shown in FIG. 2, the conventional semiconductor circuit device 150 is provided with a general-purpose PROM address input in order to allow external access (writing and reading) to a built-in programmable ROM (hereinafter referred to as “PROM”) 30. It has a circuit 5 and a general-purpose PROM data input / output circuit 7, and the general-purpose PROM address input circuit 5 and PROM 30 are connected by a PROM write / read address line 6, and a general-purpose PROM
Between the ROM data input / output circuit 7 and the PROM 30 is P
The ROM write data line 8 and the general-purpose PROM data output line 9 are connected to each other. This general-purpose PROM
The address input circuit 5 and the general-purpose PROM data input / output circuit 7 allow data (processing content data in the central processing unit 1) to be written to and read from the PROM from the outside.

A central processing unit (hereinafter "CPU")
That. ) 1 and the PROM 30 are connected by a processing address line 2 and a processing data line 4, and the CPU 1 uses the processing address line 2 as a PROM.
The processing content data to be executed is requested to the processing data line 30, and the processing data line 4 obtains the processing content data from the PROM 30.

Further, an output selection circuit 12 is connected to the CPU 1 via a CPU arithmetic processing output line 10 for outputting an arithmetic result and a test mode signal line 11. The output selection circuit 12 includes processing data lines 4 and C.
One of the PU arithmetic processing output lines 10 is selected, and the internal information of the semiconductor circuit device 150 is discharged to the outside by the output circuit 14 via the output line 13.

That is, in the normal mode in which the CPU operates in accordance with the execution instruction of the processing contents stored in the PROM 30, the CPU 1 does not instruct the output selection circuit 12 via the test mode signal line 11 with the test mode signal, so that the output selection circuit 12 is a CPU arithmetic processing output line 1
0 is selected, and the calculation result by the CPU 1 is output to the output circuit 14 accordingly. In addition, the semiconductor circuit device 15
In the test mode in which the 0 test is performed, the CPU1
Is the output selection circuit 1 via the test mode signal line 11.
2 by the test mode signal, the output selection circuit 12 selects the processing data line 4, and
The processing content data transmitted from the PROM 30 to the CPU 1 is output to the output circuit 14.

By the respective functions of the semiconductor circuit device 150 having the built-in general-purpose PROM 30 as described above, the processing content data to be processed by the CPU 1 can be accurately set in the PROM 30, and the test mode of the semiconductor circuit device 150 can be set. At times, access verification between the CPU 1 and the PROM 30 can be performed.

[0007]

However, in the conventional semiconductor circuit device having such a configuration, even a third party can easily read the processing content data written in the PROM 30, and the system specifications can be improved. There was a problem that the confidentiality of the Therefore, an object of the present invention is to provide a semiconductor circuit device capable of preventing the processing content data written in the programmable ROM from being read by a third party, and maintaining confidentiality of system specifications.

[0008]

A semiconductor circuit device according to the present invention includes a programmable ROM, a read prohibition information area, an address input circuit and a data input / output circuit, and a first
It has a regulation function and a second regulation function. The programmable ROM stores processing content data to be arithmetically processed by the central processing unit. The read prohibition information area is allocated in the programmable ROM and stores read prohibition data. The address input circuit and the data input / output circuit are for externally executing writing and reading of process content data with respect to the programmable ROM. The first regulation function regulates the output of the processing content data from the programmable ROM to the data input / output circuit based on the read prohibition data stored in the read prohibition information area. The second regulation function stores the output of the test mode signal by the central processing unit for selectively outputting the processing content data input from the programmable ROM to the central processing unit to the outside in the read prohibition information area. The restriction is based on the read prohibition data.

[0009]

According to the structure of the present invention, the programmable RO
The first restricting function restricts the output of the processing content data from the programmable ROM to the data input / output circuit based on the read restricting data stored in the read prohibiting information area allocated in M, and the second restricting function is , The output of the test mode signal by the central processing unit for selectively outputting the processing content data input from the programmable ROM to the central processing unit to the outside is restricted.

Therefore, after writing the read inhibit data in the read inhibit information area, the programmable R
It becomes impossible to read the processing content data stored in the OM from the outside, and it is also impossible to output the processing content data transmitted from the programmable ROM to the central processing unit to the outside.

[0011]

1 is a block diagram showing the configuration of a semiconductor circuit device according to an embodiment of the present invention. As shown in FIG. 1, a programmable ROM (hereinafter referred to as “PROM”) 3
Is for storing processing content data to be arithmetically processed by the central processing unit (hereinafter referred to as “CPU”) 1, and a read prohibition information area 16 for storing read prohibition data is allocated therein. It is a thing. The data in the read prohibition information area 16 can be taken out by the read prohibition information line 17. Like the other areas in the PROM 3, the read prohibition information area 16 can be set to "0" when the data in the area is "1", but once the data is set to "0", it is "1". It cannot be returned to.

A general-purpose PRO that serves as an address input circuit
The M address input circuit 5 and the general-purpose PROM data input / output circuit 7 serving as a data input / output circuit are external
Is for writing and reading processing content data to and from. The general-purpose PROM address input circuit 5 is connected to the PROM 3 by the PROM write / read address line 6. In addition, general-purpose PROM
The data input / output circuit 7 is a PROM write data line 8
Is connected to the PROM3.

Further, the AND circuit 18 serving as the first regulation function
In a, the general purpose PROM data output line 9 from the PROM 3 and the read prohibition information line 17 from the read prohibition information area 16 are connected to the input end, and the output end is connected to the general purpose PRO.
The MROM I / O circuit 7 is connected to the M data I / O circuit 7, and the PROM 3 to the general-purpose PROM data I / O circuit 7 is based on the read prohibition data stored in the read prohibition information area 16.
The output of the processing content data to is regulated.

The CPU 1 and the PROM 3 are connected by the processing address line 2 and the processing data line 4, and the CPU 1 requests the processing content data to be executed from the PROM 3 by the processing address line 2 and the processing data. The line 4 obtains the processing content data from the PROM 3. Also, the processing data line 2 and the CPU
The CPU arithmetic processing output line 10 of FIG.
Connected to 2. The test mode signal line 11 of the CPU 1 and the read prohibition information line 17 of the PROM 3 are connected to the output selection circuit 12 via the AND circuit 18b serving as the second regulating function. The output selection circuit 12 is connected to the output circuit 14 by the output line 13.

The output selecting circuit 12 selects the CPU arithmetic processing output line 10 in the normal mode and connects it to the output circuit 14 via the output line 13, and selects the processing data line 4 in the test mode and outputs it. It is connected to the output circuit 14 via the line 13. That is, the arithmetic processing data output from the CPU 1 is output to the output circuit 14 in the normal mode, and the PROM 3 is output in the test mode.
The processing content data output to the CPU 1 from the output circuit 1
4 can be output.

In order to enter the test mode, the CPU 1 needs to instruct the output selection circuit 12 by the test mode signal, but the AND circuit 18b serving as the second regulation function.
The output of the test mode signal is restricted based on the read prohibition data stored in the read prohibition information area 16. The semiconductor circuit device 15 thus configured first writes “1” as data in the read prohibition information area 16. As a result, the general-purpose PROM data output line 9 is connected to the general-purpose PROM data input / output circuit 7, and the general-purpose PROM address input circuit 5 and the general-purpose PROM data input / output circuit 7 are used to output processing content data from the outside to the PROM 3. Writing and reading are possible, and processing content data can be freely set and changed. Similarly, the test mode signal line 11 is also connected to the output selection circuit 12, and C
When the PU1 instructs the output selection circuit 12 via the test mode signal line 11 with the test mode signal, the output selection circuit 12 selects the processing data line 4 and outputs the processing content data transmitted from the PROM 3 to the CPU 1 to the outside. It becomes possible to read. Thereby, the inspection of the processing content data transmitted from the PROM 3 to the CPU 1, that is, the access inspection between the PROM 3 and the CPU 1 can be performed in the same manner as in the conventional case.

After the inspection is carried out in this manner, the read prohibition data "0" is written in the read prohibition information area 16 so that the AND circuits 18a and 18b can read the PROM3 based on the read prohibition data "0". The output of the processing content data and the output of the test mode signal to the general-purpose PROM data input / output circuit 7 are regulated. That is, the AND circuit 18a to which the read inhibition data “0” is input is the general-purpose PROM for transmitting the processing content data from the PROM 3 to the general-purpose PROM input / output data circuit 7.
The output line 9 is disconnected, and the AND circuit 18
In b, the test mode signal line 11 for transmitting the test mode signal by the CPU 1 is brought into a non-connection state, so that the output selection circuit 12 selects only the CPU arithmetic processing output line 4 and connects it to the output circuit 12. Become. This makes it impossible to read the processing content data stored in the PROM 3 from the outside, and the PROM 3
It becomes impossible to output the processing content data transmitted from the CPU 1 to the CPU 1 to the outside.

Therefore, a third party cannot read the processing content data written in the PROM 3 to the outside. As a result, it is possible to realize a semiconductor circuit device in which confidentiality of system specifications can be maintained and quality inspection can be performed as in the conventional case.

[0019]

According to the semiconductor circuit device of the present invention, the first regulating function transfers the programmable ROM to the data input / output circuit based on the read inhibit data stored in the read inhibit information area allocated in the programmable ROM. The second regulating function regulates the output of the processing content data, and the second regulating function controls the test mode signal by the central processing unit for selectively outputting the processing content data input from the programmable ROM to the central processing unit to the outside. Regulate output.

Therefore, after writing the read inhibit data in the read inhibit information area, the programmable R
It becomes impossible to read the processing content data stored in the OM from the outside, and it is also impossible to output the processing content data transmitted from the programmable ROM to the central processing unit to the outside. As a result, it becomes impossible for a third party to read the processing content data written in the programmable ROM to the outside, and it is possible to obtain a semiconductor circuit device in which the confidentiality of the system specifications is maintained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional semiconductor circuit device.

[Explanation of symbols]

1 CPU (central processing unit) 3 PROM (programmable ROM) 5 general-purpose PROM address input circuit (address input circuit) 7 general-purpose PROM data input / output circuit (data input / output circuit) 15 semiconductor circuit device 16 read prohibition information area 18a AND circuit (First regulation function) 18b AND circuit (Second regulation function)

Claims (1)

[Claims] 1. A programmable ROM for storing processing content data to be arithmetically processed by a central processing unit, a read prohibition information area for storing read prohibition data allocated in the programmable ROM, and the programmable ROM externally. An address input circuit and a data input / output circuit for writing and reading the processing content data to and from the programmable ROM to the data input / output circuit; With a first regulating function for regulating based on read prohibition data stored in the central processing unit for selectively outputting processing content data input from the programmable ROM to the central processing unit to the outside. Read the test mode signal output The semiconductor circuit device having a second regulating function of regulating on the basis of the read disable data stored in prohibited information area out.