JPH0590426A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0590426A JPH0590426A JP24857391A JP24857391A JPH0590426A JP H0590426 A JPH0590426 A JP H0590426A JP 24857391 A JP24857391 A JP 24857391A JP 24857391 A JP24857391 A JP 24857391A JP H0590426 A JPH0590426 A JP H0590426A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gas
- insulating film
- polyimide
- plasma cvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、ポリイミド膜を層間絶縁膜とする多層配線の製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a multi-layer wiring using a polyimide film as an interlayer insulating film.
【0002】[0002]
【従来の技術】従来のポリイミド層間絶縁膜多層配線製
造方法を図3で説明する。基板1にアルミ合金より成る
下層アルミ配線2を形成する(a)。次にポリイミド前
駆体溶液をスピン塗布法によって塗布した後約100℃
から約400℃まで段階的に加熱して1.0ミクロン層
のポリイミド膜3をつけ層間絶縁膜とする(b)。2μ
m厚程度のフォトレジスト膜4をつけ、フォトリソグラ
フィ法にてフォトレジストのスルーホール部5を開口す
る(c)。酸素ガスを用いたプラズマエッチング法にて
フォトレジスト膜4及びスルーホール部5のポリイミド
膜3をエッチングし、スルーホール部5のポリイミド膜
3が除去され、フォトレジスト膜4が0.5μm程度残
った時点でエッチングを止める(d)。レジスト剥離液
を用いてフォトレジストを除去する(e)。次に、スパ
ッタ法にて約1ミクロン厚のアルミ合金膜6をつける。
フォトリソグラフィ法にて形成したフォトレジストから
露出したアルミ合金膜を塩素ガスを用いたプラズマエッ
チング法にて除去し、次にレジスト剥離液にてフォトレ
ジストを除去して上層アルミ配線7を形成する(f)。
プラズマCVD法にてアンモニア,シランを原料ガスと
して1ミクロン厚程度のシリコン窒化膜8をつけて保護
膜とする(g)。尚図では示さないがこの後ワイアーボ
ンディング箇所の保護膜を開口する。2. Description of the Related Art A conventional method for manufacturing a polyimide interlayer insulating film multilayer wiring will be described with reference to FIG. The lower layer aluminum wiring 2 made of an aluminum alloy is formed on the substrate 1 (a). Next, after applying a polyimide precursor solution by spin coating, the temperature is about 100 ° C.
To about 400 ° C. and the 1.0 μm layer polyimide film 3 is applied to form an interlayer insulating film (b). 2μ
A photoresist film 4 having a thickness of about m is applied and a through hole portion 5 of the photoresist is opened by photolithography (c). The photoresist film 4 and the polyimide film 3 in the through hole portion 5 were etched by the plasma etching method using oxygen gas to remove the polyimide film 3 in the through hole portion 5 and the photoresist film 4 remained about 0.5 μm. At this point, the etching is stopped (d). The photoresist is removed using a resist stripper (e). Next, an aluminum alloy film 6 having a thickness of about 1 micron is applied by the sputtering method.
The aluminum alloy film exposed from the photoresist formed by the photolithography method is removed by the plasma etching method using chlorine gas, and then the photoresist is removed by the resist stripping solution to form the upper layer aluminum wiring 7 ( f).
A protective film is formed by applying a silicon nitride film 8 having a thickness of about 1 micron using ammonia and silane as source gases by the plasma CVD method (g). Although not shown in the figure, after this, the protective film at the wire bonding portion is opened.
【0003】[0003]
【発明が解決しようとする課題】前述のレジスト剥離方
法は、一般的にはABS(アルモルベンゼンスルホン
酸)P,フェノール等が含まれる有機溶媒を約100℃
に昇温し、基板を5〜10分浸す処理を行っている。In the above-mentioned resist stripping method, generally, an organic solvent containing ABS (almol benzene sulfonic acid) P, phenol, etc. is added at about 100.degree.
The temperature is raised to, and the substrate is immersed for 5 to 10 minutes.
【0004】しかしながらこの処理において、ポリイミ
ド膜の電気絶縁性が劣化する問題がしばしば発生した。
この原因は明らかではないがポリイミド表面にリーク層
が生じ、この結果層抵抗換算で数十〜数百MΩのリーク
パスが配線間に存在することとなり、LSIの回路動作
不良に至るため良品歩留を著しく低下させてしまう結果
となった。However, in this process, the problem that the electric insulation of the polyimide film is deteriorated often occurs.
Although the cause of this is not clear, a leak layer is generated on the surface of the polyimide, and as a result, a leak path of several tens to several hundreds MΩ in terms of layer resistance exists between the wirings, which leads to defective circuit operation of the LSI, resulting in a good product yield. This resulted in a significant decrease.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、ポリイミド系樹脂より成る層間絶縁膜表面
に、金属配線層を形成した基板を酸素・四フッ化炭素・
六フッ化硫黄ガスの単体あるいは混合ガスを用いたプラ
ズマエッチング法若しくはアルゴンガスを用いたスパッ
タエッチング法により前記層間絶縁膜表面を2000オ
ングストローム以下のエッチングをした後第2の絶縁膜
を形成する工程を備えている。According to a method of manufacturing a semiconductor device of the present invention, a substrate having a metal wiring layer formed on a surface of an interlayer insulating film made of a polyimide resin is treated with oxygen / carbon tetrafluoride.
A step of forming a second insulating film after etching the surface of the interlayer insulating film to 2000 angstroms or less by a plasma etching method using a sulfur hexafluoride gas alone or a mixed gas or a sputter etching method using an argon gas. I have it.
【0006】[0006]
【実施例】次に本発明について図面を用いて説明する。The present invention will be described below with reference to the drawings.
【0007】図1は一実施例を示し、従来と同様に
(f)図の様に上層アルミ配線まで形成する。次に
(g)図の様にプラズマCVD装置に於いて、基板1を
リアクタ内に入れ減圧した後に酸素ガスを導入した圧力
を約1Torrとし膜成長とほぼ同様な2kwのRFパ
ワーを加えて3分程度処理しポリイミド表面を約500
〜1000オングストロームエッチングする。その後一
旦真空引きを行い、次に通常の条件にて、アンモニア,
シラン等の原料ガスを導入してシリコン窒化膜8をつけ
る。従来よりリアクタ内のクリーニングのためにS
F6 ,NF3 などのフッ化ガスや酸素ガスはプラズマC
VD装置に導入されており、工業的に見ても容易に実現
できる。FIG. 1 shows an embodiment in which the upper aluminum wiring is formed as shown in FIG. Next, in the plasma CVD apparatus as shown in FIG. 6 (g), the pressure in which the substrate 1 was put into the reactor and decompressed and then oxygen gas was introduced was set to about 1 Torr, and RF power of 2 kw, which is almost the same as the film growth, was applied to the 3 Approximately 500 minutes after processing the polyimide surface
Etch ~ 1000 angstroms. After that, evacuate once, then under normal conditions, ammonia,
A source gas such as silane is introduced to attach the silicon nitride film 8. S for cleaning the inside of the reactor
Fluorine gas such as F 6 and NF 3 and oxygen gas are plasma C
It has been introduced into the VD device and can be easily realized from an industrial point of view.
【0008】第2の実施例を、図2で説明する。従来通
り、上層アルミ配線7の形成後(f)、レジストドライ
除去装置として用いられるバレル型プラズマエッチング
装置を用い圧力を0.5Torrとした酸素プラズマに
て200w,3分程度の処理でポリイミド表面を500
オングストローム程度エッチングする。この後従来通
り、プラズマCVD装置を用いてシリコン窒化膜をつけ
る(g)。また、プラズマCVD装置による膜成長前に
基板表面を純水で洗浄しても何ら問題はない。The second embodiment will be described with reference to FIG. As in the prior art, after forming the upper layer aluminum wiring 7 (f), the polyimide surface is treated with oxygen plasma at a pressure of 0.5 Torr for about 200 minutes for about 3 minutes using a barrel type plasma etching apparatus used as a resist dry removing apparatus. 500
Etch about angstrom. After this, a silicon nitride film is attached by using a plasma CVD device as in the conventional case (g). Further, there is no problem even if the surface of the substrate is washed with pure water before the film growth by the plasma CVD apparatus.
【0009】また上に挙げた方法以外にエッチングガス
として四フッ化炭素や六フッ化炭素を用いたり、それら
と酸素ガスとの混合ガスとして用いたりしても充分な効
果が確認される。In addition to the above-mentioned methods, sufficient effects can be confirmed by using carbon tetrafluoride or carbon hexafluoride as an etching gas or using a mixed gas of them with oxygen gas.
【0010】またプラズマエッチングの代わりにアルゴ
ンガスイオンを用いたスパッタエッチングでも可能であ
ることも確認されている。さらに、保護膜としてシリコ
ン酸化・窒化膜,シリコン酸化膜,シリコンリン酸化膜
をプラズマCVD法で付けても効果は変わらない。It has also been confirmed that sputter etching using argon gas ions can be used instead of plasma etching. Furthermore, the effect does not change even if a silicon oxide / nitride film, a silicon oxide film, or a silicon phosphoric oxide film is applied as a protective film by the plasma CVD method.
【0011】[0011]
【発明の効果】以上説明したように本発明は、既存の設
備を利用してポリイミド層間絶縁膜表面のリーク不良を
解決し、安定して歩留よく多層配線LSIを製造できる
ので、高性能LSIが低コストで製造できる効果があ
る。As described above, according to the present invention, it is possible to solve the leak failure on the surface of the polyimide interlayer insulating film by utilizing the existing equipment and to stably manufacture the multilayer wiring LSI with high yield. Has the effect that it can be manufactured at low cost.
【図1】本発明の第1実施例を説明する多層配線技術の
製造工程を示す断面図。FIG. 1 is a cross-sectional view showing a manufacturing process of a multilayer wiring technique for explaining a first embodiment of the present invention.
【図2】本発明の第2実施例を説明する多層配線技術の
製造工程を示す断面図。FIG. 2 is a cross-sectional view showing a manufacturing process of a multilayer wiring technique for explaining a second embodiment of the present invention.
【図3】従来の多層配線技術の製造工程を示す断面図。FIG. 3 is a cross-sectional view showing a manufacturing process of a conventional multilayer wiring technique.
【符号の説明】 1 基板 2 下層アルミ配線 3 ポリイミド膜 4 フォトレジスト 5 スルーホール部 6 アルミ合金膜 7 上層アルミ配線 8 シリコン窒化膜[Explanation of symbols] 1 substrate 2 lower layer aluminum wiring 3 polyimide film 4 photoresist 5 through hole portion 6 aluminum alloy film 7 upper layer aluminum wiring 8 silicon nitride film
Claims (2)
面に金属配線層を形成した半導体基板を、酸素・四フッ
化炭素・六フッ化硫黄ガスの単体あるいは混合ガスを用
いたプラズマエッチング法若しくはアルゴンガスを用い
たスパッタエッチング法により前記層間絶縁膜表面を2
000オングストローム以下のエッチングした後第2の
絶縁膜を形成することを特徴とする半導体装置の製造方
法。1. A semiconductor substrate having a metal wiring layer formed on a surface of an interlayer insulating film made of a polyimide resin is treated by a plasma etching method using an oxygen / carbon tetrafluoride / sulfur hexafluoride gas or a mixed gas, or argon. The surface of the inter-layer insulation film is removed by a sputter etching method using gas.
A method of manufacturing a semiconductor device, which comprises forming a second insulating film after etching to a thickness of 000 angstroms or less.
用いて形成されたシリコン窒化膜,シリコン酸化・窒化
膜,シリコン酸化膜,又はシリコンリン酸化膜であるこ
とを特徴とする請求項1記載の半導体装置の製造方法。2. The second insulating film is a silicon nitride film, a silicon oxide / nitride film, a silicon oxide film, or a silicon phosphoric oxide film formed by using a plasma CVD method. A method for manufacturing a semiconductor device as described above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3248573A JP2757618B2 (en) | 1991-09-27 | 1991-09-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3248573A JP2757618B2 (en) | 1991-09-27 | 1991-09-27 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0590426A true JPH0590426A (en) | 1993-04-09 |
JP2757618B2 JP2757618B2 (en) | 1998-05-25 |
Family
ID=17180150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3248573A Expired - Fee Related JP2757618B2 (en) | 1991-09-27 | 1991-09-27 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2757618B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6274058B1 (en) | 1997-07-11 | 2001-08-14 | Applied Materials, Inc. | Remote plasma cleaning method for processing chambers |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6464237A (en) * | 1987-09-03 | 1989-03-10 | Sharp Kk | Forming method for multilayered interconnection in semiconductor device |
JPH01225339A (en) * | 1988-03-04 | 1989-09-08 | Nec Corp | Manufacture of multilayer wiring structure using resin interlayer film |
-
1991
- 1991-09-27 JP JP3248573A patent/JP2757618B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6464237A (en) * | 1987-09-03 | 1989-03-10 | Sharp Kk | Forming method for multilayered interconnection in semiconductor device |
JPH01225339A (en) * | 1988-03-04 | 1989-09-08 | Nec Corp | Manufacture of multilayer wiring structure using resin interlayer film |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6274058B1 (en) | 1997-07-11 | 2001-08-14 | Applied Materials, Inc. | Remote plasma cleaning method for processing chambers |
Also Published As
Publication number | Publication date |
---|---|
JP2757618B2 (en) | 1998-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4557479B2 (en) | Photoresist removal process using forming gas plasma | |
JP3189781B2 (en) | Method for manufacturing semiconductor device | |
US6465352B1 (en) | Method for removing dry-etching residue in a semiconductor device fabricating process | |
JPH03204928A (en) | Formation of contact hole | |
JPH07201834A (en) | Dry etching method | |
KR950005351B1 (en) | How to prevent corrosion of aluminum alloys | |
KR20020032342A (en) | Method of producing semiconductor device | |
JPH0590426A (en) | Manufacture of semiconductor device | |
JPH09172079A (en) | Semiconductor device and its manufacture | |
JPH01100946A (en) | Manufacture of semiconductor device | |
JP4559565B2 (en) | Method for forming metal wiring | |
KR20220156881A (en) | A method for EUV reverse patterning in the processing of microelectronic materials | |
KR20020063815A (en) | Method for forming an interconnect pattern in a semiconductor device | |
JPH1131683A (en) | Manufacture of semiconductor device | |
JPH0547720A (en) | Removing method of natural oxide film | |
KR20000071322A (en) | Method of manufacturing a semiconductor device | |
JP3156374B2 (en) | Method for manufacturing semiconductor device | |
JP3440599B2 (en) | Via hole formation method | |
JPH08213366A (en) | Pattern forming method, pattern forming equipment, manufacture of semiconductor integrated circuit device, and semiconductor manufacturing equipment | |
KR100600259B1 (en) | Manufacturing Method of Semiconductor Device | |
JP3428927B2 (en) | Dry etching method | |
JP2708019B2 (en) | Contact hole formation method | |
JPH06216264A (en) | Semiconductor device and manufacture thereof | |
JPH0653134A (en) | Manufacture of semiconductor device | |
JP2708018B2 (en) | Contact hole formation method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980210 |
|
LAPS | Cancellation because of no payment of annual fees |