JPH0582711A - Manufacture of wiring board - Google Patents

Manufacture of wiring board

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Publication number
JPH0582711A
JPH0582711A JP24548091A JP24548091A JPH0582711A JP H0582711 A JPH0582711 A JP H0582711A JP 24548091 A JP24548091 A JP 24548091A JP 24548091 A JP24548091 A JP 24548091A JP H0582711 A JPH0582711 A JP H0582711A
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Prior art keywords
film
insulation film
formed
insulating film
silicon
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JP24548091A
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Japanese (ja)
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JP2871222B2 (en
Inventor
Kenzo Hatada
Takayuki Yoshida
隆幸 吉田
賢造 畑田
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Priority to JP24548091A priority Critical patent/JP2871222B2/en
Publication of JPH0582711A publication Critical patent/JPH0582711A/en
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Publication of JP2871222B2 publication Critical patent/JP2871222B2/en
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Abstract

PURPOSE:To obtain a substrate for low dielectric multi-chip module which can operate at high frequency. CONSTITUTION:A first insulation film 2 is formed on a silicon substrate 1 where a large number of small holes 3 are formed based on a dry etching process. The silicon alone from these small holes 3 are etched by the application of a potassium hydroxide solution or a hydrofluoric-nitric acid mixed solution and cavities 4 are formed. Then, a second insulation film 5 is further formed on the first insulation film 2 where a large number of small holes 3 are bored and an electric conductor thin film wiring 6 is formed on the second insulation film 5. Therefore, the following effects can be expected by forming an air layer or a vacuum layer below the first insulation film 2. (1): The specific dielectric of the cavity portion is about epsilongamma=1, which is about one fourth of arsenic oxide. (2): When the thickness of the cavity portion is identical to that of the first insulation film, the total capacity is about one fifth the insulation film alone. (3): When the condition is identical to that represented by (2), the time constant is about one fifth the insulation film along.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体の実装形態の一つであるマルチチップモジュールに用いる配線基板に関するものである。 The present invention relates to relates to a wiring substrate used in the multi-chip module, which is one of semiconductor implementation.

【0002】 [0002]

【従来の技術】近年、様々なマルチチップモジュールが提案されている。 In recent years, there have been proposed various multi-chip module.

【0003】以下図面を参照しながら、上記した従来のシリコン基板を用いたマルチチップモジュール用配線基板の一例について説明する。 [0003] with reference to the following drawings, description will be given of an example of a wiring substrate for multi-chip module using the conventional silicon substrate described above.

【0004】(図3)は従来のシリコン基板を用いたマルチチップモジュール用配線基板の電子部品を実装した状態での断面図を示すものである。 [0004] (Figure 3) shows a cross-sectional view of a state in which electronic components to the mounting wiring board for a multi-chip module using the conventional silicon substrate. ここでは電子部品はMBB(マイクロバンプボンディング実装技術)方式と呼ばれる方式により実装されている。 Here the electronic component is mounted by a method called MBB (micro bump bonding mounting technique) scheme. MBB方式は、バンプと呼ばれる金属突起を電極に形成した電子部品をフェースダウンで光硬化性絶縁樹脂により基板に実装する方法で、以後、単にMBB方式と呼ぶ。 MBB method, an electronic component forming a metal protrusions called bumps electrodes by a method of mounting on a substrate by photo-curable insulating resin face down, hereinafter simply referred to as MBB method. (図3)において、31はシリコン基板、32は酸化膜で、33は導体配線パターン、34はMBB方式により実装された電子部品である。 In (3), 31 denotes a silicon substrate, 32 is an oxide layer, 33 conductor wiring pattern, 34 is an electronic component mounted by the MBB method.

【0005】(図4)は従来のシリコン基板を用いたマルチチップモジュール用配線基板の作製プロセス断面図を示す。 [0005] (Fig. 4) shows a manufacturing process cross-sectional view of a wiring substrate for a multichip module using the conventional silicon substrate.

【0006】まず、シリコン基板31を熱酸化等で表面に酸化膜32を約1μm形成する(a)。 [0006] First, a silicon substrate 31 is about 1μm form an oxide film 32 on the surface by thermal oxidation or the like (a). 次に酸化膜32上に約1μm厚のアルミ等の導体配線パターン33をスパッタリング薄膜形成法、およびフォトリソグラフィー等の技術を組み合わせて形成する(b)。 Then a sputtering film forming method conductive wiring pattern 33 of aluminum or the like of about 1μm thick on the oxide film 32, and is formed by combining a technique such as photolithography (b). このとき多層配線を形成するときは、導体配線上にCVD(気相成長)、スピンコート等により層間絶縁膜を形成し、層間膜上に新たに導体配線パターンを形成する。 When this time to form a multilayer wiring, CVD on the conductor wiring (vapor deposition), an interlayer insulating film by spin coating or the like to form a new conductor wiring pattern on the interlayer film. 次に電子部品34を実装する。 Then mounting the electronic components 34. 実装方法は、TAB、ワイヤボンディング、フリップチップ、MBB方式等を用いる。 Mounting method, TAB, wire bonding, flip chip, using the MBB method, and the like. 例えば、MBB For example, MBB
方式で電子部品34を実装するときは、電子部品34の電極にバンプと呼ばれる金属突起35(以下単にバンプと呼ぶ。)を形成し、導体配線パターン33にチタン、パラジューム、金の3層(計約1μm厚)、またはクロム、金2層(計約500nm厚)からなるボンディングパッド36 When mounting electronic components 34 in the manner, the metal projection 35 (hereinafter simply referred to as bumps.) Called bump electrode of the electronic component 34 is formed, titanium conductor wiring patterns 33, palladium, three layers of gold (total approximately 1μm thick), or chromium, the bonding pad 36 made of gold two layers (a total of about 500nm thick)
をバンプ35に対応させて形成する(c)。 It was corresponding to the bump 35 formed by (c). 次に電子部品 Then the electronic components
34を必要な数だけMBB実装方式によりシリコン基板31 34 a silicon substrate 31 by as many MBB mounting method required the
に実装しマルチチップモジュールが完成する(d)。 Multi-chip module is mounted on is completed (d).

【0007】 [0007]

【発明が解決しようとする課題】しかしながら上記のような構成では、次のような問題点を有している。 In the [0005] However, as the above-described configuration has the following problems.

【0008】配線パターンの持つ静電容量はおおまかに次の式で近似できる。 [0008] The electrostatic capacitance of the wiring pattern can be roughly approximated by the following equation. C=εS/d (F) ここで、Cは静電容量、εは絶縁膜の誘電率、Sは配線面積、dは絶縁膜の厚さを示す。 C = εS / d (F) wherein, C is the capacitance, epsilon is the dielectric constant of the insulating film, S is the wiring area, d represents a thickness of the insulating film. この静電容量Cは配線を伝搬する信号の遅延に大きく影響する。 The electrostatic capacitance C greatly affects the delay of the signal propagating through the wiring. 例えば、幅30 For example, the width 30
μm、装延長20cmのアルミ配線を考える。 μm, think about the aluminum wiring of instrumentation extension 20cm. 絶縁膜はシリコンの熱酸化膜(ε=3.9x8.854x10 12 (F/m))、 Insulating film thermal oxide film of a silicon (ε = 3.9x8.854x10 12 (F / m)),
膜厚d=1μmとすると、上式から C=207.2 (pF) となり、平均的なアルミ配線の面抵抗ρ s =30(mΩ/ When the film thickness d = 1μm, C = 207.2 from the above equation (pF), and the average sheet resistance [rho s = 30 for aluminum wiring (milliohms /
□)を適用すると配線抵抗は約200Ωとなり、単純にR □) and applying the wiring resistance of about 200Ω, and the simple R
C線路で近似しても信号の立ち上がり、立ち下がりの時定数は τ=41.4 (ns) となり、非常に信号の立ち上がり、立ち下がりに時間がかかる。 Rise even signals approximated by a C line, constant τ = 41.4 (ns) next time falling, very rising edge of time to fall such. このため高周波領域では静電容量Cをできるだけ小さくしなければならないが、誘電率εおよび厚さd It must be as small as possible an electrostatic capacitance C in this order high frequency region, the dielectric constant ε and thickness d
は材料、および製法により決定されてしまうという問題点を有していた。 Had material, and the problem that is determined by the method.

【0009】本発明は上記問題点に鑑み、静電容量Cを小さくした構造のマルチチップモジュール用配線基板を提供するものである。 [0009] The present invention provides a multi-chip wiring board module of view of the above problems, has a small capacitance C structure.

【0010】 [0010]

【課題を解決するための手段】上記問題点を解決するために本発明は、シリコン等の半導体基板上に第1の絶縁膜を形成し、第1の絶縁膜に小さな穴を多数形成し、これら小さな穴からたとえば基板シリコンのみを水酸化カリウム混液、またはフッ硝酸混液を用いエッチング、空洞を形成した後、小さな穴を多数開けた第1の絶縁膜上に更に第2の絶縁膜を形成し、第2の絶縁膜上に導電体薄膜配線を形成するという構成を備えた配線基板の製造方法を提案するものである。 SUMMARY OF THE INVENTION The present invention to solve the above problem, a first insulating film formed on a semiconductor substrate such as silicon, a large number to form a small hole in the first insulating film, potassium only from these small holes e.g. substrate silicon hydroxide mixture or etching using a hydrofluoric-nitric acid mixture, after forming the cavity, and further forming a second insulating film on the first insulating film on which opened a large number of small holes , it proposes a method of manufacturing a wiring board having a structure that forms a conductive thin film wiring on the second insulating film.

【0011】 [0011]

【作用】本発明は上記した構成によって第1の絶縁膜の下に空気または真空の層を形成する。 DETAILED DESCRIPTION OF THE INVENTION The present invention forms a layer of air or vacuum below the first insulating film by the configuration described above. 空気、または真空の比誘電率はεr=1で、第一の絶縁膜に酸化珪素膜を用いたとき、酸化珪素膜の比誘電率εr=4であるので空洞の部分の比誘電率は単純に考えると、絶縁膜部分の4分の1となる。 Air or dielectric constant of a vacuum is .epsilon.r = 1,, when using a silicon oxide film on the first insulating film, the dielectric constant of the portion of the cavity since it is the relative dielectric constant .epsilon.r = 4 of the silicon oxide film simply Taken, a quarter of the insulating film portion. また第1の絶縁膜の下に、例えば第1 Further below the first insulating film, for example, the first
の絶縁膜と同じ厚さの空洞を形成すると、今、仮に絶縁膜の部分の静電容量をC 1とすると空洞部分の容量は大ざっぱに近似して1/4C 1となり、両者は直列につながっていることになるので総容量Cは1/5C 1となり絶縁膜のみの場合の5分の1となる。 When forming the same thickness cavity with the insulating film, now, if the capacity of the capacitance of C 1 to the hollow portion of the portion of the insulating film is roughly approximated to 1 / 4C 1 becomes, the both connected in series it means that the total capacity C is one-fifth of the case of only 1 / 5C 1 next insulating film. このとき時定数τも5分の1となる。 Also constant τ at this time becomes 1/5. このように配線部分の静電容量Cを非常に小さくすることができ、信号の伝搬遅延を大きく減少させることができる。 Thus very it is possible to reduce the electrostatic capacitance C of the wiring portion can be reduced greatly propagation delay of the signal.

【0012】 [0012]

【実施例】以下本発明の一実施例を図面を参照しながら説明する。 EXAMPLES be described with reference to the drawings an embodiment of the following invention.

【0013】(図1)は本発明におけるシリコン基板を用いたマルチチップモジュール用配線基板の電子部品を実装した状態での断面図を示すものである。 [0013] (Figure 1) shows a cross-sectional view of a state of mounting the electronic component of the wiring substrate for multi-chip module using a silicon substrate in the present invention. 例えば、ここでは電子部品はMBB方式により実装されている。 For example, where the electronic components are mounted by the MBB method.
(図1)において、1はシリコン基板、2は第1の絶縁膜で、3は第1の絶縁膜2に形成された小さな穴、4は第1の絶縁膜2の下に形成された空洞、5は第2の絶縁膜、6は導体配線パターン、7はMBB方式により実装された電子部品である。 In (1), 1 denotes a silicon substrate, 2 a first insulating film, 3 is a cavity small holes formed in the first insulating film 2, the 4 formed under the first insulating film 2 , the second insulating film 5, 6 is conductive wiring patterns, 7 is an electronic component mounted by the MBB method.

【0014】(図2)は本発明におけるシリコン基板を用いたマルチチップモジュール用配線基板の作製プロセス断面図を示す。 [0014] (Figure 2) shows a manufacturing process cross-sectional view of a wiring substrate for a multichip module using a silicon substrate in the present invention.

【0015】まず、シリコン基板1を熱酸化等で表面に酸化膜2を約1μmを形成する(a)。 [0015] First, a silicon substrate 1 to form an about 1μm oxide film 2 on the surface by thermal oxidation or the like (a). 次にフォトレジストにより第1の酸化膜2に直径0.5μm以下の小さな穴3を多数(51000ケ/mm 2以上、以降単に多数と表現する。)形成するためにあらかじめ設計したエッチング用のマスクパターン8を形成する(b)。 Photoresist by the first oxide film 2 many small holes 3 diameters below 0.5μm to (51000 Ke / mm 2 or more, expressed simply numerous later.) Pre-designed mask for etching to form forming a pattern 8 (b). フレオンガス等を用いたドライエッチング、またはフッ化水素溶液を用いたウエットエッチング等で第1の酸化膜2に直径0.5μm未満の小さな穴3(または、エッチング孔3 Dry etching or the hydrogen fluoride solution small holes 3 of the first oxide film 2 to a diameter of less than 0.5μm in wet etching or the like using, using Freon gas like (or, etch holes 3
と呼ぶ。 The call. )を多数形成する(c)。 ) Is a number form (c). 次に水酸化カリウム混液、またはフッ硝酸混液によりシリコン基板1をエッチングする。 By then potassium hydroxide mixture or hydrofluoric nitric acid mixture to etch the silicon substrate 1. このとき、ウエットエッチングであるためエッチング液はエッチング孔3から横方向にもひろがり酸化膜2下のシリコンもエッチングする。 The etching solution for a wet etching also etching the silicon oxide film 2 underneath spread in the lateral direction from the etching hole 3. フッ酸:硝酸:純水=1:300:200の液で約70分エッチングすることにより第1の酸化膜2の下に深さ約1μm、エッチング孔3も含めて直径約2.5μmのシリコンのエッチングされた空洞4を第1の酸化膜2の下面ほぼ全域に形成することができる(d)。 Hydrofluoric acid: nitric acid: pure water = 1: 300: 200 of the liquid at about By 70 minutes etched first depth of about 1μm under the oxide film 2, an etching hole 3 also silicon having a diameter of about 2.5μm, including it is possible to form a cavity 4 etched into a first bottom surface almost the entire oxide film 2 (d). このあと、このシリコン基板1を純水でよく洗浄した後、デシケータ内等にこのシリコン基板を入れ真空脱気する。 After this, well washed the silicon substrate 1 with pure water and vacuum degassing put this silicon substrate in a desiccator the like. これにより空洞4内の水分を蒸発させる。 Thereby evaporate water in the cavity 4. 次に、第1の酸化膜2上に第2の酸化膜5をCVD法等により約1μm形成し、第1の酸化膜に形成されたエッチング孔3をふさぐ(e)。 Next, a second oxide film 5 for about 1μm formed by CVD or the like on the first oxide film 2, closing the etching hole 3 formed in the first oxide layer (e). 次に第2の酸化膜5上に約1μm厚のアルミ等の導体配線パターン6をスパッタリング薄膜形成法、およびフォトリソグラフィー等の技術を組み合わせて形成する(f)。 Then a sputtering film forming method conductive wiring patterns 6 made of aluminum or the like of about 1μm thick on the second oxide film 5, and is formed by combining a technique such as photolithography (f).
このとき多層配線を形成するときは、導体配線上にCV When this time to form a multilayer wiring, CV on the conductor wire
D、スピンコート等により層間絶縁膜を形成し、層間膜上に新たに導体配線パターンを形成する。 D, an interlayer insulating film by spin coating or the like to form a new conductor wiring pattern on the interlayer film. 次にMBB実装方式で電子部品7を実装するときは、電子部品7の電極にバンプ8を形成し、導体配線パターン6にチタン、 Then when mounting the electronic component 7 is MBB mounting method, a bump 8 is formed on the electrode of the electronic component 7, titanium conductive wiring pattern 6,
パラジューム、金の3層(計約1μm)、またはクロム、金2層(計約500nm)からなるボンディングパッド9をバンプ8に対応させて形成する(g)。 Palladium, three layers of gold (total about 1 [mu] m), or chromium, the bonding pads 9 made of gold two layers (a total of approximately 500 nm) to correspond to the bumps 8 formed by (g). 次に電子部品7を必要な数だけMBB実装方式によりシリコン基板1に実装しマルチチップモジュールが完成する(h)。 Then the mounted multi-chip module is completed on the silicon substrate 1 by MBB mounting method required number of electronic components 7 (h). 10はLSIチップ等の電子部品と基板1との固着およびバンプ8とパッド9を直接コンタクトさせる光硬化性の絶縁樹脂である。 10 is a photo-curable insulating resin to contact directly the fixation and the bump 8 and the pad 9 between the electronic component and the substrate 1 such as an LSI chip.

【0016】このように構成することにより第1の絶縁膜の下に空気または真空の層を形成することができ、空気、または真空の比誘電率はεr=1である。 [0016] Thus under the first insulating film can be formed a layer of air or vacuum by forming, the dielectric constant of air or vacuum, is .epsilon.r = 1. このため、第一の絶縁膜に酸化珪素膜を用いたときの比誘電率εr=4であるのでの単純に考えると空洞の部分の比誘電率は酸化珪素膜の4分の1となる。 Therefore, the dielectric constant of the simplest analysis the hollow portion in the in the range of the relative dielectric constant .epsilon.r = 4 when using a silicon oxide film on the first insulating film is one fourth of the silicon oxide film. また第1の絶縁膜の下に、例えば第1の絶縁膜と同じ厚さの空洞を形成すると、今、仮に絶縁膜の部分の静電容量をC 1とすると空洞部分の容量は大ざっぱに近似して1/4C 1となり、両者は直列につながっていることになるので総容量Cは1/ Further below the first insulating film, for example, to form a cavity having the same thickness as the first insulating film, now, if the capacity of the capacitance of C 1 to the hollow portion of the portion of the insulating film is roughly approximated to 1 / 4C 1, and the both the total capacity C means that are connected in series 1 /
5C 1となり絶縁膜のみの場合の5分の1となる。 1 and consists of 5 minutes in the case of 5C 1 next insulating film only. このとき時定数τも5分の1となる。 Also constant τ at this time becomes 1/5. このように配線部分の静電容量Cを非常に小さくすることができ、信号の伝搬遅延を大きく減少させることができる。 Thus very it is possible to reduce the electrostatic capacitance C of the wiring portion can be reduced greatly propagation delay of the signal.

【0017】この実施例においては第1の絶縁膜にシリコンの熱酸化膜を用いたが、CVD法等により形成される酸化珪素膜、窒化珪素膜等の無機膜、あるいはポリイミド膜等の有機膜を用いることが可能であり、第2の絶縁膜にCVD法等により形成される窒化珪素膜等の無機膜、あるいはポリイミド膜等の有機膜を用いることも可能である。 [0017] While using a thermal oxide film of silicon on the first insulating film in this embodiment, a silicon oxide film formed by a CVD method or the like, an inorganic film such as a silicon nitride film or an organic film such as a polyimide film, it is possible to use, it is also possible to use the second inorganic film of the silicon nitride film or the like formed by CVD method or the like in the insulating film or an organic film such as a polyimide film.

【0018】また、前述したように、第1の酸化膜に多数のエッチング孔を形成するときに用いたフォトレジストのエッチング用マスクは、あらかじめパターン設計をしたものを用いてもよいが、フォトレジストを溶媒で薄め、この溶媒で薄めたフォトレジストをシリコン基板にスピンコートし、ピンホール密度を高めたフォトレジスト膜を形成し、このピンホールを有するフォトレジスト膜をエッチングマスクとして使用できる。 Further, as described above, an etching mask of photoresist used in forming a plurality of etching holes in the first oxide film may be used after the pre-patterned design, the photoresist the thinned with solvent, the photoresist diluted with this solvent was spin-coated on a silicon substrate, forming a photoresist film having an increased pin hole density can be used a photoresist film having the pinhole as an etching mask.

【0019】また、実装方式をMBB方式としたが、この構成の基板は、例えばTAB、ワイヤボンド、フリップチップ等の全ての実装方式に対しても有効である。 Further, although the mounting method was MBB method, the substrate of this configuration, for example TAB, wire bonds, it is effective for all mounting method such as a flip chip.

【0020】 [0020]

【発明の効果】以上のように本発明は、第1の絶縁膜の下に空気または真空の層を形成することにより以下のような効果がある。 The present invention as described above, according to the present invention has the following effects by forming a layer of air or vacuum below the first insulating film. (1)、空洞部分の比誘電率は約εr=1であり、酸化珪素の約4分の1である。 (1), the relative dielectric constant of the cavity portion is about .epsilon.r = 1, which is about a quarter of the silicon oxide. (2)、空洞部分のの厚さ第1の絶縁膜と同じにしたときは全容量は絶縁膜のみのときの約5分の1となる。 (2), the total volume when the same as the thickness a first insulating layer of the cavity portion becomes about 1/5 when only the insulating film. (3)、(2)の条件のとき、時定数は絶縁膜のみのときの約5分の1となる。 (3), when the condition (2), the time constant is about 1/5 in the case of only an insulating film.

【0021】以上のように配線部分の静電容量Cを非常に小さくすることができ、信号の伝搬遅延を大きく減少させることができ、高周波対応のマルチチップモジュールに充分対応できるものである。 [0021] The above electrostatic capacitance C of the wiring portion can be made very small as the signal propagation delay can greatly reduce the one in which can sufficiently correspond to the frequency response of the multi-chip module.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例における電子部品を実装したときの配線基板の断面図 Cross-sectional view of a wiring board when mounting the electronic component in an embodiment of the present invention; FIG

【図2】同実施例における配線基板形成プロセス工程断面図 [Figure 2] wiring board forming process sectional views in the same embodiment

【図3】従来例における電子部品を実装したときの配線基板の断面図 3 is a cross-sectional view of the wiring board when mounting the electronic components in the conventional example

【図4】同従来例における配線基板形成プロセス工程断面図 [4] the wiring board forming process sectional views in the same prior art

【符号の説明】 DESCRIPTION OF SYMBOLS

1 シリコン基板 2 第1の絶縁膜 3 第1の絶縁膜に形成された小さな穴 4 第1の絶縁膜の下に形成された空洞 5 第2の絶縁膜 6 導体配線パターン 7 MBB方式により実装された電子部品 Be implemented by 1 silicon substrate 2 first insulating film 3 and the first small holes formed in the insulating film 4 first insulating cavity formed under the film 5 second insulating film 6 conductor wiring patterns 7 MBB method electronic components

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体基板の一主面に第1の絶縁膜を形成する工程、前記第1の絶縁膜に多数の微細孔を形成する工程、前記微細孔から半導体のみをエッチングし、前記第1の絶縁膜下に空洞を形成する工程、前記微細孔形成した第1の絶縁膜上に更に第2の絶縁膜を形成する工程、前記第2の絶縁膜上に導電体薄膜配線を形成する工程とを備えてなる配線基板の製造方法。 1. A process of forming a first insulating film on one main surface of the semiconductor substrate, forming a plurality of micropores in said first insulating film, only the semiconductor by etching from the micropores, the first forming a cavity under the first insulating film, the step of forming the micropore forming the first addition on the insulating film a second insulating film to form a conductive thin film wiring on the second insulating film a method for manufacturing a wiring board comprising a step.
  2. 【請求項2】第1の絶縁膜にシリコンの熱酸化膜、あるいはCVD法等により形成される酸化珪素膜、窒化珪素膜等の無機膜、あるいはポリイミド膜等の有機膜を用い、前記第2の絶縁膜にCVD法等により形成される酸化珪素膜、窒化珪素膜等の無機膜、あるいはポリイミド膜等の有機膜を用いることを特徴とする請求項1記載の配線基板の製造方法。 2. A thermal oxide film of silicon on the first insulating film or a silicon oxide film formed by a CVD method or the like, an inorganic film or an organic film such as a polyimide film, such as a silicon nitride film, the second insulating film a silicon oxide film formed by a CVD method or the like, a manufacturing method of a wiring board according to claim 1, characterized by using an inorganic film or an organic film such as a polyimide film, such as a silicon nitride film.
  3. 【請求項3】半導体がシリコンよりなり、シリコンのエッチングは、第1の酸化膜に形成した多数の微細孔を通しての水酸化カリウム混液、またはフッ硝酸混液を用いたウエットエッチング法を用いることを特徴とする請求項1記載の配線基板の形成方法。 3. A semiconductor is silicon, the etching of silicon, potassium hydroxide mixture through a large number of fine holes formed in the first oxide film or characterized by using wet etching method using hydrofluoric-nitric acid mixture, method for forming a wiring board according to claim 1,.
JP24548091A 1991-09-25 1991-09-25 A method for manufacturing a wiring board Expired - Fee Related JP2871222B2 (en)

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JP24548091A JP2871222B2 (en) 1991-09-25 1991-09-25 A method for manufacturing a wiring board

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229216B1 (en) * 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229216B1 (en) * 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6562653B1 (en) 1999-01-11 2003-05-13 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias

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