JPH0581427A - Frequency distribution calculating device - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by providing a prescribed number of calculating means which count data classified by a classifying means in accordance with the discrimination result of a discriminating means. CONSTITUTION:m-bit digital data is classified to 6 kinds of area. (n) m-bit digital data are provided in total and are inputted from a data input terminal 1 in order synchronously with a clock signal. That is, one m-bit digital data is inputted per clock. The average value of (n) m-bit digital data is preliminarily obtained and is inputted from an average value input terminal 8. (n) m-bit digital data have a form symmetrical with the average value of Gaussian distribution or the like as the cener. Counters 4-1 to 4-3 are counted up by one per clock synchronously with the clock signal in the same manner as m-bit digital data. Thus, the result from classification of (n) m-bit digital data to 6 kinds of area is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency distribution calculating apparatus for calculating a frequency distribution of a plurality of data applicable to image processing and the like.

[0002]

2. Description of the Related Art Generally, a frequency distribution calculation device is used in image processing of a digital copying machine or the like when examining statistical properties such as a distribution shape of pixel values. Conventionally, as such a frequency distribution calculating device, there has been disclosed in JP-A-63-18871.
A circuit as described in Japanese Patent No. 6 has been proposed. This circuit is as shown in FIG. The one shown in FIG. 2 inputs n m-bit digital data,
This is a frequency distribution calculation device that classifies these data into six types of regions as shown in FIG. In the figure, 1 is a data input terminal for inputting m-bit digital data, 2-1 to 2-5 are comparators for comparing m-bit digital data, and 3-1 to 3-6 are exclusive of digital data. XOR gate for logical OR operation, 4-1
4-6 is a counter having a data width capable of counting n, 5-1-5-6 is a data output terminal for outputting the frequency of each area, 6 is a reset input terminal, and 7-1-7-5
Is a register that stores the boundary value of each area.

In the circuit of FIG. 2, a total of n pieces of m-bit digital data are sequentially input from the data input terminal 1 in synchronization with a clock signal (not shown). That is, one m-bit digital data is input for each clock. The counters 4-1 to 4-6 are also synchronized with the clock signal and can count up by 1 every clock.

Next, taking the case where these m-bit digital data are classified into the six types of regions in FIG.
The operation of the circuit of FIG. 2 will be described. Here, FIG. 3 (a)
Is a graph showing frequencies when n pieces of m-bit digital data in the conventional example are classified into 6 types of areas,
~ Represents each area, and r0 to r4 represent boundary values of these areas. In the circuit of FIG. 2, first, the reset input terminal 6 is reset to reset all the counters 4-1 to 4-6 to 0, and then the m-bit digital data is sequentially input from the data input terminal 1 one by one. As one input of each comparator 2-1 to 2-5. At this time, the other input terminal of the comparators 2-1 to 2-5 has m bits stored in the registers 7-1 to 7-5. Boundary values r0 to r4 of each area represented by are input in order from the smallest value. In this example, register 7-1 is r0, register 7-2 is r1, register 7-3 is r2, register 7-4.
In the register 7 and r4 in the register 7-5. This boundary value is compared with the m-bit digital data input by these comparators 2-1 to 2-5. In the comparators 2-1 to 2-5, when A> B, that is, when the data input to the comparator is larger than the input boundary value, the logic “1” is set. When the data input to the comparator is smaller than the input boundary value, the logic “0” is set. Is output. An enable signal is generated by the XORs 3-1 to 3-6 based on the comparison result of the comparators 2-1 to 2-5. Since the outputs of the adjacent comparators are input to the two input terminals of XOR3-1 to 3-6,
Only when the outputs of these comparators are different, i.e.
An enable signal of logic "1" is generated from the XOR circuit only when the data input to one comparator is smaller than the boundary value and the other comparator input is larger than the boundary value. This generated enable signal enables only the counter of the area to which the m-bit digital data belongs, and the counter is incremented, and the counters 4-1 to 4-6 respectively count the frequencies of the area to. Become. In this way, after all n pieces of m-bit digital data have been input, the frequency of each area is output from the data outputs 5-1 to 5-6.

The operation of the counter will now be described in more detail. For example, assume that one input m-bit digital data belongs to a region. At this time, since the m-bit digital data is larger than r0 to r2, that is, the values of the registers 7-1 to 7-3,
The outputs of the comparators 2-1 to 2-3 are logic "1". In addition, m-bit digital data is r3 to r4,
That is, since it is smaller than the values of the registers 7-4-7-5, the outputs of the comparators 2-4-2-5 are logic "0". Therefore, the outputs of the XOR gates 3-1 to 3-6 are
Only the XOR gates 3-4 having two different input values have the logic "1", and the other two input values have the same XOR gates 3-1 to 3-1.
All of 3-3, 3-4-3-5 are logic "0". Further, the outputs of the XOR gates 3-1 to 3-6 are input to the enable terminals of the counters 4-1 to 4-6, and only the counter 4-4 corresponding to the area where the enable signal becomes the logic "1" is generated. It is counted up.

In this way, n pieces of m-bit digital data are sequentially input, and the counters 4-1 to 4-6 sequentially count up the counters corresponding to the respective areas to obtain the frequency of each area. The result is output from the data output terminals 5-1 to 5-6.

[0007]

However, in the prior art, as shown in FIG. 2, (comparator number-1) comparators and (counter region) counters are required to compare m-bit digital data. There is a problem that the circuit scale becomes large.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a frequency distribution device having a smaller circuit scale than the conventional one.

[0009]

Generally, in the case of obtaining a distribution of image values such as photographs in an image processing apparatus or the like, the distribution shape often has a symmetrical distribution shape around an average value such as a Gaussian distribution. .. Further, in an image processing apparatus or the like, the average value is often obtained in advance because various image processes are performed using the average value.

Therefore, according to the present invention, the average value of n m-bit digital data is known in advance, and n m
It is applied when it is known that the distribution of bit digital data is a symmetrical distribution around the average value.
That is, this is a case where the distribution is a symmetrical distribution centered on the average value, such as a normal distribution or a binomial distribution. When classifying n pieces of m-bit digital data into k types of areas, the average value is subtracted from the m-bit digital data first. This data is called average value separation data. Among the average value separation data thus obtained, the frequency for the k / 2 type area is obtained only for either the positive or negative sign.

[0011]

According to the present invention, either the area in the range larger than the average value or the area in the range smaller than the average value k
The frequency is obtained for / 2 types of regions, and it is not directly obtained. Either the region of the range smaller than the average value or the region of the range larger than the average value is calculated for the k / 2 type region. The frequency uses the symmetry of the distribution with respect to the mean value,
Determine based on the obtained frequency. By this,
The result of classifying n pieces of m-bit digital data into k kinds of areas is obtained. As described above, the circuit scale can be reduced by obtaining the frequencies only in the k / 2 types of regions.

[0012]

FIG. 1 shows a circuit showing an embodiment of the present invention. In the figure, 1 is a data input terminal for inputting m-bit digital data, 2-1 to 2-2 is a comparator for comparing m-bit digital data, and 3-1 to 3-2.
-3 is an XO that performs an exclusive OR operation of digital data
R gate, 4-1 to 4-3 is a counter having a data width capable of counting n, 5-1 to 5-3 is a data output terminal for outputting the frequency of each area, 6 is a reset input terminal, 7- 1 to 7-2 are registers for storing the boundary value of each area, 8 is an average value input terminal for inputting an average value represented by m bits, and 9 is a subtracter for subtracting the average value from m-bit digital data. 10 is an inverter, 11-1 to 11
11-3 is an AND gate for generating an enable signal.

The circuit shown in FIG. 1 is a frequency distribution calculation device for classifying m-bit digital data into six types of regions. There are a total of n pieces of m-bit digital data, which are sequentially input from the data input terminal 1 in synchronization with a clock signal (not shown). That is, m-bit digital data is 1
One is input for each clock. Further, the average value of n pieces of m-bit digital data has been obtained in advance and is input from the average value input terminal 8. Furthermore, n pieces of m-bit digital data are assumed to have a symmetrical shape centered on an average value such as a Gaussian distribution. Also, the counter 4
-1 to 4-3 are also synchronized with the clock signal like the m-bit digital data, and can count up by 1 every clock.

First, the principle of this circuit will be described with reference to FIG. FIG. 3A is a graph showing the frequency when n pieces of m-bit digital data are classified into 6 types of areas in the present embodiment. In FIG. 3 (a),-represents each region, and r0-r4
Indicates the boundary value of each region. Then, this distribution has a symmetrical shape centered on the average value as described above. Here, when the average value is subtracted from each of the n m-bit digital data to obtain the average value separated data,
FIG. 3B is a graph showing the distribution of the average value separation data. In FIG. 3 (b),
3 to 4 respectively represent areas corresponding to the areas having the same numbers in FIG. 3A, and rm0 to rm4 represent boundary values of these areas. This graph is shown in FIG.
It can be seen that the position of the average value of the graph is set to 0 on the horizontal axis. In addition, this graph is symmetric with respect to the vertical axis, and the frequency of the area ,,, is calculated, and the frequency of the area ,,, is set to the same value as the frequency of the area The overall distribution can be obtained without obtaining. In the present invention, after the average value is subtracted from the m-bit digital data in this way, the entire distribution is obtained by obtaining only the frequencies of the areas, and with respect to the average value separated data.

Next, the operation of this circuit will be described with reference to FIG. This circuit first resets the counters 4-1 to 4-3 to 0 by resetting from the reset input terminal 6, and then sequentially inputs m-bit digital data from the data input terminal 1 one by one. The average value input from the average value input terminal 8 is subtracted from the m-bit digital data input here by the subtractor 9, and m +
The average value separation data is represented by a 1-bit signed number. The m + 1-bit average value separation data is further divided into an upper 1-bit sign bit indicating positive or negative and a lower m-bit. The sign bits are AND gates 11-1 to 11-1 that generate an enable signal through the inverter 10.
It becomes one input of 11-3. The sign bit is such that the output of the inverter 10 becomes "0" or "1" when the average value separation data has a negative or positive sign. Therefore, when the m + 1-bit average value separation data has a negative sign, AND gates 11-1 to 11-11
Since the input on one side of the counter -3 is always logic "0", the enable inputs of the counters 4-1 to 4-3 are all logic "0" and the counters 4-1 to 4-3 are not counted up. On the other hand, when the m + 1-bit average value separation data has a positive sign, the inputs on one side of the AND gates 11-1 to 11-3 are always logic "1", so the counters 4-1 to 4-4
The output values of the XOR gates 3-1 to 3-3 are directly input to the enable inputs of the -3. Therefore, this circuit operates only when the value of the average value separation data is positive. This means that the counters 4-1 to 4-1 can be used only when the average value separation data is in the range of ,, in FIG. 3B.
This is equivalent to operating -3. Therefore, hereinafter, the case where the value of the average value separation data is positive will be described.

When the value of the average value separation data is positive, m +
Of the 1-bit signed average value separated data, the lower m bits are the average value separated data represented by an m-bit unsigned number. The m-bit average value separation data is input to one of the inputs of the comparators 2-1 to 2-2. Here, the registers 7-1 and -7 have rms shown in FIG.
3 and rm4 are stored. That is, the other one side of the inputs of the comparators 2-1 to 2-2 is set in order from the register 7-1 to -7 in order of decreasing boundary value of each area. Is compared with the m-bit average value separation data.
Here, the counters 4-1, 4-2, and 4-3 respectively count the frequencies of the areas ,. At this time, the enable signals generated by the XORs 3-1 to 3-3 based on the comparison results of the comparators 2-1 to 2-2,
By enabling only the counter of the area to which the m-bit average value separated data belongs, only that counter is incremented. In this way, after all n pieces of m-bit digital data are input, the data output 5-1
The frequency of the region 5-3 is output.

The operation of the counter will now be described in more detail. For example, the m-bit average value separation data is
Suppose you belonged to a region. At this time, the m-bit average value separated data is rm3, that is, the register 7-1.
Since it is larger than the boundary value with the area stored in, the output of the comparator 2-1 becomes logic "1". Further, since the m-bit average value separation data is smaller than rm4, that is, the boundary value with the area stored in the register 7-2, the output of the comparator 2-2 is logical "0".
Therefore, the outputs of the XOR gates 3-1 to 3-3 are logic "1" when the XOR gates 3-2 having different two input values have a logic "1", and the XOR gates 3-1 and 3-2 having the same two input values. 3 becomes a logic "0". Here, as described above, since the sign bit is a logic "0", the AND gate 11-1
11-11 transmits the output values of the XOR gates 3-1 to 3-3 as they are to the enable inputs of the counters 4-1 to 4-3, and the counter 4 corresponding to the area where the enable signal becomes the logic "1". Only -2 is counted up.

In this way, n pieces of m-bit digital data are sequentially input, and the count of each area is counted up by the counters 4-1 to 4-3 only when the average value separation data has a positive sign. To be done. Then, after all of these n pieces of data have been input, the frequency of the area is obtained from the data output terminal 5-1, the frequency of the area is obtained from the data output terminal 5-2, and the frequency of the area is obtained from the data output terminal 5-3. Furthermore, using the symmetry of the distribution,
The frequency distribution of FIG. 3B is obtained by setting the frequency of, and the same value as the frequency of the area and.

[0019]

As described above, according to the present invention, the average value is subtracted from each of n pieces of data having a symmetrical distribution shape around the average value to obtain average value separation data, and then this average value is calculated. Since the entire distribution is obtained by obtaining the frequency distribution on the positive side or the negative side of the value separation data, a subtracter, an inverter, and an AND gate are added as compared with the conventional one, but these The number of comparators and counters having a larger circuit scale than the circuit can be halved, and the overall circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is a diagram for explaining frequency distribution calculation.

[Explanation of symbols]

1 ... Data input terminal, 2-1 to 2-5 ... Comparator,
3-1 to 3-6 ... XOR gate, 4-1 to 4-6 ... Counter, 5-1 to 5-3 ... Data output terminal, 6 ... Reset input terminal, 7-1 to 7-5 ... Registers for storing boundary values, 8 ... Average value input terminal, 9 ... Subtractor, 10 ... Inverter, 11-1 to 11-3 ... AND gate.

Claims (1)

[Claims] 1. One digital data is m bits,
N whose average value is known and whose distribution is symmetric
In a frequency distribution calculation device for classifying each piece of digital data into k or less regions, subtraction means for subtracting the average value from the digital data, and the subtraction result are compared with a plurality of threshold values to classify into k / 2 kinds. For determining the magnitude relationship between the digital data and the average value, and k / 2 counting means for counting the data classified by the classifying means according to the judgment result of the judging means. A frequency distribution calculation device comprising: