JPH0578977B2 - - Google Patents

Info

Publication number
JPH0578977B2
JPH0578977B2 JP58055439A JP5543983A JPH0578977B2 JP H0578977 B2 JPH0578977 B2 JP H0578977B2 JP 58055439 A JP58055439 A JP 58055439A JP 5543983 A JP5543983 A JP 5543983A JP H0578977 B2 JPH0578977 B2 JP H0578977B2
Authority
JP
Japan
Prior art keywords
priority
station
communication
communication system
priority information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58055439A
Other languages
Japanese (ja)
Other versions
JPS59181844A (en
Inventor
Hiroshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58055439A priority Critical patent/JPS59181844A/en
Priority to DE8383112151T priority patent/DE3382313D1/en
Priority to CA000442460A priority patent/CA1201784A/en
Priority to EP83112151A priority patent/EP0111277B1/en
Publication of JPS59181844A publication Critical patent/JPS59181844A/en
Priority to US06/824,035 priority patent/US4627051A/en
Publication of JPH0578977B2 publication Critical patent/JPH0578977B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42Loop networks
    • H04L12/427Loop networks with decentralised control
    • H04L12/433Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Description

【発明の詳細な説明】 本発明は分散制御型通信システムの優先情報制
御回路に関する。分散制御型通信システムは、信
頼性,経済性の面で優れた特徴を有しており、ロ
ーカルエリアネツトワーク等に導入されている。
かかる通信システムにおいては、音声などのよう
な連続的な同期通信とバースト的な非同期通信を
統合するための制御方法の1つとして優先制御が
採用されている。即ち、同期通信に対し高い優先
度を与えて同期性を保証しようとするものであ
る。このような制御方法を採用した通信システム
としては、例えば、特願番号昭57−212364:「ル
ープ式通信システム」がある。このシステムを例
にして優先権通信の説明を行なう。第1図にこの
システムの構成を示す。第1図の通信システムに
おいてはクロツクステーシヨン1と複数のノード
ステーシヨン3,4,5,6,7が一方向に信号
を伝送するループ2により接続されている。クロ
ツクステーシヨン1は、第2図に示すように一定
周期To毎に最も優先度の高い通信を起動する信
号P1を送出する。信号P1の与える優先度を有
するノードステーシヨン3,5,7は第2図に示
すように信号ブロツクB3,B5,B7を送出す
る。クロツクステーシヨン1は次に送信権を握る
とP1の次に高い優先度を有する通信を起動する
信号P2を送出し、ノードステーシヨン2,6が
信号ブロツクB2,B6を送出する。以下同様に
して、信号P3により、更に低い優先度の通信が
起動される。従つて、最優先度通信は周期Toで
他の通信に先立つて起動されるので同期通信を収
容することが可能となる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a priority information control circuit for a distributed control communication system. Distributed control communication systems have excellent characteristics in terms of reliability and economy, and have been introduced into local area networks and the like.
In such communication systems, priority control is employed as one of the control methods for integrating continuous synchronous communication such as voice and burst asynchronous communication. That is, it attempts to guarantee synchronization by giving high priority to synchronous communication. As a communication system employing such a control method, there is, for example, Japanese Patent Application No. 57-212364: ``Loop Type Communication System''. Priority communication will be explained using this system as an example. Figure 1 shows the configuration of this system. In the communication system shown in FIG. 1, a clock station 1 and a plurality of node stations 3, 4, 5, 6, and 7 are connected by a loop 2 that transmits signals in one direction. As shown in FIG. 2, the clock station 1 sends out a signal P1 at regular intervals To to activate communication with the highest priority. Node stations 3, 5, 7 having the priority given by signal P1 send out signal blocks B3, B5, B7 as shown in FIG. When clock station 1 then takes the right to transmit, it sends out a signal P2 which activates a communication having the next highest priority after P1, and node stations 2 and 6 send out signal blocks B2 and B6. Similarly, communication with a lower priority is activated by the signal P3. Therefore, since the highest priority communication is activated prior to other communication at the period To, it is possible to accommodate synchronous communication.

第3図に優先情報を有する信号ブロツクの基本
構成を示す。各信号ブロツクは、プリアンブル
PR,開始フラグSF,同期信号ビツトSY,優先
フイールドPI,あて先アドレスDA,発信者アド
レスSA,情報I及び終了フラグEFとから構成さ
れており、優先情報はPIフイールドに書きこま
れている。各ノードステーシヨンはクロツクステ
ーシヨン1の信号ブロツクの優先フイールドPI
を監視しそれに応じた優先度の通信を行なう。
FIG. 3 shows the basic structure of a signal block having priority information. Each signal block has a preamble
It consists of PR, start flag SF, synchronization signal bit SY, priority field PI, destination address DA, sender address SA, information I, and end flag EF, and the priority information is written in the PI field. Each node station inputs the priority field PI of the clock station 1 signal block.
monitor and perform communication with priority accordingly.

しかしながら、ループ2上での符号誤りによ
り、優先フイールドPIに誤りが生じた場合、優
先度の低い通信が高い通信より先に起動されるこ
とが生じ、同期通信に対する同期性の保証を損な
うことになる。
However, if an error occurs in the priority field PI due to a code error on loop 2, lower-priority communications may be activated before higher-priority communications, which may impair synchronicity guarantees for synchronous communications. Become.

本発明の目的は、ワンシヨツト的な符号誤りが
生じても、優先制御に誤りが生じない優先情報制
御回路を提供し、分散制御による通信の信頼性を
高めることにある。本発明は、各ステーシヨン間
通信の優先度を通信される信号フレーム内の優先
度情報によつて相互に認識し、自己の送信要求の
優先度が認識された優先度と同じあるいは高い場
合に送信制御を開始する分散制御型通信システム
におけるステーシヨンの優先情報制御回路におい
て、送信部は、信号フレームの優先度情報フイー
ルドに該ステーシヨンが認識している優先度を複
数個書き込む優先情報送出回路を備え、受信部
は、受信された複数個の優先情報を互いに比較
し、最も優先度の高いものを比較結果として出力
する優先度比較回路と、前記比較結果を該通信シ
ステムの優先度と認識する優先度設定回路とを備
えることを特徴とする分散制御型通信システムに
おけるステーシヨンの優先情報制御回路である。
An object of the present invention is to provide a priority information control circuit that does not cause errors in priority control even if a one-shot code error occurs, and to improve the reliability of communication through distributed control. The present invention mutually recognizes the priority of communication between each station based on priority information in the signal frame communicated, and transmits when the priority of its own transmission request is the same as or higher than the recognized priority. In a priority information control circuit for a station in a distributed control communication system that starts control, the transmitter includes a priority information sending circuit that writes a plurality of priorities recognized by the station in a priority information field of a signal frame, The receiving unit includes a priority comparison circuit that compares the received priority information with each other and outputs the one with the highest priority as a comparison result, and a priority that recognizes the comparison result as the priority of the communication system. 1 is a priority information control circuit for a station in a distributed control communication system characterized by comprising a setting circuit;

第4図に本発明における信号ブロツクのPIフ
イールドを示す。このPIフイールドはPIA,PIB
の2つに分割され、クロツクステーシヨン1を含
む各ステーシヨンは、送信時にはPIA,PIBに同
一優先情報を書き込んで送出する。一方、各ノー
ドステーシヨンはループ2を伝搬する信号ブロツ
クのPIフイールドを監視し、PIAとPIBとが同じ
場合はこれらが示す優先度をその時の通信フエー
ズの優先度と認識し、PIAとPIBとが異なる場合
は、高い方の優先度をその時の通信フエーズと認
識する。従つて、PIフイールドに1ビツトの符
号誤りが生じても、送信ステーシヨンが送出しに
信号ブロツクの優先度よりも低い優先度の通信フ
エーズになることはない。
FIG. 4 shows the PI field of the signal block in the present invention. This PI field is PIA, PIB
Each station, including clock station 1, writes the same priority information into PIA and PIB and sends them out. On the other hand, each node station monitors the PI field of the signal block propagating through loop 2, and if PIA and PIB are the same, the priority indicated by these is recognized as the priority of the communication phase at that time, and PIA and PIB are If they are different, the higher priority is recognized as the communication phase at that time. Therefore, even if a single bit error occurs in the PI field, the transmitting station will not send a communication phase with a lower priority than the signal block.

第5図に各ステーシヨンの伝送路インタフエイ
ス部における本発明の第1の実施例を示す。な
お、説明を簡単にするために、アクセス制御部は
省略している。
FIG. 5 shows a first embodiment of the present invention in the transmission line interface section of each station. Note that, to simplify the explanation, the access control unit is omitted.

送信時にあつては、スイツチ12を送信レジス
タ15側にセツトし、送信バツフア17内の信号
ブロツクをループ2上の出力端子11に送出す
る。このとき、信号ブロツクのPIフイールドに
は優先度レジスタ16に格納されている優先情報
が、PIA及びPIBとして2回送信レジスタ15に
書きこまれる。受信時にあつては、スイツチ12
はレピータ13側にセツトされ、入力端子10の
信号は再生後バイパスされて出力端子11に供給
される。入力端子11より供給される信号ブロツ
クは受信レジスタ14に入力され、PIフイルー
ドのPIA及びPIBは、優先度比較回路18に供給
される。優先度比較回路18は、PIAとPIBとを
比較し高い方の優先度を優先度設定回路19に送
出し、優先度設定回路19はこの高い方の優先度
情報により、その時の通信フエーズの優先度を設
定する。
At the time of transmission, switch 12 is set to the transmission register 15 side, and the signal block in transmission buffer 17 is sent to output terminal 11 on loop 2. At this time, the priority information stored in the priority register 16 in the PI field of the signal block is written into the transmission register 15 twice as PIA and PIB. When receiving, switch 12
is set on the repeater 13 side, and the signal at the input terminal 10 is bypassed after being reproduced and supplied to the output terminal 11. The signal block supplied from the input terminal 11 is input to the reception register 14, and the PI fields PIA and PIB are supplied to the priority comparison circuit 18. The priority comparison circuit 18 compares PIA and PIB and sends the higher priority to the priority setting circuit 19, and the priority setting circuit 19 uses this higher priority information to determine the priority of the communication phase at that time. Set the degree.

なお、この優先情報制御回路は、前記引用例に
おけるアクセス方式固有のものではなく、例え
ば、優先制御付トークンリングにおいても適用で
きる。また、ループ(あるいはリング)状の通信
システムばかりでなく、他の形状の分散型通信シ
ステムにも適用できる。バス構成の通信システム
における本発明の第2の実施例を第6図に示す。
本実施例においては、送信レジスタ15からの信
号ブロツクはドライバ21を介しバス20に送出
され、バス20上の信号はレシーバ22を介し受
信レジスタ14に供給される。
Note that this priority information control circuit is not unique to the access method in the cited example, but can also be applied to, for example, a token ring with priority control. Furthermore, it is applicable not only to loop (or ring) communication systems but also to other forms of distributed communication systems. A second embodiment of the present invention in a communication system having a bus configuration is shown in FIG.
In this embodiment, the signal block from transmit register 15 is sent to bus 20 via driver 21, and the signal on bus 20 is provided to receive register 14 via receiver 22.

このように本発明によれば、PIフイールドに
誤りが生じても、各ノードステーシヨンはPIA,
PIBのうち高い方の優先度をその時の通信フエー
ズの優先度として認識するので、送信ステーシヨ
ンが設定した優先度よりも低い優先度の通信フエ
ーズになる確率は極めて小さく、高い信頼性を有
する通信を提供でき、特に同期通信に対する同期
性をより確実にすることができる。
According to the present invention, even if an error occurs in the PI field, each node station can
Since the higher priority of the PIB is recognized as the priority of the communication phase at that time, the probability that the communication phase will have a lower priority than the priority set by the transmitting station is extremely small, ensuring highly reliable communication. In particular, synchronization for synchronous communication can be more ensured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はループ状通信システムを示す図、第2
図はループ上の信号ブロツク図、第3図は、信号
ブロツクの構成を示す図、第4図は本発明による
PIフイルードの構成を示す図、第5図,第6図
はそれぞれ本発明の第1,第2の実施例を示すブ
ロツク図である。第6図において、1はクロツク
ステーシヨン、2,3,4,5,6,7はノード
ステーシヨン、14,15,16はレジスタ、1
7は送信バツフア、18は優先度比較回路、19
は優先度設定回路、20はバス、21はドライ
バ、22はレシーバ、13はリピータを示す。
Figure 1 is a diagram showing a loop communication system, Figure 2 is a diagram showing a loop communication system.
The figure shows the signal block diagram on the loop, Figure 3 shows the configuration of the signal block, and Figure 4 shows the structure of the signal block according to the present invention.
Figures 5 and 6 showing the structure of the PI field are block diagrams showing the first and second embodiments of the present invention, respectively. In FIG. 6, 1 is a clock station, 2, 3, 4, 5, 6, 7 are node stations, 14, 15, 16 are registers, 1
7 is a transmission buffer, 18 is a priority comparison circuit, 19
2 shows a priority setting circuit, 20 a bus, 21 a driver, 22 a receiver, and 13 a repeater.

Claims (1)

【特許請求の範囲】 1 各ステーシヨン間通信の優先度を通信される
信号フレーム内の優先度情報によつて相互に認識
し、自己の送信要求の優先度が認識された優先度
と同じあるいは高い場合に送信制御を開始する分
散制御型通信システムにおけるステーシヨンの優
先情報制御回路において、 送信部は、信号フレームの優先度情報フイール
ドに該ステーシヨンが認識している優先度を複数
個書き込む優先情報送出回路を備え、 受信部は、受信された複数個の優先情報を互い
に比較し、最も優先度の高いものを比較結果とし
て出力する優先度比較回路と、前記比較結果を該
通信システムの優先度と認識する優先度設定回路
とを備えることを特徴とする分散制御型通信シス
テムにおけるステーシヨンの優先情報制御回路。
[Claims] 1. The priority of communication between each station is mutually recognized based on the priority information in the signal frame being communicated, and the priority of the own transmission request is the same as or higher than the recognized priority. In the priority information control circuit of a station in a distributed control communication system that starts transmission control when The receiving unit includes a priority comparison circuit that compares the plural pieces of received priority information with each other and outputs the one with the highest priority as a comparison result, and recognizes the comparison result as the priority of the communication system. A priority information control circuit for a station in a distributed control communication system, comprising: a priority setting circuit for controlling a station;
JP58055439A 1982-12-03 1983-03-31 Priority information control circuit in decentralized control type communication system Granted JPS59181844A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP58055439A JPS59181844A (en) 1983-03-31 1983-03-31 Priority information control circuit in decentralized control type communication system
DE8383112151T DE3382313D1 (en) 1982-12-03 1983-12-02 RING NETWORK CONTROLLED BY A SIMPLE CLOCK STATION.
CA000442460A CA1201784A (en) 1982-12-03 1983-12-02 Loop network system controlled by a simple clock station
EP83112151A EP0111277B1 (en) 1982-12-03 1983-12-02 Loop network system controlled by a simple clock station
US06/824,035 US4627051A (en) 1982-12-03 1986-01-30 Loop network system controlled by a simple clock station

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58055439A JPS59181844A (en) 1983-03-31 1983-03-31 Priority information control circuit in decentralized control type communication system

Publications (2)

Publication Number Publication Date
JPS59181844A JPS59181844A (en) 1984-10-16
JPH0578977B2 true JPH0578977B2 (en) 1993-10-29

Family

ID=12998621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58055439A Granted JPS59181844A (en) 1982-12-03 1983-03-31 Priority information control circuit in decentralized control type communication system

Country Status (1)

Country Link
JP (1) JPS59181844A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263349A (en) * 1985-05-17 1986-11-21 Yamatake Honeywell Co Ltd Sending previlege takeover system in data transmission

Also Published As

Publication number Publication date
JPS59181844A (en) 1984-10-16

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