JPH0571410A - Electronic control unit for vehicle - Google Patents

Abstract

PURPOSE:To check a corresponding CPU for malfunction among several microcomputers to perform data communication by constructing an electronic control unit for a vehicle to perform data communication in synchronization with the rotation of an engine. CONSTITUTION:The second microcomputer 21T provided with a watch dog timer 88 has output signals sent to a general receiver port 12Q in the first microcomputer 11T via a general sender port 22p. In the case that a malfunction signaling means 63A on the first microcomputer 11T side detects the malfunction of the second microcomputer 21T using the output signal of the watch dog timer 88, an LED 12L and a lamp 12M are energized to display the malfunction of the second microcomputer 21T.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vehicle electronic control device, and more particularly to a vehicle electronic control device having a plurality of microcomputers, in which various data communication is performed directly between the microcomputers. It relates to the device.

[0002]

2. Description of the Related Art An engine ignition timing control for an automobile, a motorcycle, etc. (hereinafter referred to as a vehicle), a fuel injection control using an injector, and the like are performed by using an electronic control unit equipped with a microcomputer. Also,
In recent years, knocking control (vehicle control for preventing knocking) has come to be performed, and various knocking detection methods therefor have been proposed.

By the way, since this knocking detection requires a relatively complicated process, a microcomputer other than the microcomputer for performing the ignition timing control, the fuel injection control and the like as described above may be used. is there. In each of these microcomputers, it is necessary to calculate various data using the data output or calculated by the other microcomputer. Therefore, data communication is performed between the microcomputers.

Therefore, conventionally, as shown in FIG. 19, a communication line 3 for transmitting / receiving 1-bit data between a plurality of microcomputers (between the first and second microcomputers 1 and 2). For parallel communication by providing the number of bits required for communication, or, as shown in FIG. 20, two communication lines 4 for data transmission and reception are provided, and the transmission end of each line 4 and The serial port 5 is provided at the receiving end to perform serial communication using the reference clock in each microcomputer.

By the way, the parallel communication as shown in FIG. 19 has the following drawbacks. (A) As the number of data to be communicated increases, the number of communication lines increases accordingly, so that the configuration of the vehicle electronic control device becomes large and complicated, and the manufacturing cost increases. (B) As the number of communication lines increases, the probability of failure of the vehicle electronic control unit increases, which may reduce reliability.

The serial communication as shown in FIG. 20 also has the following drawbacks. (C) A serial port is required for data transmission and reception, and the electronic control unit for the vehicle becomes large. (D) When the data transmission / reception destinations span multiple destinations, a serial port must be added or a switching circuit is required, so the configuration of the vehicle electronic control device is more complicated,
To become larger. (E) The data communication is performed in synchronization with the clock of the microcomputer, so the data communication in synchronization with the rotation of the engine cannot be performed. That is, in controlling the vehicle, it is necessary to control various control devices (for example, ignition timing control, fuel injection control, knocking control, etc.) according to the engine speed, but data communication in synchronization with the engine speed can be performed. Without it, the various control devices cannot be controlled accurately.

In order to solve the above problems,
The applicant of the present application, in Japanese Patent Application No. 1-287881, discloses a vehicle electronic device capable of performing serial data communication between a plurality of microcomputers without requiring a special serial port and in synchronization with engine rotation. The control device has already been proposed. Specifically, this vehicle electronic control unit is provided with a general-purpose transmission port and a general-purpose reception port in each of a plurality of microcomputers that configure the vehicle electronic control unit, and the transmission port and the reception port are provided from the transmission port according to the crankshaft rotation angle. Data is transmitted bit by bit according to the crankshaft rotation angle from the reception port, and data is transmitted and received from one microcomputer that transmits and receives data. The other microcomputer for receiving the data receives the data by shifting the timing, that is, with the phase difference.

[0008]

In the technique disclosed in the above-mentioned application, each of the CPUs among the plurality of microcomputers constituting the vehicle electronic control device is
Alternatively, there is no disclosure of a technique for checking an abnormality in a transmission or reception port or the like, or noise superposition of data.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a vehicle electronic control device configured to perform data communication in synchronization with rotation of an engine. An object of the present invention is to provide an electronic control unit for a vehicle that can check abnormality of each CPU, transmission or reception ports, or noise superposition of data among a plurality of microcomputers that perform communication.

[0010]

In order to solve the above-mentioned problems, the present invention uses at least one microcomputer constituting the electronic control unit for a vehicle to use data to be transmitted and to parity the data. A feature is that a frame data creating means for adding a parity bit for checking to create frame data is provided, and the parity bit is detected from the received frame data on at least another microcomputer side.

Further, at least one microcomputer is provided with a watchdog timer and a general-purpose transmission port for watchdog output transmission for transmitting an output signal of the watchdog timer, and at least another microcomputer is provided with the watchdog timer. Another feature is that a general purpose reception port for watchdog output reception connected to the general purpose transmission port for output transmission is provided.

Further, another feature is that the frame data to be transmitted from the data transmitting means is temporarily stored in a buffer, and the data in the buffer is output bit by bit according to the crankshaft rotation angle. is there.

Furthermore, when an abnormality is detected from the parity bit or the watchdog output, the fact is displayed.

[0014]

Since the transmitting side transmits the frame data to which the parity bit for the parity check is added and the receiving side detects the parity bit, the transmitting side microcomputer or the transmission line of the data is abnormal, or noise is mixed. , The data receiving side can be detected by the microcomputer.

Similarly, since the output signal of the watchdog timer is transmitted from the data transmission side microcomputer to the data reception side microcomputer, the data reception side microcomputer can detect an abnormality in the transmission side microcomputer. it can.

Further, if the frame data to be transmitted is temporarily stored in the buffer, the data transmission according to the crankshaft rotation angle can be performed only by reading the data from the buffer.

Furthermore, if the above-mentioned abnormality is detected and displayed, the location of the abnormality in the vehicle electronic control unit (that is, the microcomputer in which the abnormality has occurred, or the port, communication line, etc.) is displayed. Can be specified.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 3 is a block diagram of the first embodiment of the present invention. In the figure, according to the engine rotation of the vehicle,
Cylinder pulse and TDC extracted by a known method
The pulse and the crank pulse are input to the first microcomputer 11 via the waveform shaping circuit 31.

Assuming that the engine is a 4-cylinder 4-cycle engine, the cylinder pulse outputs one pulse every time the crankshaft makes two revolutions (720 degrees), and the TDC pulse causes the piston of each cylinder to reach the top dead center. 1 pulse output for each, that is, 4 pulse output for every 2 revolutions of the crankshaft, and the crank pulse is T in this example.
Six pulses are output each time one DC pulse is output. The cylinder pulse and the crank pulse are also input to the second microcomputer 21 described later.

The first microcomputer 11 performs main control of the vehicle, for example, ignition timing control, fuel injection control, etc., and includes a CPU 12 (hereinafter referred to as a main CPU).
12), a ROM, a RAM, an input / output interface, etc. (none of which are shown). A Pba sensor 32 that detects the negative pressure (absolute pressure) Pba in the intake pipe, a Tw sensor 33 that detects the engine cooling water temperature Tw, a Pa sensor 34 that detects the atmospheric pressure Pa, a Th sensor 35 that detects the throttle valve opening, etc. Is connected to the first microcomputer 11 via the A / D converter 37. The first microcomputer 11 is also connected to an ignition plug 43 via an igniter 41 and an ignition coil 42, and to an injector 45 via a driver 44.

The ignition timing control and fuel injection control by the first microcomputer 11 are based on known methods. The fuel injection control is performed, for example, in Japanese Patent Publication No.
It is described in Japanese Patent Publication No. There are a plurality of types of cams (not shown) for driving the intake and exhaust valves of the engine, and for example, they are selected according to the rotation speed and load of the engine. A signal for selecting the cam (hereinafter, valve timing V / T
Is calculated by the first microcomputer 11 using the engine speed and the load condition signal of the engine. This valve timing V / T is the driver 46
To the solenoid 4 for selecting the cam.
7 is driven.

The second microcomputer 21 detects knocking of the engine, and like the first microcomputer 11, the CPU 22 (hereinafter referred to as knock CPU 22), ROM, RAM.
And an input / output interface and the like (both not shown). A knock sensor (pressure sensor) 38 provided in the cylinder head of the engine is connected to the second microcomputer 21 via a waveform shaping circuit 39.

As described above, the second microcomputer 21 detects knocking. For this knocking detection, not only the output signal of the knock sensor 38 but also the outputs of the Pba sensor 32 and the Tw sensor 33 are detected. signal,
Also, the valve timing V / T is required. The P
The output signals of the ba sensor 32 and the Tw sensor 33, the valve timing V / T, and the parity check bit (parity bit P1) are transmitted from the general-purpose transmission port 12A of the main CPU 12 to the knock CP.
It is directly transmitted to the general-purpose reception port 22B of U22 via the communication line 10.

Further, the first microcomputer 11
Is information indicating whether or not knocking has occurred (hereinafter, knock (Kno
ck) flag) and a signal indicating whether or not the knock sensor 38 is operating normally (fail safe signal, hereinafter referred to as F / S flag), to prevent knocking. Control (hereinafter referred to as knock control) is performed. This knock control retards the ignition timing when the engine is knocking, and restores the ignition timing (advances the ignition timing) when the engine is no longer knocking. Such a knock control method is disclosed, for example, in Japanese Patent Laid-Open No. 63-29061.
It is described in Japanese Patent Publication No.

The knock flag and the F / S flag, and the parity bit P2 for parity check are used for the general-purpose transmission port 22 of the knock CPU 22 by a method described later.
It is directly transmitted from A to the general-purpose reception port 12B of the main CPU 12 via the communication line 10. The second microcomputer 21 has a watchdog timer (not shown), and its output signal is a knock CPU.
The data is directly transmitted from the general-purpose transmission port 22P of 22 to the general-purpose reception port 12Q of the main CPU 12 via the communication line 10.

The main CPU 12 and the knock CPU 2
2 is LED12L and LED for abnormality display
22L is connected. The first microcomputer 11 is also connected to an abnormality display lamp 12M provided in a driver's seat of a vehicle equipped with the vehicle electronic control device. Although not shown, the second microcomputer 21 may also be connected to the lamp 12M or another abnormality indicating lamp provided in the driver's seat.

In FIG. 3, a power source (battery) for supplying electric power to the respective constituent elements shown in FIG. 3 is omitted.

Now, in the operation of the electronic control unit for a vehicle having such a configuration, the main CPU 12 and the knock C
The method of data communication between the PUs 22 will be described in detail below.

The data transmitted from the transmission port 12A of the main CPU 12 to the reception port 22B of the knock CPU 22 is the following four types of 6-bit data. Valve timing V / T: "L" / "H" information (1 bit) Negative pressure in intake pipe Pba: Zone information 4 steps (2 bits) Cooling water temperature Tw: Zone information 4 steps (2 bits) Parity bit P1 (parity (Check bit): "0" / "1" information (1 bit) Further, the data transmitted from the transmission port 22A of the knock CPU 22 to the reception port 12B of the main CPU 12 is the following 3 types of 3 bits data. Is. Knock flag: "L" / "H" information (1 bit) F / S flag: "L" / "H" information (1 bit) Parity bit P2 (bit for parity check): "0" / "1" Information (1 bit) First, a data communication method for transmitting data from the main CPU 12 to the knock CPU 22 will be described.

FIG. 4 shows the main CPU 12 to the knock CPU.
22 is a time chart showing the main operation when data is transmitted to the CPU 22, and FIGS. 5 and 6 are flowcharts showing the main processing operations (crank processing and ignition timing / fuel amount calculation processing) executed by the main CPU 12 in this case, as well. Figure 8
Is a flowchart showing a main processing operation (crank processing) performed by the knock CPU 22 in this case. 7 and 9 are flowcharts showing background processing executed by the main CPU 12 and the knock CPU 22.

Note that Rxbuf shown at the bottom of FIG. 4 indicates an 8-bit buffer (register) in the second microcomputer 21, which will be described later with reference to step S34 of FIG. Further, as shown in FIG. 4, the crank pulse generation stage generated immediately after the rising of the TDC pulse is the 0th stage, and hereinafter, the stage number is generated for each crank pulse until the next TDC pulse is generated. Is incremented. That is, the stage numbers are 0 to 5. This stage indicates the crankshaft rotation angle of the engine.

The crank processing (processing synchronized with the crank pulse) performed by the main CPU 12 is performed by an interrupt signal generated at the start of each stage. FIG. 5 shows only the main processing of the crank processing when data is transmitted from the main CPU 12 to the knock CPU 22. Immediately after the crank process is completed in the 0th stage, the ignition timing / fuel amount calculation process shown in FIG. 6 is performed. If the first stage is reached before the ignition timing / fuel amount calculation processing is completed,
As shown in, the crank processing is preferentially performed by interruption, and after the crank processing is completed, the continuation of the ignition timing / fuel amount calculation processing is executed again.

Further, FIG. 6 shows only the main processing of the ignition timing / fuel amount calculation processing when data communication is performed from the main CPU 12 to the knock CPU 22. Further, the main CPU 12 performs the background processing shown in FIG. 7 when the load of the calculation is lightened.

The crank processing performed by the knock CPU 22 is also performed by an interrupt signal generated at the start of each stage. FIG. 8 shows only the main processing of the crank processing when data is transmitted from the main CPU 12 to the knock CPU 22. Also, knock CP
The U22 performs the background processing shown in FIG. 9 when the load of the calculation and the like becomes light.

First, the operation of the main CPU 12 will be described. First, in the ignition timing / fuel amount calculation process of FIG.
In step S11, the intake pipe negative pressure Pba signal output from the Pba sensor 32 is read. In step S12, it is determined which of the areas (zones) divided into four stages the read Pba belongs to. That is,
In this process, the read Pba is converted into 2-bit digital data. This converted 2-bit data is
It is stored in the first and second bits of the 8-bit buffer (register) Txbuf (0th bit to 7th bit) in the first microcomputer 11 (see FIG. 10A,
In the figure, the Pba data is indicated by the symbol X).

In step S13, FIG.
In step S22, the area (zone) of the cooling water temperature Tw determined and stored is read. This cooling water temperature zone is divided into four stages as described above, and Tw data is 2 bits. Further, in the step S22, the Tw data is stored in the third to fourth bits of the 8-bit register in the first microcomputer 11 (see FIG. 10B, in which Tw data is represented by the symbol Y). It is shown).

In step S14, step S1
The contents of the 8-bit register read in 3 are combined in the buffer Txbuf (see FIG. 10C).

In step S15, the valve timing V / T (1 bit data) calculated and set by the first microcomputer 11 is read, and
In step S16, the data is stored in the buffer Txbuf.
Is stored in the fifth bit (see FIG. 10D, the valve timing V / T data is indicated by the symbol Z in the figure).

In step S16A, the buffer T
The parity bit P1 is set based on the data of the first to fifth bits of xbuf. This parity bit P1 is stored in the 0th bit of the buffer Txbuf in step S16B (see FIG. 10E).

In the following description, the 6-bit data (Pb
a, Tw, V / T and P1) are called frame data.

In step S18, the ignition timing (angle), the fuel injection amount, etc. are calculated, the engine load is determined, and the valve timing V / T is set. In the calculation of the ignition timing in step S18, the ignition timing is retarded by referring to a knock flag (information about whether or not the engine is knocking) fetched in step S17 (see FIGS. 13 and 17) described later. The amount is set and the ignition timing is corrected according to the retard amount. After that, other processing (not shown) is performed, and the processing ends.

Next, in the crank processing shown in FIG. 5, first, in step S1, it is determined what stage the stage is, that is, the stage number. Then, in step S2, various processes corresponding to each stage (for example, angle-time conversion of the ignition timing calculated in FIG. 6 described above, timer start for ignition, etc.) are executed.

Next, in step S5, the discriminated stage number is set to n. In step S6, the nth bit data of the frame data configured in the buffer Txbuf in step S16 of FIG. 6 described above is output to the transmission port 12A. That is, when the process shown in step S16B of FIG. 6 of the ignition timing / fuel amount calculation process shown in FIG. 4 is completed (that is, when the frame data is completed), , The first and second bit data (Pb of the buffer Txbuf synthesized in step S16B).
a) has transmit port 1 in the first and second stages respectively
2A, and similarly the third and fourth buffer Txbuf
The data of the bit (Tw), the data of the fifth bit (valve timing V / T), and the data of the zeroth bit (parity bit P1) are the third, fourth, fifth and zeroth stages, respectively. Is output with. After that, other processing (not shown) is performed, and the processing ends.

In the background processing of FIG. 7,
In step S21, the output signal of the Tw sensor 33 is read. In step S22, the read Tw is 4
It is determined which one of the zones divided into stages. That is, in this processing, Tw is converted into 2-bit digital data. The converted 2-bit data is stored in the third and fourth bits of the 8-bit register (0th to 7th bits) in the first microcomputer 11, as described above with reference to step S13 of FIG. (See FIG. 10B).

Next, the operation of the knock CPU 22 will be described. In the crank process of FIG. 8, first, step S31.
In, the stage number is determined. Then, in step S32, various types of processing (for example, knocking determination) according to each stage are executed.

In step S33, the discriminated stage number is set to n. After step S33, the process of step S34 is performed. The process of step S34 is performed by the main CPU 1 shown in FIG.
The process is completed by the time the process of step S6 of 2 is started. That is, the crank processing executed by the main CPU 12 shown in FIG. 5 and the crank processing executed by the knock CPU 22 shown in FIG. 8 are executed simultaneously with the start of each stage.
5 is performed immediately after the crank processing is started, whereas the processing of step S6 of FIG. 5 is performed after a while from the start of the crank processing (that is, the processing of step S2 and the step described later with reference to FIG. 12). This is performed after the processing of S3, S4, etc. has been executed.

As will be described later, in the process of step S34, the data generated at the transmission port 12A is knocked by the CPU.
This is the process of reading in step 22, but the above-mentioned step S34
And the processing timings of S6 are different, in other words,
Due to the phase difference between steps S34 and S6, as shown in FIG. 4, immediately after the start of each stage, the data generated at the transmission port 12A is read into the knock CPU 22, and thereafter, the data generated at the transmission port 12A is read. Will be updated.

In step S34, the main CPU
The data generated in the 12 transmission ports 12A is read and stored in the (n-2) th bit of the 8-bit buffer Rxbuf (0th bit to 7th bit) in the second microcomputer 21. That is, as the above reading is performed at each stage, as shown in FIG. 4, at the 0th to 5th bits of the buffer Rxbuf, Pba, T generated at the transmission port 12A of the main CPU 12 are
Each data of w, V / T and P1 is stored. afterwards,
Other processing not shown is performed and the processing ends.

In the background processing of FIG.
In step S41, the second microcomputer 21 determines whether or not the knock sensor 38 is functioning normally, and the F / S flag is generated according to the determination result.

Next, from the knock CPU 22 to the main CP
A data communication method for transmitting data to U12 will be described. FIG. 11 shows the knock CPU 22 to the main CPU 12
12 and 13 are flowcharts showing the main processing operations (crank processing and ignition timing / fuel amount calculation processing) executed by the main CPU 12 in this case. 1
4 is a flowchart showing the main processing operation (crank processing) performed by the knock CPU 22 in this case.

The main CP is shown in FIG. 12 and FIG.
Of the crank processing and ignition timing / fuel amount calculation processing performed by U12, the knock CPU 22 to the main CPU
Only the main processing for sending data to 12 is shown. In addition, in FIG. 14, in the crank processing performed by the knock CPU 22, from the knock CPU 22 to the main C.
Only the main processing when transmitting data to the PU 12 is shown.

First, in the crank processing of FIG. 14 executed by the knock CPU 22, after the stage determination or the like is performed (after step S31 of FIG. 8), it is determined in step S35 whether the stage is the 0th stage. Is determined. If it is the 0th stage, in step S36, the knock flag calculated by the second microcomputer 21 is output to the transmission port 22A of the knock CPU 22.

If it is determined in step S35 that the stage is not the 0th stage, step S35
At 37, it is judged if the stage is the second stage. If it is the second stage, step S3
8, the F / S flag is output to the transmission port 22A of the knock CPU 22.

When it is determined in step S37 that the stage is not the second stage, step S37
At 39A, it is determined whether or not the stage is the fourth stage. If it is the fourth stage, step S
In 39B, the parity bit P2 is set based on the knock flag and the F / S flag output to the transmission port 22A in the immediately preceding 0th and second stages, and the parity bit P2 is output to the transmission port 22A.

Step S36, S38 or S39B
Or when the stage is not the 0th, 2nd, or 4th stage, another process not shown is performed thereafter, and the process ends.

Next, in the crank processing of FIG. 12 executed by the main CPU 12, after a predetermined stage determination (step S1 of FIG. 5) and the like are executed, it is determined in step S3 whether the stage is the third stage. Is determined. If it is the third stage, the data generated in the reception port 12B of the main CPU 12 (that is, the data generated in the transmission port 22A of the knock CPU 22) in step S4 is read as the F / S flag.

When it is determined in step S3 that the stage is not the third stage, it is determined in step S4A whether or not the stage is the fifth stage.
If it is the fifth stage, the data generated at the transmission port 22A of the knock CPU 22 in step S4B is read as the parity bit P2.

After the processing of step S4 or S4B is completed, or when the stage is neither the third stage nor the fifth stage, other processing not shown is then performed and the processing ends.

FIG. 13 executed by the main CPU 12.
In the ignition timing / fuel amount calculation process of step S17, the data generated in the reception port 12B of the main CPU 12 (that is, the transmission port 22A of the knock CPU 22 in step S17).
(Data generated at) is read as a knock flag.
The process of step S17 is performed after the synthesis of the buffer Txbuf is completed (after the process of step S16B of FIG. 6 is completed).

In this way, the second microcomputer 2
The knock flag and the F / S flag calculated in 1 and the parity bit P2 set based on the knock flag and the F / S flag are transferred to the first microcomputer 11.

Data is transmitted from the first microcomputer 11 to the second microcomputer 21 in this way, and conversely, data is transmitted from the second microcomputer 2 to the second microcomputer 21.
Data is also transmitted from 1 to the first microcomputer 11. Then, this data communication is performed for each stage, that is, according to the rotation of the engine (crankshaft rotation angle).

By the way, the first microcomputer 11
From the second microcomputer 21 to the second microcomputer 21, and the second microcomputer 21 to the first
The data transmission performed to the microcomputer 11 has been described using different time charts and flowcharts, but these communications are simultaneously performed. That is, the crank processing executed by the main CPU 12 shown in FIGS. 5 and 12, the ignition timing / fuel amount calculation processing executed by the main CPU 12 shown in FIGS. 6 and 13, and FIG. Shown in,
The crank processing executed by the knock CPU 22 is stored in each of the microcomputers 11 and 12 as the same crank processing program and ignition timing / fuel amount calculation processing program.

FIG. 15 is a time chart of the first embodiment of the present invention, which is a combination of the time charts shown in FIGS. 4 and 11 described above. Figure 16 shows the main CP
13 is a flowchart showing a crank process executed by U12, which is a combination of the flowcharts shown in FIGS. 5 and 12 described above. Similarly, FIG. 17 is a flow chart showing the ignition timing / fuel amount calculation processing executed by the main CPU 12, and FIG. 18 is a flow chart showing the crank processing executed by the knock CPU 22, which are shown in FIGS. It is a combination of the flowcharts shown in FIGS. 8 and 14. 15 to 18, the same reference numerals as those used for creating (combining) the respective drawings represent the same or equivalent portions, and thus the description thereof will be omitted.

Note that the processing up to step S16B shown in FIG. 17 (FIG. 6) needs to be executed during the 0th stage even when the engine is running at a high speed.
The process of step S17 of 3) needs to be executed between the 0th stage and the 1st stage even at high engine speed. The process of step S17 may be executed in the crank process of the first stage, or may be executed in the crank process of the stage after the knock flag is output to the transmission port 22A in the 0th stage. Is also good.

Further, step S3 of FIG. 16 (FIG. 12).
As described in S4 and S4, and S4A and S4B, the main CPU 12 reads the F / S flag and the parity bit P2 in the third and fifth stages. It may be the second stage or the fourth stage as long as it is after the F / S flag and the parity bit P2 are output.

Now, as shown in FIGS. 6 and 17,
In the ignition timing / fuel amount calculation process executed by the main CPU 12, Pba is read and zone determination (A
/ D conversion), Tw read by background processing and zone discrimination, and valve timing V
/ T is read and the parity bit P1 is set by using each data, and 6-bit frame data is configured in the buffer Txbuf by using these data, so that it is executed in each stage. In the crank processing of the CPU 12 (FIGS. 5 and 16), it is sufficient to simply read the data bit by bit from the buffer Txbuf.

As a result, the load of the crank processing executed by the main CPU 12 is reduced and the processing time is not so long, so that the engine can be controlled well even if the engine speed increases.

FIG. 1 and FIG. 2 are functional block diagrams of the first embodiment of the present invention, and by combining them, the entire diagram is completed. 1 and 2, the same reference numerals as those in FIG. 3 represent the same or equivalent portions. 1 and 2, the left side of the broken line shows the configuration of the first microcomputer 11, and the right side of the broken line shows the configuration of the second microcomputer 21.

First, on the side of the first microcomputer 11, the cylinder pulse, the TDC pulse and the crank pulse are input to the stage discriminating means 51 and the engine speed discriminating means 52. The stage discriminating means 51 discriminates the stage number, and the engine speed discriminating means 52 discriminates the engine speed.

The fuel injection control means 58 uses the engine speed signal and the output signals of the Pba sensor 32, the Tw sensor 33, the Pa sensor 34 and the Th sensor 35 and the like to inject the fuel from the injector 45 by a known appropriate method. The amount of fuel to be injected, the fuel injection timing, etc. are calculated. The output signal of the fuel injection control means 58 is input to the driver 44, which drives the injector 45.

The ignition timing control means 59 calculates the ignition timing using the engine speed signal, the output signal of the Th sensor 35 and the like. The output signal of the ignition timing control means 59 is input to the igniter 41. This igniter 41
Through the ignition coil 42, the spark plug 43
It is connected to the.

The load discriminating means 54 detects the load of the engine by a known method using the output signals of the Pba sensor 32 and / or the Th sensor 35 or other signals.

The V / T calculating means 53 calculates the valve timing V / T using the engine speed signal and the engine load signal (the output signal of the load discriminating means 54). The calculated valve timing V / T is calculated by the driver 46.
, Which drives a plurality of solenoids 47 for selecting cams for driving intake / exhaust valves.

The zone discriminating means 55 and 56 discriminate which of the zones divided into four stages the output signals of the Pba sensor 32 and the Tw sensor 33 belong to, and convert each into a 2-bit digital signal. .. Then, the discriminated and converted zone information is output to the buffer Txbuf 57 in the 0th stage. Similarly, the output signal of the V / T calculation means 53, that is, the valve timing V / T (1 bit data) is also output to the buffer Txbuf 57 in the 0th stage. Then, when the 5-bit data as shown in FIG. 10D is completed in the area of the 1st bit to the 5th bit of the buffer Txbuf 57, the parity bit P1 is set by the parity bit setting means using the data, and the bit P1 is set. Is placed in the 0th bit of the buffer Txbuf57. As a result, in the 0th stage, 6-bit frame data as shown in FIG. 10E is completed in the buffer Txbuf 57.

The frame data in the buffer Txbuf 57 is output to the transmission port 12A bit by bit for each stage. More specifically, as shown in FIG. 4 (or FIG. 15), 2-bit data of Pba is stored in the first and second stages and 2 of Tw is stored in the third and fourth stages.
Bit data, 1-bit data of valve timing V / T in the fifth stage, and 1-bit data of parity bit P1 in the 0th stage are output to the transmission port 12A, respectively.

On the other hand, on the second microcomputer 21 side, the cylinder pulse and the crank pulse are input to the stage discriminating means 81. This stage discrimination means 8
1 discriminates the stage number similarly to the stage discriminating means 51.

The buffer Rxbuf 82 is the transmission port 12A.
The data transferred from the receiving port 22B to the receiving port 22B is fetched one bit at each stage. For details, see FIG.
As shown in FIG. 5), 2-bit data of Pba in the second and third stages, 2-bit data of Tw in the fourth and fifth stages, and 1 of valve timing V / T in the 0th stage. The bit data, and the 1-bit data of the parity bit P1 in the first stage, are taken into the areas of the 0th to 5th bits of the buffer Rxbuf82, respectively.

When the data is taken into the buffer Rxbuf 82, the data is transferred to the data discriminating means 83,
Then, the content of the data is determined. Of the discriminated data, each data of Pba, Tw and valve timing V / T is input to the knocking discrimination means 84. Further, the data taken into the buffer Rxbuf 82 is inputted to the abnormal signal generating means 86. The abnormal signal generating means 86 compares the 5-bit data of Pba, Tw and the valve timing V / T with the parity bit P1, and the P1
Is correct. If the parity bit P1 is erroneous data, the LED 22L is energized to display an abnormality on the first microcomputer 11 side.

The knocking determination means 84 determines each data of the determined Pba, Tw and valve timing V / T,
Also, the presence / absence of knocking is determined using the signal output from the knock sensor 38, and a knock flag is output. This knock flag is output to the transmission port 22A in the 0th stage, as shown in FIG. 11 (FIG. 15).

The F / S discriminating means 85 includes the knock sensor 38.
Is determined to be normal, and an F / S flag is generated. This F / S flag is output to the transmission port 22A in the second stage, as shown in FIG. 11 (FIG. 15).

The parity bit setting means 87 outputs the knock flag and F output to the transmission port 22A as described above.
The parity bit P2 is set using the 2-bit data of the / S flag. This parity bit P2 is shown in FIG.
As shown in (FIG. 15), it is output to the transmission port 22A in the fourth stage.

Returning to the first microcomputer 11 side again, in the 0th stage, the 3rd stage and the 5th stage, the data transferred from the transmission port 22A to the reception port 12B are the knock flag, the F / S flag, and And the abnormal signal generating means 6 as the parity bit P2.
Taken in 3. The abnormal signal generating means 63 compares the 2-bit data of the knock flag and the F / S flag with the parity bit P2, and determines whether or not the P2 is correct. If the parity bit P2 is erroneous data, LE is used to display an error on the second microcomputer 21 side.
Energize D12L and lamp 12M.

When the LED 12L and / or the lamp 12M is configured to display an abnormality of another microcomputer or the like, not only the LED 12L and the lamp 12M are simply energized, but they are blinked. However, the blinking may be performed in a pattern unique to the abnormality. The same applies to the energization of the LED 22L.

The data received at the receiving port 12B is
It is also transferred to the data discriminating means 62, and the contents of the data (knock flag and F / S flag) are discriminated. Then, the knocking control means 60 corrects the ignition timing data output from the ignition timing control means 59 to the igniter 41 according to the knock flag.

The second microcomputer 21 has a watchdog timer 88, and its output (watchdog output) is transferred from the transmission port 22P to the reception port 12Q of the first microcomputer 11. The abnormality signal generating means 63 monitors the state of the receiving port 12Q at a predetermined cycle, for example, and when an abnormality of the second microcomputer 21 is detected from the watchdog output, the abnormality signal generating means 63 displays the abnormality. , Energize the LED 12L and the lamp 12L. A watchdog timer may be provided on the first microcomputer 11 side to notify the second microcomputer 21 of its abnormality.

In the above description, the first microcomputer 11 that mainly controls the vehicle communicates with the second microcomputer 21 that determines knocking. When the traction control for suppressing idling of the vehicle at the time of acceleration or other control is performed by the microcomputer different from the first microcomputer 11, the present invention is applicable to communication between the microcomputers. It is natural that there is.

The present invention can be applied even if the number of microcomputers for data communication is three or more.

Furthermore, when data is transmitted from the first microcomputer 11 to the second microcomputer 21, a predetermined one frame (adjacent stage) is set in the ignition timing / fuel amount calculation processing of the main CPU 12. Frame data is created in the buffer Txbuf by using all the data to be transmitted in 6 pieces), in other words, all the data to be transmitted at a predetermined timing, and the frame data is generated for each stage. In the crank processing of the main CPU 12, which has been described above, the bit is transmitted to the second microcomputer 21 bit by bit, but if the processing time delay of the crank processing is allowed, the creation of frame data in the buffer Txbuf is omitted. However, in each crank processing performed in each data transmission stage, each data read and A / D conversion are performed. Was carried out, it is also possible to carry out the transmission of the data.

That is, for example, regarding the transmission of Pba,
The processing of steps S11 and S12 of FIG.
Transmission of 2-bit Pba data that has been A / D converted by the first stage crank processing of the main CPU 12,
You may make it perform 1 bit at a time in the crank process of a 1st and 2nd stage.

On the contrary, the second microcomputer 2
When transmitting data from 1 to the first microcomputer 11, the same frame data as described above is used.
It is formed in the buffer of the second microcomputer 21 once, and then, in the crank processing executed by the knock CPU 22 for each stage, the data in the buffer is output to the first microcomputer 11 bit by bit. Of course, it is okay.

As described above, at least data transmission from the main CPU 12 to the knock CPU 22 is performed by one bit for each stage. In the above embodiment, the number of stages is 6, and the main CP
The data transmitted from the U12 to the knock CPU 22 is 6 bits including the parity bit P1. Therefore, for example, when it is desired to increase the number of bits of data to be transmitted in order to improve the accuracy of data performed on the side of the knock CPU 22, that is, from the main CPU 12 to the knock C
When the data to be transmitted to the PU 22 is set to 7 bits or more, the transmission port 12A provided in the main CPU 12 and the reception port 22B provided in the knock CPU 22 are each provided in plural, and data transmission for each stage is performed in plural bits. You need to do it.

Further, in the above embodiment, the knock CPU 22
It is assumed that only the presence or absence of knocking is detected and the ignition timing retard amount corresponding to the knocking is calculated on the main CPU 12 side. However, the knocking CPU side determines the knocking state, and the ignition is performed according to the state. Even when the timing delay amount is also calculated and the delay amount is transmitted from the knock CPU to the main CPU, the data to be transmitted may exceed 7 bits.

Below, the main CPU and the knock CPU are provided with two general-purpose transmission ports for data transmission and two general-purpose reception ports for data reception, respectively, and data transmission / reception for each stage is performed by 2 bits. An example will be described.

FIG. 21 is a functional block diagram of the second embodiment of the present invention. In the figure, the same reference numerals as those in FIGS. 1 to 3 represent the same or equivalent portions. In FIG. 21, the cylinder pulse, the TDC pulse, and the crank pulse are input to the stage discrimination means 51 of the first microcomputer 11T via the waveform shaping circuit 31. Then, the stage determination output is output to the control amount computing means 91. In addition, the negative pressure Pba in the intake pipe, the cooling water temperature Tw, and the atmospheric pressure P
Various sensors for detecting a, throttle valve opening Th, atmospheric temperature Ta, etc. are also connected to the control amount computing means 91. As will be described later, the control amount computing means 91 is configured to output 2 bits for each stage (that is, 12 bits for 6 stages).
The data (in bits) is transmitted to the second microcomputer 21T. For transmitting the data, the first microcomputer 11T has two 8-bit buffers Txb.
uf1 and Txbuf2 and two general purpose transmission ports 12A connected to them are provided.

The second microcomputer 21T is provided with two general-purpose reception ports 22B connected to the two ports 12A and two 8-bit buffers Rxbuf1 and Rxbuf2 connected to the ports 22B.
The 12-bit data transmitted from the control amount etc. calculating means 91 is inputted to the control amount etc. calculating means 92 via the Rxbuf1 and Rxbuf2.

The stage discriminating means 81 discriminates the stage by using the cylinder pulse and the crank pulse. The control amount computing means 92 detects the knocking state of the vehicle using the stage information, various data transmitted from the first microcomputer 11T, and the signal input from the knock sensor, and at the same time, detects the state. Accordingly, the retard amount of the ignition timing is calculated. The control amount calculation means 92 is
This delay amount and various data to be described later are set to 2 bits for each stage (that is, 1 for 6 stages, as described later).
(2 bits) Transmitted to the first microcomputer 11T. For this data transmission, the second microcomputer 21T is provided with two 8-bit buffers Txbuf3 and Txbuf4 and two general-purpose transmission ports 22A connected to them.

The first microcomputer 11T is provided with two general-purpose reception ports 12B connected to the two ports 22A and two 8-bit buffers Rxbuf3 and Rxbuf4 connected to the ports 12B. .. The 12-bit data transmitted from the control amount etc. calculating means 92 is inputted to the control amount etc. calculating means 91 via the Rxbuf3 and Rxbuf4. Then, the control amount computing means 91 uses the data input as described above, Pba, Tw, Pa, Th, Ta, etc. to drive the ignition timing, the fuel injection amount, and the intake / exhaust valve driving cam. Calculate signals etc.

The control amount computing means 91 and 92 check the parity bits transmitted from each other, and when an abnormality is detected, the abnormality signal generating means 63A.
The LED 12L and the lamp 12M or the LED 22L is directly energized via.

Also in this embodiment, the watchdog timer 88 is provided in the second microcomputer 21T, and its output, the watchdog output, is sent to the first microcomputer 1 via the general-purpose transmission port 22P.
It is transmitted to the 1T general-purpose reception port 12Q. Then, when the abnormality signal generating means 63A detects the abnormality of the second microcomputer 21T from this watchdog signal, the LED 12L and the lamp 12M are energized.

As is apparent from the above description, each of the first and second microcomputers 11T and 21T has five ports, and the transmission port 12A and the reception port 22B, the transmission port 22A and the reception port 12 are provided.
B, and the transmission port 22P and the reception port 12Q are
Each is connected by five communication lines 10.

Data (excluding watchdog output) transmitted and received between the main CPU of the first microcomputer 11T and the knock CPU of the second microcomputer 21T in the second embodiment are as follows. ..

First, the two transmission ports 1 of the main CPU
The data transmitted from 2A to the two receiving ports 22B of the knock CPU are the following 7 types and 12 bits of data. (1) Negative pressure in intake pipe Pba: Zone information 16 levels (Pba0
~ Pba3, 4 bits) (2) Cooling water temperature Tw: Zone information 4 levels (Tw0 and Tw)
w1, 2 bits) (3) Atmospheric temperature Ta: Zone information 2 steps (1 bit) (4) Valve timing V / T: "L" / "H" information (1
Bit) (5) Information during fuel cut processing F / C: "L" / "H"
Information (1 bit) (6) Information during ignition timing retard control other than knock control R / C: "L" / "H" information (1 bit) (7) Parity bit: "0" / "1" information (P00 and P
01, 2 bits) Further, the data transmitted from the two transmission ports 22A of the knock CPU to the two reception ports 12B of the main CPU are the following four types of 12-bit data. (8) Ignition timing retard amount due to knocking Igkn: (Igkn0
~ Igkn6, 7 bits) (9) F / S flag: "L" / "H" information (1 bit) (10) Parity bit: "0" / "1" information (P02 and P)
03, 2 bits) (11) Check bit: fixed at "H" (Cb0 and Cb1, 2 bits) FIG. 22 is a diagram showing two 8-bit buffers Txbuf1 and Txbuf2 provided in the first microcomputer 11T, and the inside thereof. The 6-bit frame data is completed in the area from the 0th bit to the 5th bit. Pba0 constituting each frame data
~ Pba3 (Pba zone information), Tw0 and Tw1 (Tw zone information), Ta (Ta zone information), V / T, F / C,
R / C and P00 and P01 are both determined by calculation on the side of the first microcomputer 11T, of which Tw0
And Tw1 and Ta are determined by, for example, the calculation of the background processing, and other data are determined by, for example, the ignition timing / fuel amount calculation processing. Of course, the parity bits P00 and P01 are respectively determined according to these 5-bit data when the arrangement of the data of the first bit to the fifth bit of Txbuf1 and Txbuf2 is completed.

These frame data are completed by at least the 0th stage. Then, in the crank processing of the first microcomputer 11T that is executed for each stage from the next first stage, the data of the bit position corresponding to the stage number (that is, the first bit data (Pba0 And Pba1)
However, in the next second stage, the second bit data (Pba2 and Pba3) is output via the general-purpose transmission port 12A. Then, the frame data is transmitted at the 0th
Finish on stage.

In this way, two bits (each Txbuf1 and Tx) for each stage are transferred from the first microcomputer 11T to the second microcomputer 21T.
Data is transmitted from xbuf2 bit by bit.

FIG. 23 shows the second microcomputer 21T.
Two 8-bit buffers Txbuf3 and Txb
It is a figure which shows uf4. Similar to FIG. 22, FIG. 23 shows a state in which 6-bit frame data is completed in the area from the 0th bit to the 5th bit inside them.

Igkn0 to construct each frame data
Igkn6, F / S flag, parity bits P02 and P03,
The check bits Cb0 and Cb1 are both determined by the crank processing on the second microcomputer 21T side.
The parity bits P02 and P03 are Txbuf3 and Txbuf4.
When the arrangement of the data from the 3rd bit to the 5th bit and the 0th bit of is completed, it is determined in accordance with each of these 4 bit data and arranged in the 2nd bit thereof. After that, Cb0 and Cb1 (fixed to "H") are arranged at the first bit of each Txbuf3 and Txbuf4, thereby completing the frame data.

These frame data are completed by at least the 0th stage. Then, in the crank processing of the second microcomputer 21T which is executed for each stage from the next first stage, the data of the bit position corresponding to the stage number (that is, the data of the first bit (Cb0 in the first stage) And Cb1)
In the next second stage, the second bit data (P
02 and P03)) are output via the general-purpose transmission port 22A. Then, the transmission of the frame data ends in the 0th stage.

In this way, two bits (each Txbuf3 and Tx) for each stage are transferred from the second microcomputer 21T to the first microcomputer 11T.
Data is transmitted from xbuf4 (one bit at a time).

FIG. 24 is a time chart showing an example of the procedure of data transmission / reception by the main CPU and the knock CPU. In the figure, the main CPU side and the knock CPU
Reference signs R and T shown in the crank processing on the side indicate reception data and transmission data as viewed from the respective CPUs.

In FIG. 24, in the main CPU, the first
Unlike the embodiment of the first example, the ignition timing /
The fuel amount calculation process is executed, and then the crank process is executed. Then, the data reception and transmission on the main CPU side is performed at a timing (delayed in this example) deviated from the data reception and transmission performed on the knock CPU side in the crank processing executed simultaneously with the start of the stage. .. In other words, knock CPU data transmission → main CP
U data reception → Main CPU data transmission → Knock C
Data reception / transmission between the main CPU and the knock CPU is executed at different timings, that is, with a phase difference, such as PU data reception → knock CPU data transmission →.

In this embodiment, in order to secure the above timing, the knock CPU side receives and transmits data at the beginning of the crank processing, and the main CPU side performs crank processing at the ignition timing / fuel. Data reception and data transmission are performed after the amount calculation processing and at the end of the crank processing, but the point is that data is transmitted and received at different timings between the main CPU and the knock CPU. It suffices to be able to reliably send and receive.

Now, as described above with reference to FIG. 22, in the 0th stage, the first microcomputer 11T
Then, the parity bits P00 and P01 are transmitted to the second microcomputer 21T. The second microcomputer 21T compares P00 and P01 with the other frame data, and compares them with the first microcomputer 11
It is determined whether or not there is an abnormality in T or the received data. In the case of the abnormality determination, the LED 22L (FIG. 22) is energized. Further, the ignition timing retard amount transmitted to the first microcomputer 11T is set to a fixed value, for example.

Similarly, the second microcomputer 21T
From the first microcomputer 11T to the first
And in the second stage, check bits Cb0 and Cb
b1 and parity bits P02 and P03 are transmitted.
When the first microcomputer 11T determines that Cb0 and Cb1 are “L”, it determines that the second microcomputer 21T or the received data has an abnormality, and the LED 12L and / or the lamp 12
Energize M. Further, P02 and P03 are compared with the frame data other than P02 and P03 and Cb0 and Cb1,
Even when it is determined that there is an abnormality in the second microcomputer 21T or the received data, the LED 12
Energize L and / or lamp 12M. When the abnormality is detected, the data transmitted from the second microcomputer 21T is not adopted.

Since Cb0 and Cb1 are transmitted in the first stage which is the first transmission stage of the frame data, the remaining data (that is, Igkn0 to Igkn6, F / S) is detected when an abnormality is detected by Cb0 and Cb1. No need to receive flags and P02 and P03). Therefore, the load on the first microcomputer 11T is reduced.

In the second embodiment, the ignition timing / fuel amount is calculated for each stage. For example, in a 6-cylinder engine, the ignition timing / fuel amount is calculated for each ignition of each cylinder. However, as shown in the first embodiment, the ignition timing / fuel amount calculation process may be performed only once every six stages.

Further, in FIG. 24, a knock CPU
It is shown that the data transmission by (1) is completed within 50 [μs], and the data reception by the main CPU is performed after 100 [μs] or more has passed, but this is merely an example.

Furthermore, check bits Cb0 and Cb1
Is transmitted from only the second microcomputer 21T, but it goes without saying that it may be transmitted from the first microcomputer 11T. Also,
A watchdog timer may be provided on the first microcomputer side and the output thereof may be sent to the second microcomputer side.

Further, the abnormality display means that is activated when an abnormality is detected is not limited to the lamp and the LED, and an LCD display device, a voice output device, or the like may be used.

[0119]

As is clear from the above description, according to the present invention, the following effects can be achieved. (1) According to the electronic control unit for a vehicle according to any one of claims 1 to 3, the microcomputer on the data receiving side can detect abnormality in the microcomputer on the transmitting side or the transmission line of the data, mixing of noise, or the like. .. (2) According to the electronic control device for a vehicle of claim 4, the data transmission according to the crankshaft rotation angle can be performed only by reading the data from the buffer. Therefore, according to the crankshaft rotation angle. Moreover, the time required for data processing (crank processing) other than data processing for data transmission is not delayed. As a result, even if the engine speed becomes high, various controls for vehicle control can be performed satisfactorily without delay. (3) According to the electronic control device for a vehicle of claim 5, when the abnormality of the partner microcomputer is detected, the fact is displayed. Therefore, the location of the abnormality in the electronic control device for the vehicle ( That is, it is possible to identify the microcomputer in which an abnormality has occurred, or the port, communication line, etc.).

[Brief description of drawings]

FIG. 1 shows a part of a functional block diagram of a first embodiment of the present invention, and shows an overall view thereof in combination with FIG.

FIG. 2 shows a part of a functional block diagram of a first embodiment of the present invention, and shows an overall view in combination with FIG.

FIG. 3 is a block diagram of a first embodiment of the present invention.

FIG. 4 is a time chart showing a main operation when data is transmitted from the main CPU 12 to the knock CPU 22.

FIG. 5 is a flowchart showing a main processing operation (crank processing) when data is transmitted from the main CPU 12 to the knock CPU 22 among processing operations performed by the main CPU 12.

FIG. 6 is a flowchart showing a main processing operation (ignition timing / fuel amount calculation processing) when data is transmitted from the main CPU 12 to the knock CPU 22 among processing operations performed by the main CPU 12.

FIG. 7 is a flowchart showing background processing performed by the main CPU 12.

FIG. 8 is a flowchart showing a main processing operation (crank processing) when data is transmitted from the main CPU 12 to the knock CPU 22 among processing operations performed by the knock CPU 22.

FIG. 9 is a flowchart showing a background process performed by knock CPU 22.

FIG. 10 is a diagram for explaining an 8-bit buffer Txbuf provided in the first microcomputer 11 and how data is configured in the buffer.

FIG. 11 is a time chart showing a main operation when data is transmitted from the knock CPU 22 to the main CPU 12.

FIG. 12 is a flowchart showing a main processing operation (crank processing) when data is transmitted from the knock CPU 22 to the main CPU 12, among processing operations performed by the main CPU 12.

FIG. 13 is a flowchart showing a main processing operation (ignition timing / fuel amount calculation processing) when data is transmitted from the knock CPU 22 to the main CPU 12, among processing operations performed by the main CPU 12.

FIG. 14 is a flowchart showing a main processing operation (crank processing) when data is transmitted from knock CPU 22 to main CPU 12, among processing operations performed by knock CPU 22.

FIG. 15 is a time chart of the first embodiment of the present invention.

FIG. 16 is a flowchart showing crank processing executed by the main CPU 12.

FIG. 17 is a flowchart showing an ignition timing / fuel amount calculation process executed by the main CPU 12.

FIG. 18 is a flowchart showing a crank process executed by knock CPU 22.

FIG. 19 is a diagram showing an example of a conventional data communication method performed between a plurality of microcomputers.

FIG. 20 is a diagram showing another example of a conventional data communication method performed between a plurality of microcomputers.

FIG. 21 is a functional block diagram of a second embodiment of the present invention.

FIG. 22 is a diagram showing two 8-bit buffers Txbuf1 and Txbuf2 provided in the first microcomputer 11T.

FIG. 23 is a diagram showing two 8-bit buffers Txbuf3 and Txbuf4 provided in the second microcomputer 21T.

FIG. 24 is a time chart of the second embodiment of the present invention.

[Explanation of symbols]

11, 11T ... First microcomputer, 12 ... Main CPU, 12A ... General-purpose transmission port, 12B, 12Q ...
General-purpose reception port, 12L, 22L ... LED, 12M ... Lamp, 21, 21T ... Second microcomputer, 22
... Knock CPU, 22A, 22P ... General-purpose transmission port, 2
2B ... General-purpose reception port, 38 ... Knock sensor, 43 ... Spark plug, 45 ... Injector, 47 ... Solenoid, 5
1, 81 ... Stage discrimination means, 57 ... Buffer Txbuf,
60 ... Knocking control means, 63, 63A, 86 ... Abnormal signal generation means, 82 ... Buffer Rxbuf, 84 ... Knocking determination means, 87 ... Parity bit setting means, 88 ... Watchdog timer, 91, 92 ... Control amount computing means

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 12, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0110

[Correction method] Change

[Correction content]

In FIG. 24, in the main CPU, similarly to the first embodiment, the crank process is first executed when the stage starts. Then, the data reception and transmission on the main CPU side is performed at a timing (delayed in this example) deviated from the data reception and transmission performed on the knock CPU side in the crank processing executed simultaneously with the start of the stage. .. That is, the data transmission of the knock CPU →
Data reception / transmission between the main CPU and the knock CPU, such as data reception of the main CPU → data transmission of the main CPU → data reception of the knock CPU → data transmission of the knock CPU → ... Executed.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0115

[Correction method] Change

[Correction content]

Also in the second embodiment, the ignition timing / fuel amount calculation process is performed only once every six stages as in the first embodiment. However, the ignition timing / fuel amount is calculated for each stage. The amount may be calculated every time. For example, in a 6-cylinder engine, the ignition timing / fuel amount may be calculated for each ignition of each cylinder.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 24

[Correction method] Change

[Correction content]

FIG. 24

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukito Fujimoto 1-4-1 Chuo, Wako-shi, Saitama Stock Research Institute Honda Technical Research Institute

Claims (5)

[Claims] 1. An electronic control unit for a vehicle, comprising: a plurality of microcomputers that perform various processes according to a rotation angle of a crankshaft; and serial data communication between the microcomputers according to the rotation angles. At least one microcomputer of the plurality of microcomputers uses the data to be transmitted, adds a parity bit for parity check to the data and creates frame data, and transmits the frame data. General-purpose transmission port for frame data transmission, and data transmission means for transmitting the frame data to the general-purpose transmission port for frame data transmission in 1-bit units in a predetermined order according to the crankshaft rotation angle. And at least another of the plurality of microcomputers The microcomputer is a general-purpose reception port for frame data reception connected to the general-purpose transmission port for frame data transmission, and data for receiving data bit by bit from the general-purpose reception port for frame data reception according to a crankshaft rotation angle. The data transmitting means and the data receiving means include a receiving means and an abnormality detecting means for detecting a parity bit from the received data to detect an abnormality of at least one of the one microcomputer and the received data, and the data transmitting means and the data receiving means have a phase difference. An electronic control device for a vehicle, which transmits and receives data. 2. An electronic control device for a vehicle, comprising: a plurality of microcomputers that perform various processes according to a rotation angle of a crankshaft; and serial data communication between the microcomputers according to the rotation angles. At least one of the plurality of microcomputers has a watchdog timer,
A watchdog output transmission general-purpose transmission port for transmitting an output signal of the watchdog timer, wherein at least another microcomputer of the plurality of microcomputers is connected to the watchdog output transmission general-purpose transmission port. A watchdog output reception general-purpose reception port and a watchdog output reception general-purpose reception port that are connected detect an output signal of the watchdog timer, and detect an abnormality of at least one of the one microcomputer and reception data. An electronic control unit for a vehicle, comprising: an abnormality detecting means. 3. An electronic control device for a vehicle, comprising: a plurality of microcomputers that perform various processes according to a rotation angle of a crankshaft; and serial data communication between the microcomputers according to the rotation angles. At least one microcomputer of the plurality of microcomputers uses the data to be transmitted, adds a parity bit for parity check to the data and creates frame data, and transmits the frame data. A general-purpose transmission port for frame data transmission, a data transmission means for transmitting the frame data to the general-purpose transmission port for frame data transmission in 1-bit units in a predetermined order in accordance with a crankshaft rotation angle, and a watch. The output signal of the dog timer and the watchdog timer A general-purpose transmission port for transmitting watchdog output for transmission, wherein at least another microcomputer of the plurality of microcomputers is connected to the general-purpose transmission port for frame data transmission, and receives general-purpose reception for frame data reception. Port, data receiving means for receiving data bit by bit from the general-purpose reception port for frame data reception according to the crankshaft rotation angle, and for watchdog output reception connected to the general-purpose transmission port for watchdog output transmission A general-purpose reception port and an abnormality detection means are provided, the data transmission means and the data reception means perform transmission and reception of data with a phase difference, and the abnormality detection means detects a parity bit from the received data, From the general-purpose reception port for receiving the watchdog output, A vehicle electronic control characterized by detecting an output signal of a chidog timer and detecting an abnormality of at least one of the one microcomputer and received data according to at least one of the parity bit and the output of the watchdog timer. apparatus. 4. The one microcomputer further temporarily stores frame data to be transmitted from the data transmitting means in a buffer, and the data transmitting means further comprises the buffer according to a crankshaft rotation angle. 4. The vehicle electronic control device according to claim 1, wherein the internal data is transmitted bit by bit to the general-purpose transmission port for frame data transmission. 5. The vehicle electronic device according to claim 1, further comprising an abnormality display unit connected to the abnormality detection unit and displaying an abnormality according to an output of the unit. Control device.