JPH0556666B2 - - Google Patents
Info
- Publication number
- JPH0556666B2 JPH0556666B2 JP59200886A JP20088684A JPH0556666B2 JP H0556666 B2 JPH0556666 B2 JP H0556666B2 JP 59200886 A JP59200886 A JP 59200886A JP 20088684 A JP20088684 A JP 20088684A JP H0556666 B2 JPH0556666 B2 JP H0556666B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- terminal
- electrode
- transistor device
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 claims description 36
- 239000010408 film Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 14
- 230000005611 electricity Effects 0.000 description 12
- 230000003068 static effect Effects 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜トランジスタ装置TFTを搭載
した装置で静電気等高電圧に対し保護機能を有し
たTFT装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a TFT device equipped with a thin film transistor device TFT and having a protection function against high voltages such as static electricity.
TFTは通常ガラス基板等の絶縁基板上に設け
られるため、製造プロセス中や実装工程中の静電
気で破壊しやすい問題を有していた。例えば、Si
基板に形成されたMOSトランジスタのゲート保
護には、基板との間に保護ダイオードを挿入して
いた。保護ダイオードには、ツエナ−ダイオード
の様にMOSトランジスタのVTH（しきい値電圧）
より高く、ゲート破壊電圧より低い電圧で降伏す
る特性をもたしていた。しかしながら、TFTの
場合にはPN接合ダイオードを作るのが困難であ
つたり、そのために製造工程が増えたりしてしま
う。また基板が絶縁性のため、Si基板の様な静電
気保護はとりにくい難点があつた。
Since TFTs are usually mounted on insulating substrates such as glass substrates, they have the problem of being easily destroyed by static electricity during the manufacturing and mounting processes. For example, Si
To protect the gate of the MOS transistor formed on the substrate, a protection diode was inserted between it and the substrate. The protection diode has the V TH (threshold voltage) of the MOS transistor, like a Zener diode.
It had the characteristic of breaking down at a voltage lower than the gate breakdown voltage. However, in the case of TFT, it is difficult to make a PN junction diode, and this increases the number of manufacturing steps. Also, because the substrate is insulating, it is difficult to provide static electricity protection like a Si substrate.
上述の如く、静電気保護のためTFT搭載基板
にPN接合やシヨツトキー接合ダイオードを同時
に作りこむのは、工程が増える難点があつた。
As mentioned above, creating a PN junction and a Schottky junction diode on a TFT mounting board at the same time to protect against static electricity had the disadvantage of increasing the number of steps.
本発明は、TFT製造工程と同時に製造可能な
２端子素子で、保護すべき端子に接続できる構造
を提供し、上記の問題を解決するものである。 The present invention solves the above problem by providing a two-terminal element that can be manufactured simultaneously with the TFT manufacturing process and can be connected to a terminal to be protected.
本発明は、TFT装置の外部取り出し端子間に
TFTと同時に製造可能な２端子素子を挿入する。
または、上記２端子素子を、外部取り出し端子と
共通浮遊電極との間に挿入するものである。２端
子素子は、TFTとほぼ同様な構造を有し、TFT
の半導体薄膜と同時に形成された付加半導体薄膜
を有しており、両端に第１及び第２主電極が設け
られている。また、TFTのゲート電極及びゲー
ト絶縁膜と同時に形成できる付加ゲート電極及び
付加ゲート絶縁膜を有し、遮光と場合によれば半
導体薄膜にチヤンネルを形成する。このチヤンネ
ル形成は、付加ゲート電極と第２主電極との短
絡、または容量結合による。さらに、この２端子
素子が両方向に電流を流せる様に、付加半導体薄
膜表面に絶縁膜を介して延在し、第１主電極と同
電位の第１主電極延在部を設ける。以上の２端子
素子は、内部のTFT動作に影響を与えない様、
チヤンネル長、チヤンネル幅、VTHの選択がされ
るが、さらに付加ゲート電極と第１主電極の間、
第１主電極延在部と第２主電極の間にオフセツト
領域を設定することも可能である。
The present invention provides a
Insert a two-terminal element that can be manufactured at the same time as TFT.
Alternatively, the two-terminal element is inserted between the external terminal and the common floating electrode. The two-terminal element has a structure almost similar to that of a TFT.
It has an additional semiconductor thin film formed at the same time as the semiconductor thin film, and first and second main electrodes are provided at both ends. It also has an additional gate electrode and an additional gate insulating film that can be formed simultaneously with the gate electrode and gate insulating film of the TFT, and serves to shield light and, if necessary, form a channel in the semiconductor thin film. This channel formation is due to a short circuit or capacitive coupling between the additional gate electrode and the second main electrode. Further, a first main electrode extending portion is provided on the surface of the additional semiconductor thin film, extending through an insulating film and having the same potential as the first main electrode, so that current can flow in both directions in this two-terminal element. The above two-terminal elements are designed so as not to affect the internal TFT operation.
Channel length, channel width, and V TH are selected, and in addition, between the additional gate electrode and the first main electrode,
It is also possible to set an offset region between the first main electrode extension and the second main electrode.
外部取り出し端子間、または外部取り出し端子
と共通浮遊電極の間に非線形特性を有する２端子
素子を挿入することにより、例えば１つの端子に
静電気が印加されたとき２端子素子を通して他の
端子にも静電気を分割し、実質的な印加電圧を低
くする。共通浮遊電極を設けた場合には、静電気
は２端子素子から共通浮遊電極さらに２端子素子
を通して他の複数の端子に放電されるので、さら
に印加電圧を低くすることができる。２端子素子
は、それ故TFT装置の動作電圧をより高く、破
壊電圧より低い電圧で電流が流れる様、寸法、構
造が選ばれている。
By inserting a two-terminal element with nonlinear characteristics between the external take-out terminals or between the external take-out terminal and the common floating electrode, for example, when static electricity is applied to one terminal, the static electricity is transferred to the other terminals through the two-terminal element. to lower the actual applied voltage. When a common floating electrode is provided, static electricity is discharged from the two-terminal element to a plurality of other terminals through the common floating electrode and the two-terminal element, so that the applied voltage can be further reduced. The two-terminal element is therefore dimensioned and constructed to allow the TFT device to operate at a higher operating voltage and to allow current to flow at a lower voltage than the breakdown voltage.
〔実施例〕
以下に図面に沿つて本発明を詳述する。第１図
ａは、本発明の１つのTFTに適用した１実施例
の平面図、第１図ｂは第１図ａのＢ−B′線に沿
つた断面図、第１図ｃは第１図ａのＡ−A′線に
沿つた断面図である。第１図ｂは静電気保護２端
子素子部、第１図ｃはTFT部の断面図を示す。
TFTは、ガラス、石英、セラミツクス、絶縁物
コートされた導電基板等のいわゆる絶縁基板１上
に形成され、ゲート電極２、ゲート絶縁膜３、半
導体薄膜４、ソース電極５、ドレイン電極６から
成る。本例では、TFTのソース．ゲート端子１
５，１２の間に２端子素子を挿入した例を示し
た。２端子素子は、基板１の上のゲート絶縁膜３
と同時に堆積された付加ゲート絶縁膜１３上に形
成され、TFTの半導体薄膜４と同時に堆積され
た付加半導体薄膜１４と、ソース．ドレイン電極
５，６と同時に設けられた第１主電極１０５，第
２主電極１０６から成る。この例では、第２主電
極１０６とゲート端子１２を短絡している。本例
において、例えばソース端子１５に静電気が印加
すれば、静電気はTFTのソース側と２端子素子
を通してゲート側に分流され実質的電圧は低下す
る。勿論、ゲート端子１２とドレイン端子間に２
端子素子を挿入することも有効である。半導体薄
膜４にａ−Si：Ｈ膜やａ−Si：Ｆ膜を用いたと
き、TFT及び２端子素子共に遮光を必要とする
場合があるが、図面では省略した。本例の２端子
素子は、保護すべき静電気の範囲によつて異なる
が、一般的にTFTのチヤンネル長より短い第１、
第２主電極間距離を有する。また、２端子素子の
構造は、第１図ｂに限らず、さらに他の例もあり
後述する。[Example] The present invention will be described in detail below with reference to the drawings. FIG. 1a is a plan view of one embodiment applied to one TFT of the present invention, FIG. 1b is a sectional view taken along the line B-B' of FIG. 1a, and FIG. FIG. 3 is a sectional view taken along line A-A' in FIG. FIG. 1b shows a sectional view of the electrostatic protection two-terminal element section, and FIG. 1c shows a sectional view of the TFT section.
The TFT is formed on a so-called insulating substrate 1 such as glass, quartz, ceramics, or a conductive substrate coated with an insulator, and includes a gate electrode 2, a gate insulating film 3, a semiconductor thin film 4, a source electrode 5, and a drain electrode 6. In this example, the TFT source. Gate terminal 1
An example is shown in which a two-terminal element is inserted between 5 and 12. A two-terminal element has a gate insulating film 3 on a substrate 1.
An additional semiconductor thin film 14 is formed on the additional gate insulating film 13 deposited at the same time as the semiconductor thin film 4 of the TFT, and the source. It consists of a first main electrode 105 and a second main electrode 106, which are provided at the same time as the drain electrodes 5 and 6. In this example, the second main electrode 106 and the gate terminal 12 are short-circuited. In this example, if static electricity is applied to the source terminal 15, for example, the static electricity will be shunted to the source side of the TFT and the gate side through the two-terminal element, and the actual voltage will drop. Of course, between the gate terminal 12 and the drain terminal 2
It is also effective to insert a terminal element. When an a-Si:H film or an a-Si:F film is used as the semiconductor thin film 4, both the TFT and the two-terminal element may require light shielding, but this is omitted in the drawing. The two-terminal device of this example differs depending on the range of static electricity to be protected, but generally the first terminal is shorter than the channel length of the TFT.
It has a distance between the second main electrodes. Furthermore, the structure of the two-terminal element is not limited to that shown in FIG. 1b, and there are other examples, which will be described later.
第１図ａ〜ｃでは２端子素子を外部取り出し端
子間に入れた例を示したが、第２図は外部取り出
し端子と共通浮遊電極間に入れた平面図例を示
す。第２図において、TFT装置の外部取り出し
端子１０，２０，３０，４０，……は例えばチツ
プの周辺に位置するが、チツプ外周に沿つて共通
浮遊電極１００を設け、外部取り出し端子１０，
２０，３０，４０……と共通浮遊電極１００の
各々の間に２端子素子１１０，１２０，１３０，
１４０……を挿入する。例えば、端子１０に印加
された静電気は、２端子素子１１０、共通電極１
００、２端子素子１２０，１３０，１４０……を
経て端子２０，３０，４０，……に放電し、端子
１０に接続されたTFT等を保護する。そのため、
この例での２端子素子は、外部取り出し電極側か
ら共通浮遊電極側へ電流が流れるしきい値電圧よ
りも逆方向のしきい値電圧の方が低いことが望ま
しい。共通浮遊電極は、外部取り出し端子と同時
に、またはゲート電極または他電極と同時に形成
できるので特に工程増にはならない。 1a to 1c show an example in which a two-terminal element is inserted between the external lead-out terminals, and FIG. 2 shows a plan view example in which the two-terminal element is inserted between the external lead-out terminal and the common floating electrode. In FIG. 2, the external extraction terminals 10, 20, 30, 40, . . . of the TFT device are located, for example, around the chip.
20, 30, 40... and the common floating electrode 100, two-terminal elements 110, 120, 130,
Insert 140... For example, the static electricity applied to the terminal 10 is transferred to the two-terminal element 110, the common electrode 1
00, the two-terminal elements 120, 130, 140, . . . are discharged to the terminals 20, 30, 40, . Therefore,
In the two-terminal element in this example, it is desirable that the threshold voltage in the reverse direction is lower than the threshold voltage at which current flows from the external extraction electrode side to the common floating electrode side. Since the common floating electrode can be formed at the same time as the external lead terminal, or at the same time as the gate electrode or other electrodes, there is no particular increase in the number of steps.
TFT装置に外部取り出し端子として共通接地
端子がある場合には、この端子を共通浮遊電極と
同様に利用することができる。 If the TFT device has a common ground terminal as an external terminal, this terminal can be used in the same way as a common floating electrode.
以下に２端子素子の構造例について説明する。 A structural example of a two-terminal element will be described below.
第３図ａは、本発明に使用される２端子素子の
実施例を、第３図ｂのTFTの構造と対応して示
す。TFTは逆スタガー構造例であり、基板１、
ゲート電極２、ゲート絶縁膜３、半導体薄膜４、
ソース、ドレイン電極５，６及び必要に応じ遮光
膜も含む表面保護膜７から成る。このTFTに対
応し、同時作製可能な２端子素子は、ゲート電極
２と同時に形成される付加ゲート電極１２、以下
同様に付加ゲート絶縁膜１３、付加半導体薄膜１
４、第１及び第２主電極１０５，１０６及び表面
保護膜１７より成る。この例では、付加ゲート電
極１２は電気的に浮いており、遮光の役目を果た
す。また、第１及び第２主電極１０５，１０６と
の平面的重なりを大きくすれば、容量結合で付加
ゲート電極１２の電位を制御でき付加半導体薄膜
１４にチヤンネルを形成できる。表面保護膜１７
は、SiOx、ポリイミド等絶縁膜が用いられるが
最上層に不透明導電膜を設ければ、遮光と浮遊ゲ
ートの働きを兼ねられる。 FIG. 3a shows an embodiment of a two-terminal element used in the invention, corresponding to the structure of a TFT in FIG. 3b. TFT is an example of an inverted staggered structure, with substrate 1,
gate electrode 2, gate insulating film 3, semiconductor thin film 4,
It consists of source and drain electrodes 5 and 6, and a surface protection film 7 that also includes a light shielding film if necessary. A two-terminal element that corresponds to this TFT and can be manufactured at the same time includes an additional gate electrode 12 formed at the same time as the gate electrode 2, an additional gate insulating film 13, and an additional semiconductor thin film 1.
4. Consists of first and second main electrodes 105, 106 and a surface protection film 17. In this example, the additional gate electrode 12 is electrically floating and serves as a light shield. Further, by increasing the planar overlap with the first and second main electrodes 105 and 106, the potential of the additional gate electrode 12 can be controlled by capacitive coupling, and a channel can be formed in the additional semiconductor thin film 14. Surface protective film 17
An insulating film such as SiOx or polyimide is used, but if an opaque conductive film is provided as the top layer, it can function as both a light shield and a floating gate.
第４図乃至第６図は、第３図ｂの逆スタガー型
TFTと同時に作成できる２端子素子の断面例で
ある。第４図は第３図ａの２端子素子の付加ゲー
ト電極１２と第２主電極１０６を短絡した例で、
第２主電極１０６に電圧が印加されたときTFT
のVTHとほぼ同じ値で電流が流れる。そのため静
電気保護素子と用いるときには、TFTよりチヤ
ンネル長を長く、またはチヤンネル幅を狭くする
ことが望ましい。また、第２主電極１０６を共通
浮遊電極に接続することが好ましい。 Figures 4 to 6 show the inverted stagger type of Figure 3b.
This is an example of a cross section of a two-terminal device that can be created at the same time as TFT. FIG. 4 shows an example in which the additional gate electrode 12 and the second main electrode 106 of the two-terminal device shown in FIG. 3a are short-circuited.
When voltage is applied to the second main electrode 106, the TFT
Current flows at approximately the same value as V TH . Therefore, when used as an electrostatic protection element, it is desirable to have a longer channel length or narrower channel width than TFT. It is also preferable to connect the second main electrode 106 to a common floating electrode.
第５図は、第４図の例において付加ゲート電極
１２と第１主電極１０５の間に平面的重畳をなく
し、いわゆるオフセツトを設け、見かけ上VTHを
高くした例である。 FIG. 5 shows an example in which the planar overlap between the additional gate electrode 12 and the first main electrode 105 in the example shown in FIG. 4 is eliminated, and a so-called offset is provided to increase the apparent V TH .
第６図は、さらに第５図の例において遮光膜を
第１主電極延在部２７として第１主電極１０６に
接続した例で、両方向に電流を流しやすい構造を
有している。 FIG. 6 shows an example in which the light-shielding film is further connected to the first main electrode 106 as the first main electrode extension part 27 in the example shown in FIG. 5, and has a structure that allows current to easily flow in both directions.
第７図ａとｂは、本発明をゲート電極が半導体
薄膜の上方に位置するいわゆるスタガー形TFT
（第７図ｂ）と同時搭載可能な２端子素子（第７
図ａの例である。第１図ｂ、第３図ａ、第５図及
び第６図の各構造に対応する２端子素子が可能で
あるが、第７図ａには第４図に対応する構造例を
示した。第７図ｂのスタガー形TFTは、基板１
上の遮光膜３７、絶縁膜４７、ソース・ドレイン
電極５，６、半導体薄膜４、ゲート絶縁膜３、ゲ
ート電極２、必要に応じゲート電極２と同時に形
成できるソース・ドレイン配線１５，１６から成
つている。このTFTに対応して第７図ａの２端
子素子は、遮光膜３７と同時形成できる第１主電
極延在部５７、以下同様に絶縁膜４７、第１及び
第２主電極１０５，１０６、付加半導体薄膜１
４、付加ゲート絶縁膜１３、付加ゲート電極１２
から成り、付加ゲート電極１２と第２主電極１０
６とが短絡され、必要により第１が第２主電極配
線１１５，１１６が設けられている。 Figures 7a and 7b show the present invention in a so-called staggered TFT in which the gate electrode is located above the semiconductor thin film.
(Fig. 7b) and a two-terminal element (7th
This is an example of figure a. Although two-terminal devices corresponding to the structures shown in FIGS. 1b, 3a, 5 and 6 are possible, FIG. 7a shows an example of the structure corresponding to FIG. 4. In the staggered TFT shown in Figure 7b, the substrate 1
The upper light shielding film 37, the insulating film 47, the source/drain electrodes 5, 6, the semiconductor thin film 4, the gate insulating film 3, the gate electrode 2, and the source/drain wirings 15, 16 which can be formed at the same time as the gate electrode 2 if necessary. It's on. Corresponding to this TFT, the two-terminal element shown in FIG. Additional semiconductor thin film 1
4. Additional gate insulating film 13, additional gate electrode 12
consisting of an additional gate electrode 12 and a second main electrode 10
6 are short-circuited, and the first and second main electrode wirings 115 and 116 are provided as necessary.
以上、逆スタガー形、スタガー形TFTと同時
形成可能な２端子素子の例を述べてきたが、以上
の例に限らず本発明で用いる２端子素子は基本的
にTFTと同じ構造をもつているので、他の構造
のTFTのときにも本発明は適用できる。 Examples of two-terminal elements that can be formed simultaneously with inverted staggered and staggered TFTs have been described above, but the two-terminal elements used in the present invention are not limited to the above examples and basically have the same structure as TFTs. Therefore, the present invention can also be applied to TFTs with other structures.
上述の如く、本発明によればTFT装置の特に
実装工程における静電気破壊をなくせるので最終
的な歩留りが向上し、コスト低減に役立つ。ま
た、静電気対策のために特に製造工程の増加がな
いことも他の利点である。
As described above, according to the present invention, it is possible to eliminate electrostatic damage especially in the mounting process of a TFT device, thereby improving the final yield and helping to reduce costs. Another advantage is that there is no increase in the manufacturing process for static electricity countermeasures.
本発明を主にａ−SiTFT装置について述べて
きたが、多結晶Six単結晶Siを初め他の半導体薄
膜を用いたTFTを搭載する装置についても本発
明は適用でき、その工業的意義は大きい。 Although the present invention has been mainly described with respect to an a-Si TFT device, the present invention can also be applied to devices equipped with TFTs using other semiconductor thin films, including polycrystalline Six single crystal Si, and has great industrial significance.
第１図ａは本発明の一実施例を説明するための
平面図、第１図ｂは第１図ａのＢ−B′線にそつ
た断面図であり、第１図ｃは第１図ａのＡ−
A′線にそつた断面図である。第２図は本発明の
他の実施例の平面図、第３図ａ及び第３図ｂはそ
れぞれ本発明で用いる２端子素子とTFTの構造
例の断面図、第４図乃至第６図はそれぞれ本発明
で用いる２端子素子の構造例の断面図、第７図ａ
及び第７図ｂはそれぞれ本発明による他の実施例
の２端子素子とTFTの構造例の断面図である。
１……基板、２……ゲート電極、３……ゲート
絶縁膜、４……半導体薄膜、５……ソース電極、
６……ドレイン電極、７，１７……表面保護膜、
１２……付加ゲート電極、１３……付加ゲート絶
縁膜、１４……付加半導体薄膜、１０５……第１
主電極、１０６……第２主電極、２７，５７……
第１主電極延在部、１０，２０，３０，４０……
外部取り出し電極、１００……共通浮遊電極。
FIG. 1a is a plan view for explaining one embodiment of the present invention, FIG. 1b is a sectional view taken along the line B-B' of FIG. 1a, and FIG. A- of a
It is a sectional view taken along line A'. FIG. 2 is a plan view of another embodiment of the present invention, FIGS. 3a and 3b are cross-sectional views of structural examples of a two-terminal element and a TFT used in the present invention, and FIGS. 4 to 6 are FIG. 7a is a cross-sectional view of a structural example of a two-terminal element used in the present invention, respectively.
and FIG. 7b are cross-sectional views of structural examples of a two-terminal element and a TFT according to other embodiments of the present invention, respectively. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate electrode, 3...Gate insulating film, 4...Semiconductor thin film, 5...Source electrode,
6...Drain electrode, 7,17...Surface protection film,
12...Additional gate electrode, 13...Additional gate insulating film, 14...Additional semiconductor thin film, 105...First
Main electrode, 106... Second main electrode, 27, 57...
First main electrode extension portion, 10, 20, 30, 40...
External lead-out electrode, 100... common floating electrode.
Claims (1)
ト絶縁膜、半導体薄膜、ソース電極、ドレイン電
極からなる薄膜トランジスタを搭載し、外部取り
出し端子を複数個有する薄膜トランジスタ装置に
おいて、 前記外部取り出し端子間、または、前記端子と
これに近接して設けられた共通浮遊電極との間に
は、少なくともその一か所が、付加薄膜半導体か
らなる高圧保護用の２端子薄膜半導体素子に接続
されていることを特徴とする薄膜トランジスタ装
置。 ２ 前記２端子薄膜半導体素子は、前記絶縁基板
上に重ねて形成された付加ゲート電極、および、
付加ゲート絶縁膜の上に設けられていることを特
徴とする特許請求の範囲第１項記載の薄膜トラン
ジスタ装置。 ３ 前記２端子薄膜半導体素子の一方の端子は、
前記付加ゲート電極と短絡されていることを特徴
とする特許請求の範囲第２項記載の薄膜トランジ
スタ装置。 ４ 前記付加ゲート電極がこれと短絡されていな
い２端子薄膜半導体素子の他方の端子に対して、
オフセツトを形成してことを特徴とする特許請求
の範囲第３項記載の薄膜トランジスタ装置。 ５ ２端子薄膜半導体素子の上面には、これを構
成する両端子および付加薄膜半導体にかけて絶縁
膜を形成され、かつ、前記絶縁膜の表面には、両
端子の内、いずれか一方の端子が、他方の端子表
面の絶縁膜上部にまで延在されていることを特徴
とする特許請求の範囲第２ないし第４項記載の薄
膜トランジスタ装置。[Scope of Claims] 1. A thin film transistor device including a thin film transistor comprising at least a gate electrode, a gate insulating film, a semiconductor thin film, a source electrode, and a drain electrode mounted on an insulating substrate and having a plurality of external lead-out terminals, the external lead-out terminals comprising: At least one point between the terminal and the common floating electrode provided close to the terminal is connected to a two-terminal thin film semiconductor element for high voltage protection made of an additional thin film semiconductor. A thin film transistor device characterized by: 2. The two-terminal thin film semiconductor element includes an additional gate electrode formed on the insulating substrate, and
2. The thin film transistor device according to claim 1, wherein the thin film transistor device is provided on an additional gate insulating film. 3. One terminal of the two-terminal thin film semiconductor element is
3. The thin film transistor device according to claim 2, wherein the thin film transistor device is short-circuited to the additional gate electrode. 4. With respect to the other terminal of the two-terminal thin film semiconductor element to which the additional gate electrode is not short-circuited,
4. The thin film transistor device according to claim 3, wherein an offset is formed. 5. An insulating film is formed on the upper surface of the two-terminal thin film semiconductor element, covering both terminals constituting this and the additional thin film semiconductor, and on the surface of the insulating film, one of the two terminals is formed. 5. The thin film transistor device according to claim 2, wherein the thin film transistor device extends above the insulating film on the surface of the other terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59200886A JPS6179259A (en) | 1984-09-26 | 1984-09-26 | Thin-film transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59200886A JPS6179259A (en) | 1984-09-26 | 1984-09-26 | Thin-film transistor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6179259A JPS6179259A (en) | 1986-04-22 |
| JPH0556666B2 true JPH0556666B2 (en) | 1993-08-20 |
Family
ID=16431878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59200886A Granted JPS6179259A (en) | 1984-09-26 | 1984-09-26 | Thin-film transistor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6179259A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010147032A1 (en) * | 2009-06-18 | 2010-12-23 | シャープ株式会社 | Semiconductor device |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0130955B1 (en) * | 1992-10-07 | 1998-04-14 | 쓰지 하루오 | Fabrication of a thin film transistor & production of liquid crystal display apparatus |
| US5796116A (en) | 1994-07-27 | 1998-08-18 | Sharp Kabushiki Kaisha | Thin-film semiconductor device including a semiconductor film with high field-effect mobility |
| JPH10288950A (en) * | 1997-04-14 | 1998-10-27 | Casio Comput Co Ltd | Liquid crystal display device |
| TW457690B (en) | 1999-08-31 | 2001-10-01 | Fujitsu Ltd | Liquid crystal display |
| EP2073255B1 (en) * | 2007-12-21 | 2016-08-10 | Semiconductor Energy Laboratory Co., Ltd. | Diode and display device comprising the diode |
| JP5407638B2 (en) * | 2009-07-28 | 2014-02-05 | セイコーエプソン株式会社 | Active matrix substrate, electro-optical device, and electronic apparatus |
| CN106662783B (en) | 2014-04-30 | 2018-11-13 | 夏普株式会社 | Active-matrix substrate and the display device for having the active-matrix substrate |
| JP2019197128A (en) | 2018-05-09 | 2019-11-14 | 三菱電機株式会社 | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153588A (en) * | 1980-04-25 | 1981-11-27 | Toshiba Corp | Storage device |
| JPS58180054A (en) * | 1982-04-15 | 1983-10-21 | Seiko Epson Corp | Matrix picture display |
| JPS5991479A (en) * | 1982-11-17 | 1984-05-26 | セイコーエプソン株式会社 | Active matrix substrate |
| JPS59166984A (en) * | 1983-03-14 | 1984-09-20 | 三菱電機株式会社 | Manufacture of matrix type liquid crystal display |
-
1984
- 1984-09-26 JP JP59200886A patent/JPS6179259A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153588A (en) * | 1980-04-25 | 1981-11-27 | Toshiba Corp | Storage device |
| JPS58180054A (en) * | 1982-04-15 | 1983-10-21 | Seiko Epson Corp | Matrix picture display |
| JPS5991479A (en) * | 1982-11-17 | 1984-05-26 | セイコーエプソン株式会社 | Active matrix substrate |
| JPS59166984A (en) * | 1983-03-14 | 1984-09-20 | 三菱電機株式会社 | Manufacture of matrix type liquid crystal display |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010147032A1 (en) * | 2009-06-18 | 2010-12-23 | シャープ株式会社 | Semiconductor device |
| JP5406295B2 (en) * | 2009-06-18 | 2014-02-05 | シャープ株式会社 | Semiconductor device |
| US8921857B2 (en) | 2009-06-18 | 2014-12-30 | Sharp Kabushiki Kaisha | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6179259A (en) | 1986-04-22 |
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