JPH0555240U - Memory control device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a memory control device that operates normally even if a part of the memory becomes unusable by replacing it with a normal unused bit part. [Structure] Check data CD [6: 0] is created from data D [31: 0] to be transferred, and an error is detected by comparing with the check data CD [6: 0] created previously to detect a 1-bit error. A data control circuit 3 that corrects and stores the correction information, and a bit that is abnormal in terms of hardware is determined using the correction information, and based on a select signal output from the CPU 1, the corresponding bit is set as "1" as an abnormal signal. A selection signal generation circuit 6 for outputting a data selection signal DSEL [31: 0] or a check data selection signal CDSEL [31: 0], and data for switching a data line or a check data line to a replacement data line by the abnormal signal input. A selector 11 including a selector 9 and a check data selector 10 is provided.

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a memory control device for a computer system, and more particularly to a memory control device capable of replacing a normal unused bit of the memory when a certain bit of the memory becomes unavailable.

[0002]

[Prior Art]

 In the conventional data transfer between the CPU and the memory of the computer system, if an ECC (Error Correction Code) is used as an error correction code for the data to be transferred and a 1-bit error occurs during the transfer, The location of error occurrence is known, and if there is a 2-bit error, it has a function to recognize that there is a 2-bit error.

[0003]

[Problems to be solved by the device]

 When this ECC is used, there may be a bit that is not used depending on the memory configuration, but the memory of that bit is left unused.

For example, when a 7-bit wide error correction code is combined with 32-bit wide data, if 1 memory of 1 Mbyte × 4 bits is used, 1 bit is left over.

In the memory having such a configuration, when one bit of the memory becomes unusable by hardware, a one-bit error always occurs, and even if there is a surplus of one bit, one There is no remedy other than replacing the memory (for 4 bits).

The present invention has been made in view of the above points, and an object thereof is to perform memory control so that even if a part of a memory becomes unusable, it can be replaced with a normal unused bit part. It is to realize the device.

[0007]

[Means for Solving the Problems]

 The present invention, which solves the above-mentioned problems, provides a memory control device having a function of transferring data between a CPU and a memory, and a data error correction function, and is composed of a data memory and a check data memory having redundant bits in terms of configuration. Of the check data created based on the data read from the data memory and the check data created at the time of transfer to the data memory and stored in the check data memory. A data control circuit that outputs a select signal from the CPU when it recognizes that there is an address decoder that receives the address and write signal transfer start signal from the CPU and detects the select signal sent from the CPU; If there is something wrong with the data from the CPU and the address A data select signal generation circuit that outputs a data select signal, which is a binary signal indicating an abnormality, to the abnormality bit in response to the output WP1 of the data, and the check data from the data control circuit when the check data is abnormal. A check data select signal generation circuit that outputs a check data select signal, which is a binary signal indicating abnormality, to the abnormal bit in response to the output WP2 of the address decoder, and a unit selector equal to the number of bits. Data, a data select signal and a line of replacement data, which is a surplus bit, are input, and a data selector that uses the replacement data line as a data line by the data select signal that is an error notification signal and a number of bits equal to the number of bits. It consists of unit selector and check data for each bit The check data select signal and the replacement data line that is a surplus bit are input, and a check data selector that uses the replacement data line as a data line by the check data select signal that is an abnormality notification signal is provided. It is a feature.

[0008]

[Action]

 The data control circuit reads the data from the data memory that stores the data transferred from the CPU, creates check data, and compares it with the check data from the check data memory. If there is an abnormality, the CPU outputs a select signal to the address decoder, and causes the data select signal generating circuit to output the abnormal signal to the data selector, and the check data select signal generating circuit to output the abnormal signal to the check data selector. Based on the input abnormal signal, the data selector and check data selector replace the abnormal bit line with the replacement data line and restore normal operation.

[0009]

【Example】

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the figure, reference numeral 1 is a CPU that attempts to transfer 32-bit data D [31: 0] to a memory. 2 is an address that receives the address A [31: 0], write signal WE and transfer start signal XTS (X represents negative logic) from the CPU 1 and detects the select signal sent from the CPU 1 to output the signals WP1 and WP2 It is a decoder.

When the data D [31: 0] is input from the CPU 1, 3 receives check data CD [6: 0] which is an error correction code for error detection based on the input data D [31: 0]. It is created and stored in the check data memory described later. When reading data, check data CD [6: 0] is created based on the read data D [31: 0] and read from the check data memory. A data control circuit equipped with an EDC function that compares with check data CD [6: 0] and corrects if there is an error and detects the existence of an error if there is a 2-bit error. Is.

Reference numeral 4 is a data select signal generation circuit which receives the data D [31: 0] from the CPU 1 and WP 1 output from the address decoder 2 and outputs a data select signal DSEL [31: 0]. A check data select signal generation circuit for receiving the check data CD [6: 0] from the control circuit 3 and the WP2 output from the address decoder 2 and outputting a check data select signal CDSEL [6: 0]. The circuit 4 and the check data select signal generation circuit 5 constitute a selection signal generation circuit 6.

Reference numeral 7 is a data memory composed of eight 1 Mbyte × 4 bit memories, and has a capacity of 1 Mbyte × 32 bits. 8 is a check data memory that is composed of two 1 Mbyte x 4 bit memories, has a capacity of 1 Mbyte x 8 bits, and is a check data memory that stores check data of 7 bits. There is.

9 receives the data D [31: 0] from the data control circuit 3 and transfers it to the data memory 7. At the same time, a 32-bit data select signal DSE L [31: 0] generates a data select signal. It is a data selector that inputs the replacement data output from the circuit 4 to the surplus bits of the check data memory 8.

10 receives the check data CD [6: 0] from the data control circuit 3 and transfers it to the check data memory 8. At the time of abnormality, the 7-bit check data select signal CDSEL [6: 0] outputs the check data. It is a check data selector which inputs the replacement data output from the select signal generation circuit 5 to the surplus bits of the check data memory 8. The data selector 9 and the check data selector 10 form a selector 11.

Next, the operation of the apparatus configured as described above will be described. At the time of data transfer from the CPU 1 to the data memory 7, the CPU 1 inputs data D [31: 0] to the data control circuit 3. The data control circuit 3 creates check data CD [6: 0] based on the input data D [31: 0] and stores the data D [3 1: 0] in the data memory 7 via the data selector 9. The check data CD [6: 0] is stored in the check data memory 8 via the check data selector 10.

When the CPU 1 reads the data D [31: 0] from the data memory 7, the data D [31: 0] is input to the data control circuit 3 via the data selector 9. At the same time, the check data CD [6: 0] is also read from the check data memory 8 and input to the data control circuit 3 via the check data selector 10.

The data control circuit 3 creates check data CD [6: 0] based on the input data D [31: 0], and the data D [31: 0] read from the check data memory 8 is generated. The presence or absence of an error is detected by comparing with the check data CD [6: 0] corresponding to. The data control circuit 3 has an EDC function, performs 1-bit error correction and 2-bit error detection, and stores the correction information when the 1-bit error is corrected.

The CPU 1 processes the read data D [31: 0]. If the CPU 1 determines from the correction information stored in the data control circuit 3 that the bit has an error in consideration of the error occurrence frequency of the same bit, etc., the address decoder 2 In addition to outputting the select signal, the address A [31: 0] of the bit, the write signal WE, and the transfer start signal XTS are output. The data selection signal generation circuit 4 of the selection signal generation circuit 6 receives the signal WP1 output from the address decoder 2 and the data D [31: 0] from the CPU 1 and outputs the data selection signal DSEL [31: 0]. The check data select signal generation circuit 5 outputs the check data select signal CDSEL [6] to the check data select signal generation circuit 5 which receives the signal WP2 output from the address decoder 2 and the check data CD [6: 0] from the data control circuit 3. : 0] is output to the check data selector 10.

For example, if it is determined that the circuit of the data D [31] in the data is abnormal, the data select signal DSEL [31] of the data select signal generating circuit 4 of the select signal generating circuit 6 becomes 1. Write a value like this. The data select signal generation circuit 4 inputs the data select signal DSEL [31: 0] in which the data select signal DSEL [31] is 1 and the other signals are 0 to the data selector 9 of the selector 11.

FIG. 2 is a block diagram of the configuration of the selector 11. In the figure, 9-0 to 9-31 are data D, respectively.

The data selector [0] to data D [31] input from the data control circuit 3 stores data of 1 bit each. Further, each data selector 9-0 to 9-31 has a replacement data line which is a surplus bit of the check data memory 8 and a data select signal DSEL.

Lines [0] to [31] are input. The check data selector 10 is also composed of seven selectors 10-0 to 10-6.

Since the data D [31] is abnormal, the data select signal generation circuit 4 inputs a signal such that the data select signal DSEL [31] becomes “1” to the data selector 9-31, and D [31] ], The replacement data is selected, and the surplus bits of the check data memory 8 are adopted as the memory D [31] of the data memory 7. Therefore, the function of the data memory thereafter is D of the data memory 7.

32 memories of [0] to D [30] and surplus bits of the check data memory 8. Even if an abnormal line is formed in the check data CD [6: 0], the replacement data is selected in the same manner and the check data circuit of the data control circuit 3 continues the same operation as in the normal state.

As described above, according to the present embodiment, even if an abnormality occurs in the line of the data D [31: 0] or the line of the check data CD [6: 0], the replacement data line with the surplus bit is generated. By using, the data control circuit can continue the same operation as normal without delay.

The present invention is not limited to the above embodiment. In the embodiment, the case where the replacement bit is 1 bit is shown. However, if an extra 1M × 4 bit memory is prepared, even if the previously used 1M × 4 bit memory becomes defective, it is switched by the selector. As a result, normal operation can be continued without replacing the memory.

[0024]

[Effect of the device]

 As described above in detail, according to the present invention, even if a part of the memory becomes unusable, normal unused bits can be used for replacement data, and even if an error occurs. You will be able to respond immediately, and the practical effect will be great.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a selector of an apparatus according to an embodiment of the present invention.

[Explanation of symbols]

 1 CPU 2 Address Decoder 3 Data Control Circuit 4 Data Select Signal Generation Circuit 5 Check Data Select Signal Generation Circuit 7 Data Memory 8 Check Data Memory 9 Data Selector 10 Check Data Selector 11 Selector

Claims (1)

[Scope of utility model registration request] 1. A memory control device having a function of transferring data between a CPU and a memory and a data error correction function, comprising a data memory (7) and a check data memory (8) having redundant bits in configuration. And a data (D) read from the data memory (7).
[31: 0]) based check data (CD
[6: 0]) and the check data (CD [6: 0]) created at the time of transfer to the data memory (7) and stored in the check data memory (8) are compared,
A data control circuit (3) that outputs a select signal from the CPU (1) when it is recognized that there is an abnormality, an address (A [31: 0]) from the CPU (1), and a write signal transfer start signal (XTS). In response to the CP
When there is an abnormality in the address decoder (2) for detecting the select signal sent from U (1) and the data (D [31: 0]), the CP
An error is shown 2 by receiving the data (D [31: 0]) from U (1) and the output WP1 of the address decoder (2).
Data select signal (DSEL [31:
0]) is output to the abnormal bit, and the check data (CD [6: 0]) is output from the data control circuit (3) when the check data (CD [6: 0]) is abnormal. : 0]) and the output WP2 of the address decoder (2) to output a check data select signal (CDSEL [6: 0]), which is a binary signal indicating an abnormality, to the abnormal bit concerned. A circuit (5) and a unit selector whose number is equal to the number of bits. Data (D), a data select signal (DSEL), and a line of replacement data, which is a surplus bit, are input for each bit, and an abnormality is notified. Data select signal (DSE
L) comprises a data selector (9) having a replacement data line as a data line, and unit selectors of a number equal to the number of bits, and a check data (CD), a check data select signal (CDSEL) and a surplus for each bit. And a check data selector (10) which receives the replacement data line which is a bit and which receives the replacement data line as a data line in response to a check data select signal (CDSEL) which is an abnormality notification signal. Memory control device.