JPH0546996B2 - - Google Patents

Info

Publication number
JPH0546996B2
JPH0546996B2 JP61156868A JP15686886A JPH0546996B2 JP H0546996 B2 JPH0546996 B2 JP H0546996B2 JP 61156868 A JP61156868 A JP 61156868A JP 15686886 A JP15686886 A JP 15686886A JP H0546996 B2 JPH0546996 B2 JP H0546996B2
Authority
JP
Japan
Prior art keywords
laminated
base material
guide hole
mold
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61156868A
Other languages
Japanese (ja)
Other versions
JPS6313395A (en
Inventor
Takashi Shin
Hisashi Kuwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15686886A priority Critical patent/JPS6313395A/en
Publication of JPS6313395A publication Critical patent/JPS6313395A/en
Publication of JPH0546996B2 publication Critical patent/JPH0546996B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

Description

【発明の詳細な説明】[Detailed description of the invention]

[産業上の利用分野] 本発明は多層印刷配線板の製造方法に関し、特
に多層印刷配線板の内層基板の層間位置精度を向
上させた積層方法に関する。 [従来の技術] 近年、多層印刷配線板の高密度化、高多層化の
要求が高まりつつある。このため、内層基板の積
層後の層間の位置精度、すなわち貫通スルホール
形成後、貫通スルホールと内層パターンの位置ズ
レによる短絡不良、絶縁不良が重大な問題となつ
てきている。 従来の多層印刷配線板の積層方法は、積層下金
型の周辺部に金属製のガイドピンを植立し、あら
かじめ積層金型のガイドピン位置と同一の位置に
ガイドピンと同一径のガイド孔を形成した外周基
板、内層基板およびプリプレグを所望の構成に組
み立て積層上金型を載置した後、一定の加熱、加
圧条件で積層するものであつた。 [発明が解決しようとする問題点] しかしながら、上述した従来の積層方法では、 (イ) 加熱、加圧時の内層基板(例えばガラス布基
材−エポキシ樹脂積層板)の寸法変動、 (ロ) 積層金型のピン位置精度のバラツキおよび内
層基板のガイドピン位置に対応するガイド孔の
位置精度のバラツキ等による積層組み立て時の
たわみ、ひつぱりによる内層基板の変形等によ
り積層後の内層位置精度を高精度にコントロー
ルすることは不可能であるという欠点があつ
た。 このため、例えば特願昭55−117981号では、内
層基板のガイド孔間のピツチ寸法を積層金型のガ
イドピン間のピツチ寸法に対して一定率で縮小形
成させる方法により内層基板の積層時の寸法変化
を制御することも試みられているが、最近の一層
の高多層化要求に伴い内層基板をより薄くする必
要があり、例えば板厚0.1〜0.2mmの内層基板では
積層金型への組み立て時に、ガイドピンにより内
層基板のガイド孔の変形が発生し易く、積層後の
内層基板の位置精度を改善することは困難であ
る。 [発明の従来技術に対する相違点] 上述した従来の積層方法に対し、本発明は(イ)内
層基板の中心に形成したガイド孔により複数の内
層基板の中心を整合させ、(ロ)周辺に形成した長穴
状のガイド孔により軸を整合させ、かつ、長穴方
向にひずみを逃がすという独創的内容を有する。 [問題点を解決するための手段] 前記目的を達成するため、本発明に係る多層印
刷配線板の製造方法は、外層基板、内層基板およ
びプリプレグからなる積層構成基材を積層金型上
にガイドピンを基準に組み立て積層する多層印刷
配線板の製造方法であつて、 積層構成基材は、円形のガイド孔と長穴状のガ
イド孔とを有し、 円形のガイド孔は、積層構成基材の相対する辺
の中点を結ぶ2軸が交差する該積層構成基材の中
央位置に設けられ、 長穴状のガイド孔は、積層構成基材の相対する
辺の中点を結ぶ2軸方向に沿い長穴状に形成され
て該積層構成基材の周辺部に設けられ、 積層金型は、積層構成基材の円形ガイド孔の内
周面に内接する第1のガイドピンと、長穴状ガイ
ド孔の短径方向に内接するとともに、長径方向に
クリアランスをもつ第2のガイドピンとを有し、 積層構成基材は、円形のガイド孔に積層金型の
第1のガイドピンを嵌合させて基材中央位置を固
定すると同時に、長穴状のガイド孔の短径方向に
積層金型の第2のガイドピンを内接させるととも
に長径方向にクリアランスをもたせて基材周辺部
を位置決めすることにより、複数の積層構成基材
を積層金型上に相対的に上下に積層するものであ
る。 [実施例] 以下本発明の実施例を図面を参照して説明す
る。 (実施例 1) 第1図〜第3図は本発明の第1の実施例を説明
する図である。 第1図に示すように、内層基板1aの中心すな
わち相対する辺の中点を結ぶX,Y軸の交点上に
直径4〜6mmのガイド孔2を、さらにX,Y軸の
両端部にX,Y軸方向に短径方向4〜6mm、長径
方向6〜8mmの長穴状のガイド孔3を打抜加工ま
たはルータ加工等によりそれぞれ形成する。また
外層板1b、プリプレグ1cにも内層基板1aと
同様にガイド孔2及び3を形成する。 一方、第2図に示すように積層下金型4上に、
内層基板1aの各ガイド孔2,3の位置と同一の
位置にガイド孔2に内接する外径寸法のガイドピ
ン12aおよびガイド孔3の短径方向に内接する
直径を有するガイドピン13aを植立してある。 本実施例1は厚さ5〜10mmの積層下金型4上
に、内層基板1aと同様にガイド孔2,3を形成
した外層基板1b、プリプレグ1cの複数枚およ
び複数枚の内層基板1aを、前記積層構成基板1
a,1b,1cの円形のガイド孔2および長穴状
のガイド孔3の短径方向にそれぞれ内接する外形
寸法の円形のガイドピン12a,13aを基準に
組み立て積層する。 第3図は積層下金型4上に内層基板1aを組み
立てた時のガイドピン12a,13aと内層基板
1aのガイド孔2,3の嵌合状態を示す平面図で
ある。 しかる後、その上に第2図に示す積層下金型4
のガイドピン12a,13aが嵌合するピン嵌合
孔12,13を形成した厚さ5〜10mmの積層上金
型5を載置し、積層プレス機により一定条件で加
熱、加圧して積層一体化し本発明の多層印刷配線
板を完成させる。 (実施例 2) 第4図は本発明の第2の実施例を説明する図で
あり、積層下金型4上に内層基板1aを組み立て
た状態の平面図である。 本実施例では内層基板1aの長穴状のガイド孔
3に対して長径方向に片側0.2〜0.5mmのクリアラ
ンスをとつた長穴状のガイドピン13bを用いて
第1の実施例と同様に組み立て積層一体化して本
発明の多層印刷配線板を完成させる。 なお、長穴状のガイドピン13bに嵌合する積
層上下金型4,5のピン嵌合孔は勿論長穴状のガ
イドピン13bと同一寸法を形成したものであ
る。 内層基板として厚さ0.1mmのガラス布基材−エ
ポキシ樹脂積層板を使用した10層構成での多層印
刷配線板の実施例1および実施例2での積層後の
内層位置精度の結果を、第5図に示す四隅のみに
ガイド孔14を有する内層基板11を用いて従来
方法で積層した比較例を併せて第1表に示す。
[Industrial Field of Application] The present invention relates to a method for manufacturing a multilayer printed wiring board, and particularly to a lamination method that improves the interlayer positional accuracy of inner layer substrates of a multilayer printed wiring board. [Prior Art] In recent years, there has been an increasing demand for higher density and higher multilayer multilayer printed wiring boards. For this reason, the positional accuracy between the layers of the inner layer substrate after lamination, that is, after the formation of the through hole, short circuit failures and insulation failures due to misalignment between the through hole and the inner layer pattern have become serious problems. The conventional method for laminating multilayer printed wiring boards is to install metal guide pins around the periphery of the lower lamination mold, and to drill guide holes with the same diameter as the guide pins in advance at the same positions as the guide pins in the lamination mold. After assembling the formed outer peripheral substrate, inner layer substrate, and prepreg into a desired configuration and placing a mold on top of the lamination, the layers were laminated under constant heating and pressurizing conditions. [Problems to be Solved by the Invention] However, in the conventional lamination method described above, (a) dimensional variation of the inner layer substrate (for example, glass cloth base material - epoxy resin laminate) during heating and pressurization; (b) Inner layer position accuracy after lamination may be affected due to deflection during lamination assembly due to variations in the pin position accuracy of the lamination mold, variations in the position accuracy of guide holes corresponding to the guide pin positions of the inner layer substrate, deformation of the inner layer substrate due to strain, etc. The drawback was that it was impossible to control with high precision. For this reason, for example, in Japanese Patent Application No. 55-117981, the pitch dimension between the guide holes of the inner layer substrate is reduced at a constant rate with respect to the pitch dimension between the guide pins of the lamination mold. Attempts have been made to control dimensional changes, but with the recent demand for even higher multilayers, it is necessary to make the inner layer substrate thinner. For example, for an inner layer substrate with a plate thickness of 0.1 to 0.2 mm, it is difficult to assemble it into a laminated mold. Sometimes, the guide hole of the inner layer substrate is easily deformed by the guide pin, and it is difficult to improve the positional accuracy of the inner layer substrate after lamination. [Differences between the invention and the prior art] In contrast to the conventional lamination method described above, the present invention (a) aligns the centers of a plurality of inner layer substrates with a guide hole formed at the center of the inner layer substrates, and (b) aligns the centers of a plurality of inner layer substrates with a guide hole formed at the center of the inner layer substrates, and (b) It has the original content of aligning the axes with the elongated guide hole and releasing strain in the direction of the elongated hole. [Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a multilayer printed wiring board according to the present invention includes guiding a laminated base material consisting of an outer layer substrate, an inner layer substrate, and a prepreg onto a laminated mold. A method for manufacturing a multilayer printed wiring board in which the laminated wiring board is assembled and laminated based on pins, wherein the laminated base material has a circular guide hole and an elongated guide hole, and the circular guide hole is formed in the laminated base material. The elongated guide hole is provided at the center of the laminated base material where two axes connecting the midpoints of opposite sides of the laminated base material intersect. The laminated mold includes a first guide pin inscribed in the inner peripheral surface of the circular guide hole of the laminated base material, and a first guide pin inscribed in the inner peripheral surface of the circular guide hole of the laminated base material; A second guide pin is inscribed in the short diameter direction of the guide hole and has a clearance in the long diameter direction, and the laminated base material has a circular guide hole in which the first guide pin of the laminated mold is fitted. At the same time, the second guide pin of the laminated mold is inscribed in the short diameter direction of the elongated guide hole, and a clearance is provided in the long diameter direction to position the peripheral part of the base material. Accordingly, a plurality of laminated base materials are laminated one on top of the other on a laminated mold. [Examples] Examples of the present invention will be described below with reference to the drawings. (Example 1) FIGS. 1 to 3 are diagrams illustrating a first example of the present invention. As shown in FIG. 1, a guide hole 2 with a diameter of 4 to 6 mm is formed at the center of the inner substrate 1a, that is, at the intersection of the X and Y axes connecting the midpoints of opposite sides, and at both ends of the X and Y axes. , an elongated guide hole 3 having a length of 4 to 6 mm in the minor axis direction and 6 to 8 mm in the major axis direction is formed in the Y-axis direction by punching or router machining, respectively. Guide holes 2 and 3 are also formed in the outer layer board 1b and the prepreg 1c in the same way as in the inner layer board 1a. On the other hand, as shown in FIG. 2, on the laminated lower mold 4,
A guide pin 12a having an outer diameter inscribed in the guide hole 2 and a guide pin 13a having a diameter inscribed in the short diameter direction of the guide hole 3 are planted at the same position as the guide holes 2 and 3 of the inner layer substrate 1a. It has been done. In the first embodiment, on a laminated lower mold 4 having a thickness of 5 to 10 mm, an outer layer substrate 1b in which guide holes 2 and 3 are formed in the same way as the inner layer substrate 1a, a plurality of prepregs 1c, and a plurality of inner layer substrates 1a are placed. , the laminated structure substrate 1
They are assembled and stacked on the basis of circular guide pins 12a and 13a having outer dimensions inscribed in the short diameter direction of the circular guide holes 2 and elongated guide holes 3 of a, 1b and 1c, respectively. FIG. 3 is a plan view showing how the guide pins 12a, 13a and the guide holes 2, 3 of the inner layer substrate 1a are fitted when the inner layer substrate 1a is assembled on the laminated lower mold 4. After that, the laminated lower mold 4 shown in FIG.
A mold 5 with a thickness of 5 to 10 mm formed with pin fitting holes 12 and 13 into which the guide pins 12a and 13a fit is placed on top of the laminate, and is heated and pressurized under certain conditions using a laminate press to form a laminate. to complete the multilayer printed wiring board of the present invention. (Example 2) FIG. 4 is a diagram illustrating a second example of the present invention, and is a plan view of the inner layer substrate 1a assembled on the laminated lower mold 4. As shown in FIG. This embodiment is assembled in the same manner as in the first embodiment using an elongated guide pin 13b with a clearance of 0.2 to 0.5 mm on one side in the major diameter direction with respect to the elongated guide hole 3 of the inner layer substrate 1a. The multilayer printed wiring board of the present invention is completed by laminating and integrating the layers. The pin fitting holes of the upper and lower laminated molds 4 and 5 that fit into the elongated guide pin 13b are of course formed to have the same dimensions as the elongated guide pin 13b. The results of the inner layer position accuracy after lamination in Example 1 and Example 2 of a multilayer printed wiring board with a 10-layer configuration using a glass cloth base material-epoxy resin laminate with a thickness of 0.1 mm as the inner layer substrate are as follows. Table 1 also shows a comparative example in which the inner layer substrate 11 having guide holes 14 only at the four corners shown in FIG. 5 was laminated by the conventional method.

【表】 第1表に示すように、本発明により積層後の内
層位置精度を従来の約1/2に抑えることができ、
高精度かつ信頼性の高い多層印刷配線板が製造で
きる。 [発明の効果] 以上説明したように本発明は、内層基板の中心
に形成したガイド孔により各内層基板の中心位置
が固定され、かつ各辺中点部の長穴状のガイド孔
によりX,Y軸を整合させると共に、長穴状のガ
イド孔とガイドピンの間のX,Y軸方向にクリア
ランスを設けたことにより内層基板の積層時の寸
法変動および組み立て時のひずみ等を吸収するこ
とができ、内層位置精度を向上できる効果があ
る。
[Table] As shown in Table 1, the present invention makes it possible to suppress the inner layer position accuracy after lamination to approximately 1/2 of that of the conventional method.
Highly accurate and reliable multilayer printed wiring boards can be manufactured. [Effects of the Invention] As explained above, in the present invention, the center position of each inner layer substrate is fixed by the guide hole formed at the center of the inner layer substrate, and the elongated guide hole at the midpoint of each side allows By aligning the Y axis and providing clearance in the X and Y axis directions between the elongated guide hole and the guide pin, it is possible to absorb dimensional fluctuations during stacking of the inner layer substrates and distortion during assembly. This has the effect of improving the inner layer position accuracy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の内層基板を示す平面図、第2
図は積層上下金型を示す斜視図、第3図は積層下
金型に第1図の内層基板を組み立てた状態を示す
本発明の実施例1を示す平面図、第4図は積層下
金型に第1図の内層基板を組み立てた状態を示す
本発明の実施例2を示す平面図、第5図は従来の
内層基板を示す平面図である。 1,11……内層基板、2,14……円形のガ
イド孔、3……長穴状のガイド孔、4……積層下
金型、5……積層上金型、12,13……円形の
ピン嵌合孔、12a,13a……ガイドピン、1
3b……長穴状のガイドピン。
Figure 1 is a plan view showing the inner layer substrate of the present invention, Figure 2 is a plan view showing the inner layer substrate of the present invention;
The figure is a perspective view showing the laminated upper and lower molds, FIG. 3 is a plan view showing Embodiment 1 of the present invention, showing a state in which the inner layer substrate of FIG. 1 is assembled to the laminated lower mold, and FIG. 4 is the laminated lower mold. FIG. 5 is a plan view showing a second embodiment of the present invention, showing a state in which the inner layer substrate of FIG. 1 is assembled into a mold, and FIG. 5 is a plan view showing a conventional inner layer substrate. 1, 11... Inner layer substrate, 2, 14... Circular guide hole, 3... Elongated guide hole, 4... Lamination lower mold, 5... Lamination upper mold, 12, 13... Circular Pin fitting holes, 12a, 13a...Guide pin, 1
3b...Elongated hole-shaped guide pin.

Claims (1)

【特許請求の範囲】 1 外層基板、内層基板およびプリプレグからな
る積層構成基材を積層金型上にガイドピンを基準
に組み立て積層する多層印刷配線板の製造方法で
あつて、 積層構成基材は、円形のガイド孔と長穴状のガ
イド孔とを有し、 円形のガイド孔は、積層構成基材の相対する辺
の中点を結ぶ2軸が交差する該積層構成基材の中
央位置に設けられ、 長穴状のガイド孔は、積層構成基材の相対する
辺の中点を結ぶ2軸方向に沿い長穴状に形成され
て該積層構成基材の周辺部に設けられ、 積層金型は、積層構成基材の円形ガイド孔の内
周面に内接する第1のガイドピンと、長穴状ガイ
ド孔の短径方向に内接するとともに、長径方向に
クリアランスをもつ第2のガイドピンとを有し、 積層構成基材は、円形のガイド孔に積層金型の
第1のガイドピンを嵌合させて基材中央位置を固
定すると同時に、長穴状のガイド孔の短径方向に
積層金型の第2のガイドピンを内接させるととも
に長径方向にクリアランスをもたせて基材周辺部
を位置決めすることにより、複数の積層構成基材
を積層金型上に相対的に上下に積層することを特
徴とする多層印刷配線板の製造方法。
[Claims] 1. A method for manufacturing a multilayer printed wiring board, in which a laminated base material consisting of an outer layer substrate, an inner layer substrate, and a prepreg is assembled and laminated on a lamination mold with guide pins as a reference, the laminated base material comprising: , has a circular guide hole and an elongated guide hole, and the circular guide hole is located at the center of the laminated base material where two axes connecting the midpoints of opposing sides of the laminated base material intersect. The elongated guide hole is formed in the shape of an elongated hole along the biaxial direction connecting the midpoints of opposing sides of the laminated base material, and is provided in the periphery of the laminated base material. The mold includes a first guide pin inscribed in the inner peripheral surface of the circular guide hole of the laminated base material, and a second guide pin inscribed in the short diameter direction of the elongated guide hole and having a clearance in the long diameter direction. The laminated base material has a first guide pin of the laminated mold fitted into the circular guide hole to fix the center position of the base material, and at the same time, the laminated metal mold is inserted in the short axis direction of the elongated guide hole. By inscribing the second guide pin of the mold and positioning the peripheral part of the base material with a clearance in the long diameter direction, it is possible to stack a plurality of laminated base materials vertically on a laminated mold. A method for manufacturing a multilayer printed wiring board.
JP15686886A 1986-07-03 1986-07-03 Manufacture of multilayer printed interconnection board Granted JPS6313395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15686886A JPS6313395A (en) 1986-07-03 1986-07-03 Manufacture of multilayer printed interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15686886A JPS6313395A (en) 1986-07-03 1986-07-03 Manufacture of multilayer printed interconnection board

Publications (2)

Publication Number Publication Date
JPS6313395A JPS6313395A (en) 1988-01-20
JPH0546996B2 true JPH0546996B2 (en) 1993-07-15

Family

ID=15637143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15686886A Granted JPS6313395A (en) 1986-07-03 1986-07-03 Manufacture of multilayer printed interconnection board

Country Status (1)

Country Link
JP (1) JPS6313395A (en)

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JP2001129622A (en) * 1999-10-28 2001-05-15 Honda Motor Co Ltd Positioning mechanism for superplastic forming mold
JP3931330B2 (en) * 2001-09-14 2007-06-13 ソニー株式会社 Hot press plate and card manufacturing equipment
JP2006202957A (en) * 2005-01-20 2006-08-03 Shinko Seisakusho:Kk Manufacturing method of printed circuit board with reinforcing plate
JPWO2009034819A1 (en) * 2007-09-11 2010-12-24 コニカミノルタエムジー株式会社 Microchip manufacturing method, microchip, and vacuum bonding apparatus
JP6867205B2 (en) * 2017-03-22 2021-04-28 シャープ株式会社 Cover mounting structure and display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553495A (en) * 1978-10-14 1980-04-18 Fujitsu Ltd Method of manufaturing multilayer printed circuit board
JPS6035596A (en) * 1983-08-08 1985-02-23 株式会社日立製作所 Mold for bonding laminated layer of multilayer printed circuit board
JPS60171790A (en) * 1984-02-17 1985-09-05 株式会社日立製作所 Mold for bonding laminated layer of multilayer printed circuit board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57193261U (en) * 1981-06-02 1982-12-07
JPS59194917U (en) * 1983-06-15 1984-12-25 日本電気株式会社 Resin peeling device for guide pins for laminating multilayer printed wiring boards

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553495A (en) * 1978-10-14 1980-04-18 Fujitsu Ltd Method of manufaturing multilayer printed circuit board
JPS6035596A (en) * 1983-08-08 1985-02-23 株式会社日立製作所 Mold for bonding laminated layer of multilayer printed circuit board
JPS60171790A (en) * 1984-02-17 1985-09-05 株式会社日立製作所 Mold for bonding laminated layer of multilayer printed circuit board

Also Published As

Publication number Publication date
JPS6313395A (en) 1988-01-20

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