JPH0544834B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device on an insulating film, and more particularly to a method for manufacturing a semiconductor device in which an element isolation method for isolating elements is improved.

[Technical background of the invention and its problems]

In a semiconductor device manufactured using a semiconductor thin film on an insulating film, especially in a MOS type semiconductor device, a desired field region (element isolation region) between elements is used to eliminate insulation defects due to parasitic channels and reduce parasitic capacitance. Forming a thick oxide film is being practiced. Conventionally, one of the device isolation methods using an oxide film is to etch the semiconductor thin film in the field region to separate the device formation region into islands.
There is a method of burying a field oxide film in the element isolation region using CVD technology. This element isolation method is useful for manufacturing highly integrated semiconductor devices because the surface after element isolation is approximately flat and the dimensions of the element isolation region are determined by the dimensions of the etched region that is formed with precision. It is a very useful technique.

Such a conventional device isolation method will be briefly explained with reference to FIGS. 1a to 1e. First, as shown in FIG.
A single-crystal silicon film 12 having a thickness of approximately 0.6 [μm] is prepared, and a mask material 13 is formed on the element formation region of this silicon film 12. Then,
As shown in FIG. 1B, the silicon film 12 is anisotropically etched using the mask material 13 as a mask to form element isolation regions 14. Subsequently, as shown in FIG. 1c, an insulating film 15 is buried in the element isolation region 14, and its surface is planarized.

However, this type of method has the following problems. That is, the surface of the silicon film in the element forming region and the surface of the insulating film in the element isolation region do not necessarily coincide, and the corner portion 16 around the element forming region protrudes from the surface of the insulating film, as shown in FIG. 1d. Thereafter, a gate oxide film 17 and a gate electrode 18 are formed as shown in FIG. 1e, and then a well-known method is used.
When creating a MOS transistor, the gate electrode 18
When a voltage is applied to the corner portion 16, an electric field is concentrated at the corner portion 16, a parasitic transistor is generated, and leakage current between the source and drain increases.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the generation of parasitic transistors due to electric field concentration at corners around an element formation region and improve element characteristics.

[Summary of the invention]

The gist of the present invention is to prevent an electric field from occurring at a corner around an element formation region by forming an element isolation region and embedding an insulating film after forming a gate insulating film and a gate electrode film.

That is, the present invention provides a method for manufacturing a semiconductor device on an insulating film, in which a semiconductor film is formed on the insulating film, a gate insulating film and a gate electrode film are formed on the semiconductor film, and then an element formation region is defined. A method in which the gate insulating film and the gate electrode film in the element isolation region are etched using a mask material, the insulating film is then buried in the element isolation region, and then a desired element is formed on the semiconductor film. It is.

〔Effect of the invention〕

According to the present invention, electric field concentration at the corners of the periphery of the element formation region is eliminated, so that the source-drain leakage current in the subthreshold region is reduced to a second level.
As shown in the figure, improvements are made from broken line A to solid line B. Therefore, it is possible to improve device characteristics. Furthermore, since the gate electrode can be formed in self-alignment with the element formation region, the degree of integration of the element can be improved. Furthermore, since electric field concentration around the device formation region can be suppressed, leakage current through the gate oxide film can also be suppressed, thereby preventing deterioration of device characteristics.

[Embodiments of the invention]

Figures 3a to 3d relate to an embodiment of the method of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a MOS transistor. First, as shown in FIG. 3a, a single crystal silicon film 22 is formed on an insulating film 21 such as a silicon oxide film.
is formed on this silicon film 22, for example, 20
A gate oxide film (gate insulating film) 23 of [nm] and a phosphorus-doped polysilicon electrode (gate electrode film) 24 of 0.4 [μm] are formed. Here, to form the silicon film 22, a method may be selected in which an amorphous or polycrystalline silicon film is made into a single crystal by beam annealing or the like. Next, as shown in FIG. 3b, a mask material 25 is formed to define the element formation area, and
Next, polysilicon electrode 24 and gate oxide film 23
Then, the silicon film 22 is etched by anisotropic etching to form an element isolation region 26.

Next, as shown in Figure 3cc, CVD technology is used to form an insulating film for element isolation in the element isolation region 26.
A SiO ₂ film 27 is buried and its surface is planarized.
Next, the gate electrode 24 is patterned as shown in FIG. 3d, and source/drain regions 28 are further formed in the semiconductor film 22 by diffusion. Subsequently, an insulating film 29 is deposited on the entire surface, and a contact hole is formed and an Al film 30 for wiring, etc. are formed, thereby completing a MOS transistor.

The MOS transistor thus created was able to suppress electric field concentration at the corners around the element formation region, and significantly reduce leakage current between the source and drain due to parasitic transistors.

FIGS. 4a and 4b are process sectional views for explaining another embodiment method. This embodiment differs from the previously described embodiments in that the periphery of the element formation region is oxidized to further suppress electric field concentration in the periphery. That is, in the step shown in FIG. 3b, the sides of the silicon film 22 and the polysilicon gate electrode 24 are oxidized as shown in FIG. 4a. Here, the oxidation conditions are such that the oxide film 31 resulting from the oxidation becomes thicker than the gate oxide film 23. In addition,
FIG. 4a shows a cross section perpendicular to FIG. 3b. After this, MOS
When a transistor is fabricated, the corners of the silicon film 22 and the gate electrode 24 are rounded as shown in FIG. 4b, making it possible to more effectively suppress electric field concentration at the corners around the element formation region. .

Note that the present invention is not limited to the embodiments described above. For example, the material of the gate electrode film is not limited to polysilicon, but may also be _MoSi2 or
It may also be a high melting point metal silicide such as WSi ₂ .
Furthermore, it goes without saying that a gate insulating film may be used instead of the gate oxide film. Further, the present invention can be applied not only to the production of MOS transistors but also to the production of MOS capacitors. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views for explaining the conventional element isolation method, FIG. 2 is a characteristic diagram for explaining the effects of the present invention, and FIGS. FIGS. 4a and 4b are cross-sectional views illustrating the manufacturing process of a MOS transistor according to the present invention. FIGS. 21, 27, 29, 31...Silicon oxide film (insulating film), 22...Silicon film, 23...Gate oxide film (gate insulating film), 24...Polysilicon gate electrode (gate electrode film), 25... …mask material,
26... Element isolation region, 28... Source/drain region, 30... Al film for wiring.

Claims (1)

[Claims] 1. A step of forming a semiconductor film on an insulating film, a step of forming a gate insulating film and a gate electrode film on the semiconductor film, and then forming an element using a mask material that defines an element formation region. the gate electrode in the isolation region;
A method for manufacturing a semiconductor device, comprising the steps of etching a gate insulating film and a semiconductor film, then embedding an insulating film in the element isolation region, and then forming a desired element. 2. Before the step of embedding an insulating film in the element isolation region, the semiconductor film and the gate electrode film in the element formation region are oxidized under conditions to obtain a film thickness equal to or greater than the thickness of the gate insulating film. A method for manufacturing a semiconductor device according to claim 1. 3. The semiconductor device according to claim 1 or 2, wherein in the step of forming the element, source/drain regions are formed in the semiconductor film to form a MOS transistor. manufacturing method.