JPH0536874A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a chip to be protected against warpage and prevented from deteriorating in heat dissipating properties even if it is enlarged in size by a method wherein a layer of good heat conductive material is provided only to the heat dissipating part of the rear of a board by plating, and a honeycomb layer of the same material is provided to the rest of the rear of the board. CONSTITUTION:An Au PHS(plated heat sink) 5 is selectively formed on the second surface of a board 1 aligned with an element heat releasing part and a viahole 2 through electroplating, then the board 1 is dipped with the second surface upside into a sulfurous acid Au electroplating solution, and spherical fine Au particles 6 are precipitated. Thereafter, the fine particles are brought into contact with the surface of the board or each other to form a honeycomb Au film 66 through pulse electrolysis executed with a current of low density. Stress induced by the thermal expansion difference the board and the Au film is relaxed by the voids concerned. Therefore, chip can be protected against warpage induced at stabilizing baking or die bonding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a high frequency and high output Ga having PHS.
The present invention relates to an AsIC and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 6 is a schematic sectional view showing the structure of a conventional high-frequency high-power semiconductor device, in which 1 is a semiconductor substrate.
2 is a via hole in the semiconductor substrate 1, 2a is a metal layer formed in the via hole 2, 3 is a separation groove for separating the semiconductor chip into individual substrates, 3a is a metal layer formed in the separation groove 3, Reference numeral 4 is a power supply layer for electrolytic Au plating, 5 is a plated heat sink formed by Au electrolytic plating (hereinafter referred to as AuPHS), symbol δ is a warp amount of the chip, and 1 is a long side length of the chip. There is.

First, the manufacturing method will be described. Figure 7
(a) shows an element portion 8 such as an FET, a via hole 2 and the like formed on the first surface side of the semiconductor substrate 1, a chip separation groove 3 is further provided, and a metal is provided in each of the via hole 2 and the chip separation groove 3. After forming the layers 2a and 3a, the second surface side opposite to the first surface side of the semiconductor substrate 1 is placed on the substrate 1
The state is such that the thickness is polished to about 30 μm, and then the electrolytic Au plating power supply layer 4 is formed on the second surface of the substrate 1.

Thereafter, about 40 μm is formed by Au electrolytic plating.
A thick AuPHS 5 is formed (FIG. 4 (b)), followed by dicer cutting at the separation groove 3 portion of the chip to obtain a semiconductor chip for high frequency and high output as shown in FIG.

In the above conventional semiconductor device, the PHS5
Is a function as a radiator for radiating heat generated from the element portion 8 such as FET formed on the first surface side of the semiconductor substrate 1 to the chip carrier side, and facilitates handling of the thin semiconductor substrate 1, that is, the chip. It has a function to do.

[0006]

In the conventional semiconductor device configured as described above, due to the difference in linear expansion coefficient between the substrate 1 material and the AuPHS5, the warp of the chop occurs due to the heating during die bonding. For example, about 1
0 μm thick GaAs and PHS5 are about 40 μm thick Au,
Assuming that the heating temperature at the time of die bonding is 300 ° C., the relationship between the warpage amount δ and the chip long side length 1 is shown in FIG.
become that way. That is, in the conventional semiconductor device under the above conditions, if the long side length l of the chip is set to 2 mm or more, it will not be within the assembly testable region (δ = 30 μm).
Die bonding when mounting the chip on the chip carrier,
Not only is it difficult to perform wire bonding, but the contact area between the chip and the chip carrier is reduced, and the heat dissipation characteristics are significantly degraded, causing a problem that desired RF characteristics cannot be obtained.

In addition, such a chip warp is difficult to control the amount of melted solder when the chip and the chip carrier are attached by using Au-Sn eutectic solder pellets at the time of mounting. The fact that the chip floats was also a major factor in the occurrence.

The present invention has been made in order to solve the above problems, and prevents high-frequency high-power semiconductor devices that prevent chip warpage and do not deteriorate heat dissipation characteristics even when the chip size is increased. The purpose is to obtain a manufacturing method.

[0009]

In a semiconductor device according to the present invention, a layer made of a good heat conductive material is formed by plating only on a heat radiating portion on the back surface of the substrate corresponding to a heat generating portion of a chip provided on the front surface of the substrate. A honeycomb layer formed by laminating fine particles made of a material having good thermal conductivity so as to form voids is provided on the other back surface of the substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention, the element is formed on the first surface side of the semiconductor substrate, and the feeding layer for electrolytic plating is formed on the entire second surface of the substrate.
A first layer made of a material having good thermal conductivity is formed by electrolytic plating only on a region of the second surface aligned with the heat generating portion of the element, and the first layer of the second surface of the substrate is formed. Spherical fine particles made of a material having good thermal conductivity are deposited in a region other than the formation region, and the substrate surface and the fine particles or the fine particles are brought into close contact with each other by electrolysis with a low current density to form a second honeycomb-shaped layer. Of the heat-conductive material for reinforcing the first layer and the second layer on the first layer and the honeycomb-shaped second layer formed on the second surface of the substrate. The third layer is formed.

Further, in the semiconductor device and the method of manufacturing the same according to the present invention, a layer made of a good heat conductive material is formed by plating only on the heat radiating portion on the back surface of the substrate corresponding to the heat generating portion of the chip provided on the front surface of the substrate. The graphite fiber composite plating for preventing warpage is formed on the other back surface of the substrate. In addition, Au is formed on the upper layer of the composite plating.
-Sn alloy solder layer is formed by electrolytic plating.

[0012]

In the present invention, the voids between the fine particles forming the honeycomb-shaped heat-conductive material layer are formed between the substrate material and the heat-conductive material layer provided on the back surface of the substrate during chip stabilization baking or die bonding. The stress of the good thermal conductive material layer with respect to the substrate material, which is caused by the difference in the coefficient of thermal expansion, is relaxed, and the warpage of the chip is reduced.

In the present invention, the warp can be prevented by forming the graphite fiber composite plating with a combination and a composition ratio that cancel the signs of stress on the substrate material. Further, by forming the Au—Sn alloy solder layer by electrolytic plating, the solder amount can be made constant without controlling the molten solder amount during mounting.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a sectional view showing the structure of a semiconductor device for high frequency and high output according to a first embodiment of the present invention, and FIG. 2 is a main sectional view showing an example of a method for manufacturing the semiconductor device according to the first embodiment. Is. In the figure, 1 is a semiconductor substrate, 2 is a via hole, 2a is a metal layer provided in the via hole 2,
3 is a separation groove for separating the semiconductor chip into individual substrates, 3a is a metal layer provided in the separation groove 3, 4 is a power supply layer for electrolytic Au plating, 5 is PHS formed by Au electrolytic plating, 6 Is Au fine particles, 66 is a honeycomb-shaped Au film made of Au fine particles 6, and 7 is a reinforcing Au film formed so as to cover the AuPHS 5 and the honeycomb-shaped Au film 66.

First, the manufacturing method will be described. First, an element portion 8 such as an FET, a via hole 2, and a chip separation groove 3 are formed on the first surface side of the semiconductor substrate 1, and the via hole 2 is formed.
After forming the metal layers 2a and 3a in the chip separation groove 3, respectively, the second surface side of the semiconductor substrate 1 opposite to the first surface side is polished until the thickness of the substrate 1 becomes about 30 μm. Then, a power feeding layer 4 for electrolytic Au plating is formed on the second surface of the polished substrate 1.

After that, only the portion of the second surface side opposite to the first surface side of the substrate 1 aligned with the element heating portion such as FET and the via hole portion 2 is selected by electrolytic plating. After forming the AuPHS5 having a thickness of about 40 μm, the second surface of the substrate 1 is placed upward in a sulfite-based Au electroplating solution, and the above-mentioned sulfite-based Au electroplating solution is added by adding a trace amount of acid. And the particle size is about 0.5 to 1
The spherical Au fine particles 6 of μm are generated, and the spherical Au fine particles 6 are settled on the substrate (FIG. 2 (a)).

Then, the Au particles 6 are deposited on the second surface of the substrate 1 at least 50 μm or more (FIG. 2 (b)),
Thereafter, the fine particles or the fine particles are brought into close contact with the substrate surface by pulse electrolysis with a low current density to form a honeycomb-shaped Au film 66. Subsequently, the honeycomb-shaped Au film 66 formed on the second surface of the substrate 1 is polished to a thickness of about 4
It is set to 0 μm (FIG. 2 (c)).

After that, AuPHS5 and honeycomb-shaped Au
A reinforcing Au film 7 having a thickness of about 3 μm is formed on the film 66 by electrolytic plating, and the chip is cut in the chip separation groove 3 by dicer cutting to perform chip separation to obtain a semiconductor device as shown in FIG.

In the semiconductor device configured as described above, the void portion of the honeycomb-shaped Au film 66 is heated by the substrate material and the Au film when the semiconductor device, that is, the semiconductor chip is subjected to stabilization baking or die bonding. It has the effect of relieving the stress of the Au film on the substrate material caused by the difference in expansion.

Therefore, according to this embodiment, the warp of the chip at the time of stabilizing baking and die bonding is suppressed,
When mounting a chip on a chip carrier, die bonding and wire bonding can be easily performed. Further, even if the size of the chip is increased, the contact area between the chip and the chip carrier can be increased, so that the heat dissipation characteristic can be improved and the one having desired RF characteristics can be obtained. Although Au plating is used as PHS in this embodiment, other metal material or alloy having good heat conductivity such as Cu may be used.

3 and 4 are sectional views showing the structure of a high-frequency high-power semiconductor device according to the second embodiment of the present invention, and FIG. 5 is a main sectional view showing a manufacturing method. In the figure, 1 is G
aAs substrate, 8 is an element part such as FET, 2 is a via hole, 4 is a first Au plating layer, 10 is an Au-graphite composite plating layer, 10a is a graphite fiber, 10b is a plating metal layer, 5 is AuPHS, 11 is Au. -Sn alloy plating layer.

FIG. 3 shows the FE on the first surface side of the semiconductor chip.
An AuPHS5 having a thickness of about 40 μm is formed on a portion of the chip that is aligned with the element heating portion such as T8 and the via hole portion 2 on the second surface side opposite to the first surface side. About 40μ on the second surface side of the substrate of
m of Au-graphite composite plating layer 10 is arranged. The linear expansion coefficient at room temperature is 6 for GaAs, 14.2 for Au, and 3.1 for graphite ([× 10
^-6 ° C. ⁻¹ ] The following units are omitted.) Therefore, the plating metal 10b is Au, and the graphite fibers 10a and Au in the dispersion plating layer 10 have a composition ratio of about 7: 3, respectively. In this case, the signs of the stress applied to the substrate material 1 are offset from each other, and the chip warp can be reduced.

In the graphite composite plating 10, the plating metal layer 10b is made of Ni (coefficient of linear expansion 13.4).
The same effect can be obtained by setting the composition ratio of the graphite fiber 10a and the plated metal 10b to about 13: 7. However, in this case, in order to reduce the conductor loss of the microstrip line as much as possible, it is necessary to take a structure in which the first Au plating layer 4 having a thickness of about 1 to 2 μm having good electrical conductivity is arranged under the dispersion plating 10.

The structure shown in FIG. 4 corresponds to the structure A of the second embodiment.
A on top of uPHS5 and graphite composite plating layer 10
The u-Sn composite plating layer 11 is arranged.

Next, the formation process flow will be described. FIG. 5 (a) shows an element portion 8 such as a FET and a via hole 2
The second surface of the GaAs substrate 1 on which the above are formed is polished to about 30 μm, and then the first Au plating layer 4 is formed. Then, selective electroplating using the first Au plating layer 4 as a power supply layer and a photoresist as a mask forms an AuPHS having a thickness of about 40 μm ((FIG. 5
(b)). In this state, the fiber 10a, which is woven with graphite wire having a thickness of about 6 to 8 μm, the surface of which is previously coated with electroless Ni plating, is attached to the second surface of the substrate 1 by the surface tension of water so as to avoid the PHS. At the same time, it is physically fixed so that the position does not shift (Fig. 5 (c)). After that, electrolytic plating of Au, Cu, Ni or the like is performed to bring them into close contact. At this time, the plating solution permeates between the graphite fibers, but since the plating reaction is diffusion-controlled, pulse plating is preferable as the plating method. Thus, the Au-graphite composite plating layer 10 is obtained (FIG. 5 (d)).
). The composite plating layer 10 is flattened (FIG. 5 (e)).
), The structure shown in FIG. 3 is obtained.

When the chip separation is performed after the state of FIG. 5 (e) and the Au--Sn alloy plating layer 11 is formed (FIG. 5 (f)), the structure of FIG. 4 is obtained. The Au—Sn alloy plating layer 11 is formed by adjusting the plating current density so that the composition ratio is Au: Sn = 8: 2.

In the semiconductor device constructed as described above, the AuP is formed on the portion of the second surface side opposite to the first surface side of the substrate aligned with the element heating portion such as FET.
Since the HS is formed and the other part of the second surface of the substrate is provided with a graphite fiber composite plating having a thermal expansion coefficient matched to that of the substrate material, chip warpage during mounting is reduced.

By forming the Au--Sn alloy solder by electrolytic plating, the chip can be attached to the chip carrier in a flat state without controlling the amount of solder during mounting.

Although Au plating is used as PHS in this embodiment, other metal material or alloy having good heat conductivity such as Cu may be used. Ga is used as a semiconductor substrate.
Although the As substrate is used, a semiconductor substrate such as a Si substrate, an InP substrate, or a Si substrate on which a GaAs layer is epitaxially grown, or a ceramic substrate may be used. Further, although graphite fiber is used, any fiber made of a material having a linear expansion coefficient of about 3 × 10 ⁻⁶ may be used.

[0030]

As described above, according to the present invention, the portion of the second surface side of the substrate, which is aligned with the element heat generating portion such as the FET, opposite to the first surface side, is preferably plated. Since a layer made of a heat conductive material is formed and a layer made of a good honeycomb heat conductive material is arranged on the other portion of the second surface of the substrate, the voids of the fine particles forming the honeycomb layer are formed. Part relaxes the stress of the good thermal conductive material layer on the substrate material caused by the difference in the thermal expansion coefficient between the substrate material and the good thermal conductive material layer during die bonding of the chip, and as a result, heat dissipation from the element heat generating part The warp of the chip can be reduced without impairing the effect, and the chip size can be increased.

Further, according to the present invention, the portion of the second surface side opposite to the first surface side of the substrate, which is aligned with the element heat generating portion such as the FET, has good thermal conductivity by plating. Since a layer made of a material is formed and a second layer formed by graphite fiber composite plating in which the coefficient of thermal expansion is adjusted to the substrate material is arranged on the other portion of the second surface of the substrate, the device heat generation is improved. The warp of the chip can be reduced without impairing the heat radiation effect from the part, and the size of the chip can be increased.

By forming the Au—Sn alloy solder by electrolytic plating, the chip can be attached to the carrier in a flat state without controlling the amount of solder during mounting, and the chip warpage can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a high frequency and high power semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the high-frequency high-power semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a configuration of a high frequency and high power semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing the structure of a high frequency and high power semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the high frequency high power semiconductor device according to the second embodiment of the invention.

FIG. 6 is a sectional view showing a conventional high-frequency high-power semiconductor device.

FIG. 7 is a cross-sectional view showing a method of manufacturing a conventional high-frequency high-power semiconductor device.

FIG. 8 is a diagram showing a relationship between a warp amount and a long side length of a conventional high frequency and high output semiconductor chip.

[Explanation of symbols]

1 GaAs substrate 2 via holes 4 First Au plating layer 5 AuPHS 8 FET and other elements 10 Au-graphite fiber composite plating layer 10a Graphite fiber 10b Plating metal in composite plating 11 Au-Sn alloy solder plating layer δ Chip warp amount l Chip long side length

Claims (5)

[Claims] 1. An element is formed on a first surface side of a substrate,
In a semiconductor device having a heat radiating means on a second surface side opposite to the first surface side, the heat radiating means is a region aligned with a heat generating portion of the element on the second surface of the substrate. A first layer made of a good heat conductive material formed by plating, and a spherical layer made of a good heat conductive material on a portion other than the first layer forming region on the second surface of the substrate. A semiconductor device comprising a honeycomb-shaped second layer formed by laminating fine particles such that voids are formed between the fine particles. 2. A method of manufacturing a semiconductor device having an element on a first surface side of a substrate and having a heat radiating means on a second surface side opposite to the first surface side, the method comprising: A step of forming an element on the first surface side, a step of forming a power feeding layer for forming electrolytic plating on the entire second surface of the substrate, and a step of arranging a heat generating portion of the element on the second surface. A step of forming a first layer made of a material having good thermal conductivity by electrolytic plating only in the combined area; and a step of good thermal conductivity in an area other than the first layer forming area on the second surface of the substrate. Deposited spherical particles made of a flexible material,
A step of bringing the fine particles or the fine particles into close contact with the substrate surface by electrolysis with a low current density to form a honeycomb-shaped second layer; and the first layer formed on the second surface of the substrate. Forming a third layer made of a good heat conductive material for reinforcing the first layer and the second layer on the upper and the honeycomb-shaped second layer. Device manufacturing method. 3. An element is formed on the first surface side of the substrate,
In a semiconductor device having a heat radiating means on a second surface side opposite to the first surface side, the heat radiating means is a region aligned with a heat generating portion of the element on the second surface of the substrate. In addition, the substrate material and the linear expansion coefficient were adjusted to the first layer formed by plating and made of a material having good thermal conductivity, and the portion other than the first layer formation region on the second surface of the substrate. A semiconductor device comprising a second layer formed by graphite fiber composite plating. 4. The Au-Sn alloy plating film is formed on the composite plating film by an electrolytic plating method so as to form a eutectic alloy having a composition ratio of 8: 2. Semiconductor device. 5. A method of manufacturing a semiconductor device having an element on a first surface side of a substrate and having a heat radiation means on a second surface side opposite to the first surface side, the method comprising: A step of forming an element on the first surface side, a step of forming a power feeding layer for forming electrolytic plating on the entire second surface of the substrate, and a step of arranging a heat generating portion of the element on the second surface. A step of forming a first layer made of a material having good thermal conductivity by electrolytic plating only in the combined area; and a metal coating on an area other than the first layer forming area on the second surface of the substrate. And a step of performing electroplating in a state in which the graphite fibers are pressure-bonded, adhering the graphite fibers to each other while filling the gaps between the graphite fibers, and a step of polishing and flattening the second surface of the substrate. Of manufacturing a semiconductor device.