JPH05343633A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH05343633A
JPH05343633A JP15040792A JP15040792A JPH05343633A JP H05343633 A JPH05343633 A JP H05343633A JP 15040792 A JP15040792 A JP 15040792A JP 15040792 A JP15040792 A JP 15040792A JP H05343633 A JPH05343633 A JP H05343633A
Authority
JP
Japan
Prior art keywords
layer
electrode
semiconductor device
electrodes
increased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15040792A
Other languages
Japanese (ja)
Inventor
Fumitake Mieno
文健 三重野
Atsuhiro Tsukune
敦弘 筑根
Hiroshi Miyata
宏志 宮田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15040792A priority Critical patent/JPH05343633A/en
Publication of JPH05343633A publication Critical patent/JPH05343633A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To realize a semiconductor device wherein an antifuse of low writing voltage is used as a memory cell, by changing contents of germanium. CONSTITUTION:In the initial state that a voltage is applied across a first electrode 2 and a second electrode 4, a current flowing through an a-Si layer 3 is uniform, and the layer 3 is kept at a low temperature T1. When the central part of the layer 3 begins to be heated at T2, conductivity is increased, and a locally heated region (b) is formed, the electric field at the central part is decreased, the electric field in the vicinities of the first and the second electrodes 2, 4 are increased, and a region (a) where space charges are locally exist appears. As a result, the electric field is distorted, the electric resistance R of the a-Si layer 3 becomes low at the central part, and maximum points are generated in the vicinities of the electrodes 2, 4. When the electric resistance relatively increases, the heated region propagates to the vicinities of the electrodes 2, 4, and the temperature is increased at T2, so that the conductivity of the layer 3 is increased. Hence, the a-Si lawyer 3 between the first and the second electrodes are turned into a conduction state, and the writing voltage is adjusted, so that the writing voltage of a semiconductor device can be lowered.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、アモルファスシリコン
層を用いたアンチヒューズを記憶セルとして有する半導
体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an antifuse using an amorphous silicon layer as a memory cell.

【0002】[0002]

【従来の技術】従来から、配線と配線の間にアモルファ
スシリコン(a−Si)層を介挿したアンチヒューズを
記憶セルとして用いた1回書込み用ROM、ゲートアレ
イ等の半導体装置が知られていた。
2. Description of the Related Art Conventionally, semiconductor devices such as a one-time write ROM and a gate array using an antifuse having an amorphous silicon (a-Si) layer interposed between wirings as a storage cell have been known. It was

【0003】これらの半導体装置においては、この記憶
セルであるアンチヒューズを絶縁状態から導電状態に変
換して情報を書き込むには、例えば、一辺0.8μmの
角形で厚さが1000Åのセルに対して10V程度の電
圧が必要であった。この電圧はa−Si層中のElec
trothermal現象によって決定される。
In these semiconductor devices, in order to convert the antifuse, which is the memory cell, from the insulating state to the conductive state and write information, for example, for a cell with a side of 0.8 μm and a thickness of 1000 Å Therefore, a voltage of about 10V was required. This voltage is equal to the Elec in the a-Si layer.
It is determined by the trothermal phenomenon.

【0004】[0004]

【発明が解決しようとする課題】したがって、従来のa
−Si層を介挿したアンチヒューズを記憶セルとして用
いたROM、ゲートアレイ等の半導体装置にデータやプ
ログラムを書き込むには10V程度の電圧をかけなけれ
ばならなかった。
Therefore, the conventional a
In order to write data or programs to a semiconductor device such as a ROM or a gate array using an anti-fuse with a -Si layer interposed as a memory cell, a voltage of about 10V has to be applied.

【0005】しかし配線が微細化され、回路素子が低電
圧化された装置においては、配線間の耐圧あるいは回路
素子の耐圧が低下しているから、これらの回路等に書込
み電圧が悪影響を与えるのを防ぐために、書込み電圧を
より低下することが期待されている。本発明は、書込み
電圧が低いアンチヒューズを記憶セルとして用いたRO
M、ゲートアレイ等の半導体装置を提供することを目的
とする。
However, in a device in which wirings are miniaturized and circuit elements are lowered in voltage, the withstand voltage between wirings or the withstand voltage of circuit elements is lowered, and therefore the write voltage adversely affects these circuits and the like. To prevent this, it is expected that the write voltage will be further lowered. The present invention is an RO using an antifuse with a low write voltage as a memory cell.
It is an object to provide a semiconductor device such as M and a gate array.

【0006】[0006]

【課題を解決するための手段】本発明にかかる半導体装
置においては、配線と配線の間にゲルマニウムを含有す
るアモルファスシリコン層を介挿したアンチヒューズを
記憶セルとして有する構成を採用した。
In a semiconductor device according to the present invention, a structure having an anti-fuse having an amorphous silicon layer containing germanium interposed between wirings as a storage cell is adopted.

【0007】また本発明にかかる、配線と配線の間にゲ
ルマニウムを含有するアモルファスシリコンを介挿した
アンチヒューズを記憶セルとして有する半導体装置の製
造方法においては、ゲルマニウムの含有量を変えること
によって、アンチヒューズを絶縁状態から導電状態に変
換する書込み電圧を調節する過程を採用した。
Further, according to the present invention, in the method of manufacturing a semiconductor device having an anti-fuse in which amorphous silicon containing germanium is inserted between wirings as a memory cell, the anti-fuse is changed by changing the content of germanium. The process of adjusting the write voltage to convert the fuse from the insulated state to the conductive state is adopted.

【0008】[0008]

【作用】図1は、本発明のシリコンアンチヒューズの原
理説明図である。この図の横軸はゲルマニウムの含有量
(Ge/Si+Ge)、縦軸は温度(℃)であり、図中
の曲線は絶縁状態であるアモルファスから導電状態であ
る多結晶に変換する固相成長開始ラインを示している。
FIG. 1 is a diagram for explaining the principle of the silicon antifuse of the present invention. The horizontal axis of this figure is the content of germanium (Ge / Si + Ge) and the vertical axis is the temperature (° C). Shows the line.

【0009】この図の固相成長開始ラインによると、a
−Si層中のゲルマニウムの含有量が多くなるにしたが
って、絶縁状態であるアモルファスから導電状態である
多結晶に変換する温度が低下することがわかる。
According to the solid-phase growth start line of this figure, a
It can be seen that as the content of germanium in the -Si layer increases, the temperature at which the amorphous state, which is the insulating state, is changed to the polycrystalline state, which is the conductive state, decreases.

【0010】図2(A)〜(C)、図3(D),(E)
は、a−Si層のElectrothermal現象の
説明図である。この図を参照して、本発明の作用効果を
生じるa−Si層のElectrothermal現象
を説明する(J.Vac.Aci.Technol.,
Vol.17,No.1,Jan./Feb.1980
参照)。
2A to 2C, 3D and 3E.
FIG. 4 is an explanatory diagram of an Electrothermal phenomenon of an a-Si layer. With reference to this figure, the Electrothermal phenomenon of the a-Si layer which produces the effect of the present invention will be described (J. Vac. Aci. Technol.,
Vol. 17, No. 1, Jan. / Feb. 1980
reference).

【0011】この図においては、1は基板、2は第1電
極、3はa−Si層、4は第2電極、T1 ,T2
2 ’は温度、aは空間電荷極在領域、bは極在加熱領
域、Rは電気抵抗である。
In this figure, 1 is a substrate, 2 is a first electrode, 3 is an a-Si layer, 4 is a second electrode, T 1 , T 2 ,
T 2 'is temperature, a is space charge local area, b is local heating area, and R is electrical resistance.

【0012】この試料においては、基板1の上に第1電
極2が形成され、その上にa−Si層3が形成され、さ
らにその上に第2電極4が形成されている。
In this sample, the first electrode 2 is formed on the substrate 1, the a-Si layer 3 is formed thereon, and the second electrode 4 is further formed thereon.

【0013】〔スイッチ前の初期状態〕この試料の第1
電極と第2電極の間にある電圧を印加した初期状態で
は、a−Si層に流れる電流は一様で、a−Si層3は
低温(T1 )に保たれる(図2(A)参照)。
[Initial state before switch] First of this sample
In the initial state in which a voltage is applied between the electrode and the second electrode, the current flowing through the a-Si layer is uniform and the a-Si layer 3 is kept at a low temperature (T 1 ) (FIG. 2 (A)). reference).

【0014】〔スイッチの先駆状態〕前記の一様な電流
によって、a−Si層3の中心部が加熱(T2 )され始
めてその領域の導電度が上昇して極在加熱領域bが形成
され、そのためにa−Si層3の中央部の電界が低下す
る。そして相対的に低温(T1 )である第1電極2と第
2電極4の近傍の電界が上昇して、第1電極2と第2電
極4の近傍に空間電荷極在領域aが現れる(図2(B)
参照)。
[Prior state of switch] The central portion of the a-Si layer 3 begins to be heated (T 2 ) by the above-mentioned uniform current, the conductivity of the region is increased, and the localized heating region b is formed. Therefore, the electric field at the center of the a-Si layer 3 is lowered. Then, the electric field in the vicinity of the first electrode 2 and the second electrode 4 having a relatively low temperature (T 1 ) rises, and the space charge local area a appears in the vicinity of the first electrode 2 and the second electrode 4 ( Figure 2 (B)
reference).

【0015】誘起された空間電荷が極在することによっ
て電界が歪められ、a−Si層3の電気抵抗Rは、a−
Si層の中央で低く、第1電極2と第2電極4の近傍に
極大点を生じる(図2(C)参照)。
Due to the presence of the induced space charges, the electric field is distorted, and the electric resistance R of the a-Si layer 3 becomes a-
It is low at the center of the Si layer, and a maximum point occurs near the first electrode 2 and the second electrode 4 (see FIG. 2C).

【0016】第1電極2と第2電極4の近傍の電気抵抗
が相対的に上昇すると、加熱領域がより第1電極2と第
2電極4の近くに伝播し、この領域の温度を上げて(T
2 ’)、a−Si層3全体の導電度を上昇させる(図2
(D)参照)。
When the electric resistance in the vicinity of the first electrode 2 and the second electrode 4 relatively rises, the heating region propagates closer to the first electrode 2 and the second electrode 4, and the temperature in this region is raised. (T
2 '), to increase the conductivity of the entire a-Si layer 3 (Fig. 2
(D)).

【0017】 〔スイッチ状態〕(図2(E)参照)上記のa−Si層
3の導電度の上昇過程は、a−Si層3全体の雪崩的な
導電度の上昇をもたらし、第1電極2と第2電極間4の
a−Si層3を導電状態に変換する。
[Switched State] (See FIG. 2E) The above-described process of increasing the conductivity of the a-Si layer 3 causes an avalanche-like increase in conductivity of the entire a-Si layer 3 and thus the first electrode. The a-Si layer 3 between the second electrode 4 and the second electrode 4 is converted into a conductive state.

【0018】本発明の作用効果に関与するメカニズム
は、ダングリングボンドが水素によって補償されて絶縁
状態を呈しているa−Si層3に電流を流し、この電流
によって生じる抵抗加熱(ジュール熱)によって、この
水素を離脱させて多結晶化して導電状態に転換する過程
である。すなわち、Geの含有量によって多結晶化する
固体成長温度がシフトする現象を利用して、書込み電圧
を調節するものである。
The mechanism involved in the function and effect of the present invention is that a dangling bond is compensated by hydrogen and an electric current is passed through the a-Si layer 3 which is in an insulating state, and resistance heating (Joule heat) is caused by this electric current. This is a process in which this hydrogen is released, polycrystallized, and converted into a conductive state. That is, the writing voltage is adjusted by utilizing the phenomenon that the solid growth temperature at which polycrystallization occurs shifts depending on the Ge content.

【0019】[0019]

【実施例】本発明の一実施例を説明する。この実施例
の、配線と配線の間にゲルマニウムを含有するアモルフ
ァスシリコン層を介挿したアンチヒューズを記憶セルと
する半導体装置を製造するにあたっては、基板上に第1
の方向の延在する複数の配線層を形成し、その上に、基
板温度を450℃に保ち、SiH4 を30sccmの流
量で、GeH4 を0〜40sccmの流量で、N2 を5
00sccmの流量で反応室に供給し、この反応室中の
圧力を100Torrにした状態でCVDによってa−
Si層を形成し、その上に、第1の方向と交差する第2
の方向に延在する複数の配線を形成した。
EXAMPLE An example of the present invention will be described. In manufacturing a semiconductor device having a memory cell of an antifuse in which an amorphous silicon layer containing germanium is interposed between wirings of this embodiment, the first device is formed on a substrate.
A plurality of wiring layers extending in the direction of, the substrate temperature is maintained at 450 ° C., SiH 4 at a flow rate of 30 sccm, GeH 4 at a flow rate of 0 to 40 sccm, and N 2 at 5
It is supplied to the reaction chamber at a flow rate of 00 sccm, and the pressure in the reaction chamber is set to 100 Torr, and a-
A Si layer is formed on which a second crossing first direction is formed.
A plurality of wirings extending in the direction of are formed.

【0020】図4は、a−Si層中のGe含有率と書込
み電圧の関係図である。この図にみられるように、a−
Si層中のGe含有率(Ge/Si+Ge)が増大する
にともなって書込み電圧が低下するから、Ge含有率を
変化することによって書込み電圧を図示された範囲内で
調節することができる。
FIG. 4 is a diagram showing the relationship between the Ge content in the a-Si layer and the write voltage. As seen in this figure, a-
Since the write voltage decreases as the Ge content (Ge / Si + Ge) in the Si layer increases, the write voltage can be adjusted within the range shown by changing the Ge content.

【0021】なお、上記の実施例においては配線と配線
の間の接続について説明したが、配線のうち一方を基板
に置き換えて、配線と基板の間の接続に適用できること
はいうまでもない。
Although the connection between the wirings has been described in the above embodiment, it is needless to say that one of the wirings may be replaced with a substrate to apply the connection between the wirings and the substrate.

【0022】[0022]

【発明の効果】以上説明したように、本発明によると書
込み電圧を前記の範囲で調節することができるため、R
OM等の半導体装置の書込みを低電圧化することができ
る。
As described above, according to the present invention, since the write voltage can be adjusted within the above range, R
It is possible to reduce the voltage for writing in a semiconductor device such as an OM.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のシリコンアンチヒューズの原理説明図
である。
FIG. 1 is a diagram illustrating the principle of a silicon antifuse of the present invention.

【図2】(A)〜(C)は、a−Si層のElectr
othermal現象の説明図(1)である。
FIGS. 2A to 2C show an electr of an a-Si layer.
It is explanatory drawing (1) of the general phenomenon.

【図3】(D),(E)は、a−Si層のElectr
othermal現象の説明図(2)である。
3 (D) and (E) are Electr of a-Si layer.
It is explanatory drawing (2) of the general phenomenon.

【図4】a−Si層中のGe含有率と書込み電圧の関係
図である。
FIG. 4 is a relationship diagram between a Ge content rate in an a-Si layer and a write voltage.

【符号の説明】[Explanation of symbols]

1 基板 2 第1電極 3 a−Si層 4 第2電極 T1 ,T2 ,T2 ’ 温度 a 空間電荷極在領域 b 極在加熱領域 R 電気抵抗1 substrate 2 first electrode 3 a-Si layer 4 second electrodes T 1, T 2, T 2 ' temperature a space charge pole standing area b Gokuzai heating region R the electrical resistance

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 配線と配線の間、または、配線と基板の
間にゲルマニウムを含有するアモルファスシリコン層を
介挿したアンチヒューズを記憶セルとして有することを
特徴とする半導体装置。
1. A semiconductor device having an antifuse as a memory cell, in which an amorphous silicon layer containing germanium is interposed between wirings or between wirings and a substrate.
【請求項2】 配線と配線の間、または、配線と基板の
間にゲルマニウムを含有するアモルファスシリコン層を
介挿したアンチヒューズを記憶セルとして有する半導体
装置の製造方法であって、該ゲルマニウムの含有量を変
えることによって、該アンチヒューズを絶縁状態から導
電状態に変換する書込み電圧を調節することを特徴とす
る半導体装置の製造方法。
2. A method of manufacturing a semiconductor device having an antifuse as a memory cell, wherein an amorphous silicon layer containing germanium is interposed between wirings or between wirings and a substrate, wherein the germanium is contained. A method of manufacturing a semiconductor device, wherein a write voltage for converting the antifuse from an insulating state to a conductive state is adjusted by changing an amount.
JP15040792A 1992-06-10 1992-06-10 Semiconductor device and its manufacture Withdrawn JPH05343633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15040792A JPH05343633A (en) 1992-06-10 1992-06-10 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15040792A JPH05343633A (en) 1992-06-10 1992-06-10 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH05343633A true JPH05343633A (en) 1993-12-24

Family

ID=15496288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15040792A Withdrawn JPH05343633A (en) 1992-06-10 1992-06-10 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH05343633A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859562A (en) * 1996-12-24 1999-01-12 Actel Corporation Programming circuit for antifuses using bipolar and SCR devices
EP1970956A2 (en) 2007-03-14 2008-09-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7994607B2 (en) 2007-02-02 2011-08-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8519509B2 (en) 2010-04-16 2013-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859562A (en) * 1996-12-24 1999-01-12 Actel Corporation Programming circuit for antifuses using bipolar and SCR devices
US7994607B2 (en) 2007-02-02 2011-08-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
EP1970956A2 (en) 2007-03-14 2008-09-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2008258598A (en) * 2007-03-14 2008-10-23 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
US8981524B2 (en) 2007-03-14 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a plurality of antifuse memory cells
US9356030B2 (en) 2007-03-14 2016-05-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device having antifuse with semiconductor and insulating films as intermediate layer
US8519509B2 (en) 2010-04-16 2013-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
EP0078165B1 (en) A semiconductor device having a control wiring layer
US3771026A (en) Conductive region for semiconductor device and method for making the same
JP3256603B2 (en) Semiconductor device and manufacturing method thereof
US5786268A (en) Method for forming programmable interconnect structures and programmable integrated circuits
KR101009512B1 (en) Phase change current density control structure
US5557136A (en) Programmable interconnect structures and programmable integrated circuits
KR0162073B1 (en) Programmable low impedance interconnect circuit element
US5314840A (en) Method for forming an antifuse element with electrical or optical programming
TW564427B (en) One time programmable fuse/anti-fuse combination based memory cell
KR100299340B1 (en) Antifuse structure and process
US5049970A (en) High resistive element
JPS60254662A (en) Improved thin film field effect transistor compatible with integrated circuit and method of producing same
JP2535084B2 (en) Method for manufacturing semiconductor device
US20060163553A1 (en) Phase change memory and fabricating method thereof
TW201117367A (en) Semiconductor memory device and manufacturing method thereof
JPH05343633A (en) Semiconductor device and its manufacture
US20060226410A1 (en) Heating phase change material
JPH08241997A (en) Thin film transistor
KR940008564B1 (en) Semiconductor device and manufacturing method thereof
US11004511B2 (en) Memory device having separate programming and resistance readout control
CN1606157A (en) Semiconductor device with polysilicon fuse and method for trimming the same
JP2538881B2 (en) Method for manufacturing semiconductor device
CN102136488A (en) Organic light emitting diode display and method for manufacturing the same
US3343254A (en) Method of narrowly spacing electrically conductive layers
JPH0332228B2 (en)

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990831