JPH05326976A - Semiconductor memory and manufacture thereof - Google Patents

Semiconductor memory and manufacture thereof

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Publication number
JPH05326976A
JPH05326976A JP12774792A JP12774792A JPH05326976A JP H05326976 A JPH05326976 A JP H05326976A JP 12774792 A JP12774792 A JP 12774792A JP 12774792 A JP12774792 A JP 12774792A JP H05326976 A JPH05326976 A JP H05326976A
Authority
JP
Japan
Prior art keywords
formed
gate electrode
insulating film
semiconductor memory
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12774792A
Other languages
Japanese (ja)
Inventor
Hironobu Nakao
広宣 中尾
Original Assignee
Rohm Co Ltd
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd, ローム株式会社 filed Critical Rohm Co Ltd
Priority to JP12774792A priority Critical patent/JPH05326976A/en
Publication of JPH05326976A publication Critical patent/JPH05326976A/en
Pending legal-status Critical Current

Links

Abstract

(57) [Summary] [Object] To provide a semiconductor memory device capable of accurately forming a MONOS-type or MNOS-type FACE-type semiconductor memory device with a small cell area, and a manufacturing method thereof. A first insulating film 5 is formed on a surface of a semiconductor substrate 1, a gate electrode 6 is formed on the first insulating film, and then a second insulating film is formed on one side of the gate electrode. A sidewall 10 is formed on the other lateral side by a polysilicon film via a third insulating film, and a source region 3 (drain region 4) is formed by using both sidewalls as a mask. A select gate electrode 9 is formed in contact with the sidewall of the polysilicon film, and a word line 12 is formed on the select gate electrode via a fourth insulating film.
Is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and its manufacturing method. More specifically, the present invention relates to a semiconductor memory device in which electrons are injected into an insulating film to adjust a threshold voltage, and a cell area is reduced, and a manufacturing method thereof.

[0002]

2. Description of the Related Art EEPROMs, which can electrically rewrite data and can hold data even in a non-powered state, are widely used. This EEPROM has a flash memory type in which hot electrons are injected into a floating gate, and a metal-oxide film-nitride film-oxide film-semiconductor structure MONOS (metal) which injects electrons by FN tunneling or direct tunneling in an insulating film. oxide ni
MNOS (metal nitride oxide semiconductor) type or metal-nitride film-oxide film-semiconductor structure
n type or MNOS type, and MONOS and MNOS types have 1 to 2 digits more writing times than flash type memory.
Has been useful.

On the other hand, in order to miniaturize the element, the flash memory type is arranged in an array and the drain and source of adjacent memory transistors are connected to each other, and no contact is formed on both the drain and the source.
A semiconductor memory device of ACE (Flash Array Contactless Eprom) type is disclosed in, for example, the document "High Density Contactless, Self Aligned.
EPROM Cell Array Technology) ", (IEDM, 1986, pp. 592-595).

On the other hand, the writing and reading of this FACE type semiconductor memory device can be performed more easily, and the low concentration between the source region and the channel region is self-aligned without using the LOCOS oxide film for element isolation. A semiconductor memory device in which an impurity region is formed and writing is prohibited is described in "Ancimental light re-doped source (A
LDS) Cell for Virtual Surround High Density EPROM (An Asymmetrical Lightl)
y-Doped Source (ALDS) Cell For Virtual Ground High
Density EPROMS) "(IE DM
DM), 1988, pp. 432-435).

FIG. 11 shows a semiconductor structure diagram of this FACE type semiconductor memory device, and FIG. 12 shows an equivalent circuit diagram thereof. In order to write to the memory transistor of the cell P 1 in this semiconductor memory device, a high voltage of about 8 V is applied to the bit line k (drain region 24), and the bit line k + 1 (source region 23) and other bit lines are applied. Applies a low voltage of about 0V, a high voltage of about 12V to the word line m (word line 25), and a low voltage of about 0V to the other word lines, so that the channel region (p layer ) 22 and the drain region 24 (bit lines k, n + layers) have a large difference in concentration, so that hot electrons are easily generated and writing is performed. In the cell P 2 on the right of the cell p, the source region (bit line k) has a high voltage and the gate electrode is also applied with a high voltage, but a low concentration n region 21 is provided between the source region and the channel region. Therefore, hot electrons are hard to occur, and writing is not performed. During reading, the bit line k + 1 (source region 23) has a high voltage of about 2.5 V, the bit line k has a low voltage, the other bit lines are open, and the word line m has a high voltage of about 5 V. The cell P 1 can be read by applying a low voltage to the word line.

[0006]

As described above, in the conventional FACE type semiconductor memory device, a flash type memory transistor using a floating gate is used for writing and reading. However, in the flash type memory transistor, hot electrons are injected with high energy, so that charges are slightly trapped in the oxide film, the structure is changed due to the coupling of H 2 in the insulating film, and the threshold voltage V There is a problem that the amount of shift of th changes and it becomes impossible to distinguish between the high voltage and the low voltage applied to the gate, and the number of times of rewriting is reduced by one to two digits as compared with the MONOS type or MNOS type memory transistor.

On the other hand, in a MONOS type or MNOS type memory transistor, writing is performed only by applying a high voltage to the gate, and only one memory transistor can selectively perform writing or reading in one cell. I can't, MO
The FACE type has not been realized in the NOS type and MNOS type semiconductor memory devices.

The present invention solves such a problem and provides MO
It is an object of the present invention to provide a method for manufacturing a semiconductor memory device of NOS type or MNOS type, in which the FACE type cell area is reduced.

[0009]

A semiconductor memory device according to the present invention comprises: (a) a gate electrode formed on a semiconductor substrate of a first conductivity type with a first insulating film interposed therebetween (b) one of the gate electrodes. A sidewall made of a second insulating film formed on the lateral side of the gate electrode, (c) a sidewall made of polysilicon formed on the other lateral side of the gate electrode via a third insulating film, (d) A source region and a drain region formed by introducing an impurity of the second conductivity type into the semiconductor substrate outside each of the both sidewalls, and (e) formed by being connected to the sidewall made of polysilicon. It is composed of a selection gate electrode.

Further, the method of manufacturing a semiconductor memory device according to the present invention comprises: (a) a step of forming a first insulating film on the surface of a semiconductor substrate and forming a gate electrode on the first insulating film, (b) A step of forming a sidewall made of a second insulating film on one lateral side of the gate electrode and a sidewall made of polysilicon on the other lateral side of the gate electrode;
(c) A step of forming a source region (drain region) by an ion implantation method using the both sidewalls as a mask, and forming a selection gate electrode on the first insulating film in the region,
And (d) a fourth insulating film is formed on the select gate electrode, and a word line is formed on the fourth insulating film to which gate electrodes of cells arranged in the lateral direction are connected. It will be.

[0011]

According to the present invention, the gate electrode of the memory transistor is formed on the first insulating film of the semiconductor substrate of the first conductivity type, and the sidewall formed on the lateral side of the gate electrode is of the second conductivity type. Since the high-concentration region (source region and drain region) is formed, the source region and the drain region are formed with a minute dimension so as to be separated from the channel region.

Moreover, one side wall is made of polysilicon and is connected to the select gate electrode. When a voltage is applied to the select gate electrode, the depletion layer on the source region side expands, and the channel region and the source region are separated from each other. Electrons are supplied to the channel region from the source region of high-concentration impurities, which are connected by the depletion layer, and electrons are injected into the insulating film from the entire channel region to perform writing.

At this time, in other cells which are not programmed,
Since no voltage is applied to the select gate, writing is not performed.

Further, at the time of reading, a voltage is applied to the word line (gate electrode) and the selection gate, and the voltage is applied to the drain line as well as the above-mentioned writing, so that the depletion layer in the drain region is also expanded. Connected to the channel region, and finally connected to the drain region through the channel region from the source region to be in a state capable of being energized, and becomes conductive or non-conductive depending on a threshold voltage due to the written electric charge. The state of "0" can be read.

Therefore, MONOS type or MNOS
It is possible to realize a FACE type semiconductor memory device having a fine structure with a mold.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1A and 1B show the structure of a semiconductor memory device according to the present invention. FIG. 1A is a sectional structure view and FIG. 1B is a plan view.
2 shows an equivalent circuit diagram thereof.

In FIG. 1, the first conductivity type (for example, p
Source region 3 and drain region 4 are formed by high-concentration regions of the second conductivity type (for example, n type) spaced apart from each other on both sides of the channel region 2 of the semiconductor substrate 1. Drain region 4 is shared with the source region of the cell on the right,
An ACE type semiconductor memory device is configured. A first insulating film 5 is formed on the surface of the semiconductor substrate 1.
Is formed of a three-layer structure of a silicon oxide film, a silicon nitride film, a silicon oxide film or a two-layer structure of a silicon oxide film and a silicon nitride film. On the insulating film 5 in the channel region 2,
For example, a gate electrode 6 formed of a polysilicon film is formed, and a side wall 8 of the polysilicon film is formed on one side of the gate electrode 6 with a third insulating film 7 interposed therebetween. The sidewall 8 is electrically connected to the select gate electrode 9 formed of, for example, tungsten, and the voltage applied to the select gate electrode 9 causes the source region 3 and the channel to pass through the sidewall 8 of the polysilicon film. Conduction / non-conduction with the region 2 is controlled. A side wall 10 made of a second insulating film is formed on the lateral side opposite to the gate electrode 6 so that the channel region 2 and the drain region 4 are offset from each other. A word line is formed above the select gate electrode 9 via a fourth insulating film 11.
12 are wired to connect the gate electrodes of the lateral cells. As shown in FIG. 1B, the gate electrodes of the cells arranged in the array in the lateral direction are connected to form word lines W 1 and W 2 , and the word lines W 1 and W 2 are formed in the cells arranged in the vertical direction. The second conductivity type high-concentration regions of the source region 3 and the drain region 4 are connected to form the bit lines B 2 and B 3 , and similarly, the selection gate electrodes 9 of the cells arranged in the vertical direction are connected to each other. Gate lines SG 2 and SG 3 are formed.

A method of driving the semiconductor memory device thus formed will be described. Writing and reading of the cell Q 1 shown in the equivalent circuit diagram of FIG. 2 will be described with reference to FIG.

[0019] First, the writing is, to the word line W 1 10
A high voltage of about V is applied, a high voltage of about 5V is applied to the select gate SG 2 , and a low voltage of 0V or close thereto is applied to other word lines, bit lines, select gate lines and the substrate. Writing is performed only in the cell Q 1 . That is, since 5 V is applied to the select gate electrode SG 2 of the cell Q 1 , a depletion layer is formed in a portion where the source region 3 (bit line B 2 ) and the channel region 2 are separated from each other, and the source region 3 becomes conductive. From the n + type high concentration region, the electrons proceed to the channel region 2, and the electrons are tunneled and injected into the insulating film 5 by the voltage applied to the gate electrode 6, and writing is performed. No writing is performed in the other cells because a high voltage is not applied to the gate electrode 6 or a high voltage is not applied to the selection gate electrode 9. That is, writing is performed only when a high voltage is applied to both the gate electrode 6 and the selection gate electrode 9.

Next, reading will be described. For reading, a current can flow between the source and drain, and a voltage is applied to the gate electrode,
ON / OFF occurs at the threshold value voltage according to the writing state of the gate insulating film, and the state is “1” or “0”.
The state of can be read. Therefore, in order to read the cell Q 1 , a high voltage of about 5 V is applied to the bit line B 3 and a depletion layer is formed in the space between the channel region 2 and the drain region 4 to form the channel region 2 and the drain region. 4 is connected, and a high voltage of about 5 V is applied to the select gate line SG 2 so that the source region 3 and the channel region 2 are also brought into conduction, and then 5 is connected to the word line W 1 .
By applying the high voltage of V level, the state of “1” or the state of “0” can be read because the current may or may not flow between the source and the drain depending on the threshold voltage. At this time, the bit line B 2 is at 0V or a voltage close to 0V, and the other bit lines are opened.
The other word lines, select gate lines, and substrate are all set to 0V or a low voltage close to 0V.

When erasing, a batch erasing method for all cells is used.
A high voltage of about 10V is applied to the substrate, and the other word lines, bit lines and select gate lines are all set to 0V or a low voltage close to 0V.

Table 1 summarizes the above relationships.

[0023]

[Table 1]

Next, a method of manufacturing the semiconductor memory device of the present invention will be described. 3 to 10 are manufacturing process diagrams of a semiconductor memory device according to an embodiment of the present invention.

First, as shown in FIGS. 3 and 4, the first insulating film 5 is formed on the surface of the semiconductor substrate 1, and then the gate electrode 6 is formed. Specifically, as the first insulating film 5, first, a silicon oxide film of about 20 angstrom is formed by heat treatment at 800 to 900 ° C. for about 20 minutes by the thermal oxidation method. Further, SiH 2 Cl 2 gas and NH 3 gas are introduced by the CVD method, and a silicon nitride film is formed at about 80 angstrom by performing a gas phase reaction at 700 to 800 ° C. for about 10 minutes. Introduce more steam on this
A silicon oxide film of about 50 Å is formed by the steam oxidation method in which heat treatment is performed at 900 to 1000 ° C. for about 60 minutes. The first insulating film 5 does not have to have a three-layer structure but may have a two-layer structure of an oxide film and a nitride film. In this case, the respective thicknesses should be about 15 to 30 and 190 to 300 angstroms, respectively. preferable. In order to form the gate electrode 6 on the first insulating film 5, SiH 4 gas and N 2 gas are introduced, and a polysilicon film of about 5000 angstrom is formed by the treatment at 600 to 650 ° C. , The gap between the channel region 2 and the source region 3 and the gap between the channel region 2 and the drain region 4 are removed by etching to form the opening 15.

Next, as shown in FIGS.
On both sides of the gate electrode 6, that is, on both sides of the gate electrode 6, a sidewall 8 made of a polysilicon film and a sidewall 10 made of a second insulating film are formed. Specifically, C which introduces SiH 2 Cl 2 gas and N 2 O gas and causes a gas phase reaction at 500 to 600 ° C.
A silicon oxide film is formed on the entire surface of about 2000 angstroms by the VD method, and subsequently, it is etched back by the RIE method, one side is masked and etched, and the side wall 10 of the second insulating film is formed only on one side. Further, a silicon oxide film of about 500 angstroms is formed around the gate electrode 6 as a third insulating film 7 for a stopper of the later ion etching by a pyrogenic oxidation method in which water vapor is introduced and heated at 800 to 900 ° C. for about 30 minutes. Formed in. After that, a polysilicon film is formed to about 2000 angstroms by the CVD method as described above, and the sidewalls 8 of the polysilicon film are formed by etching back. At this time, the side wall of the polysilicon film on the side where the side wall 10 of the second insulating film is formed is removed by etching.

Next, as shown in FIGS. 7 to 8, impurities of the second conductivity type are introduced by the ion implantation method using the sidewalls 8 and 10 as masks to form the source region 2 (drain region 3). Select gate electrode 9 on insulating film 5
Is formed. Specifically, phosphorus (P) ions are ion-implanted at an accelerating voltage of 70 keV and a dose amount of 5 × 10 15 cm -2 , and then WF 6 gas and SiH 4 gas are introduced, and 300 to 400 A Dangsten film is formed by the CVD method of reacting at a temperature of ℃, and is formed so as to be lower than the surface of the gate electrode 6 by etching back. At this time, since the above-mentioned third insulating film 7 is formed on the surface of the gate electrode 6 side, the etching stops at this third insulating film 7, and only the tungsten film is etched. The selection gate electrode 9 is formed lower than the gate electrode 6 in a later step. When the distance from the word line 12 connecting the gate electrodes 6 is close, the voltage applied to the word line 12 interacts with the selection gate electrode 9, and the source and the channel become conductive even though no voltage is applied to the selection gate electrode 9. This is to prevent the situation.

Finally, as shown in FIGS. 9 to 10, word lines are formed on the select gates 9 to connect the gate electrodes of the cells in the lateral direction through the fourth insulating film. Specifically, PH
3 gas, SiH 4 gas and B 2 H 6 gas are introduced, and 500-
Approximately 1000 angstrom BPSG film (borophosphosilicate glass film) by CVD method of reacting at 600 ° C
Is formed and the BPSG film is flattened by heat treatment at 900 to 1000 ° C. for about 60 minutes. After that, the gate electrode 6 is exposed by etching back by the RIE method, a polycide film is formed on the gate electrode 6 by the CVD method, and the word line 12 is formed by patterning. after that,
A protective film may be formed on this surface at any time.

The above-mentioned specific example is merely an example,
The material of the insulating film and the electrode, and the forming method are not limited to the above-mentioned specific examples, and may be other known materials and methods.

[0030]

According to the present invention, the offset between the channel region and the source region and the drain region can be formed in a self-aligned manner by the side wall, a mask is not required, and it is miniaturized. MONOS
Type or MNOS type semiconductor memory device can be obtained. Further, according to the present invention, the voltage of the word line is kept between the channel region and the drain region by the insulating film formed by the CVD method or the like on the surface without forming the LOCOS oxide film forming the thick oxide film on the semiconductor substrate. Since it does not affect the offset, it can contribute to further miniaturization.

[Brief description of drawings]

FIG. 1 is an explanatory view showing the structure of a semiconductor memory device according to an embodiment of the present invention, in which (a) is a sectional view and (b) is a plan view.

FIG. 2 is an equivalent circuit diagram of a semiconductor memory device that is an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the semiconductor memory device which is an embodiment of the present invention.

FIG. 4 is an explanatory diagram of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 9 is an explanatory diagram of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 10 is a diagram illustrating the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 11 is an explanatory cross-sectional view of a conventional floating gate type FACE type semiconductor memory device.

FIG. 12 is an equivalent circuit diagram of a conventional floating gate type FACE type semiconductor memory device.

[Explanation of symbols]

 1 Semiconductor Substrate 3 Source Region 4 Drain Region 5 First Insulating Film 6 Gate Electrode 7 Third Insulating Film 8 Polysilicon Sidewall 9 Select Gate Electrode 10 Second Insulating Film Sidewall 11 Fourth Insulating Film 12 Word line

Claims (2)

[Claims]
1. A gate electrode formed on a semiconductor substrate of a first conductivity type via a first insulating film, and a second insulating film formed on one lateral side of the gate electrode. A side wall made of a film, (c) a side wall made of polysilicon formed on the other lateral side of the gate electrode via a third insulating film, (d) the semiconductor outside each of the both side walls A semiconductor memory device comprising a source region and a drain region formed by introducing a second conductivity type impurity into a substrate, and (e) a select gate electrode formed in connection with a sidewall made of polysilicon.
2. A step of: (a) forming a first insulating film on a surface of a semiconductor substrate and forming a gate electrode on the first insulating film; (b) forming a gate electrode on one side of the gate electrode. A step of forming a side wall made of an insulating film of No. 2 and a side wall made of polysilicon on the other lateral side of the gate electrode, and (c) a source region ( Drain region) and a select gate electrode is formed on the first insulating film in the region, and (d) a fourth insulating film is formed on the select gate electrode, and the fourth insulating film is formed. A method of manufacturing a semiconductor memory device, which comprises the steps of forming a word line in which gate electrodes of cells arranged in a lateral direction are connected to each other on a film.
JP12774792A 1992-05-20 1992-05-20 Semiconductor memory and manufacture thereof Pending JPH05326976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12774792A JPH05326976A (en) 1992-05-20 1992-05-20 Semiconductor memory and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12774792A JPH05326976A (en) 1992-05-20 1992-05-20 Semiconductor memory and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05326976A true JPH05326976A (en) 1993-12-10

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Country Status (1)

Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19600423A1 (en) * 1996-01-08 1997-07-17 Siemens Ag Electrically programmable memory cell arrangement and method for its production
DE19600422C1 (en) * 1996-01-08 1997-08-21 Siemens Ag Electrically programmable memory cell arrangement and method for its production
WO2002043158A1 (en) * 2000-11-21 2002-05-30 Halo Lsi Design & Device Technology Inc. Dual bit multi-level ballistic monos memory, and manufacturing method, programming, and operation process for the memory
EP1227518A2 (en) * 2001-01-30 2002-07-31 Halo LSI Design & Device Technology, Inc. Method of manufacturing semiconductor integrated circuit device including nonvolatile semiconductor memory devices
EP1227519A3 (en) * 2001-01-30 2003-08-27 Halo LSI Design & Device Technology, Inc. Semiconductor integrated circuit device including nonvolatile semiconductor memory devices
US6717207B2 (en) 2002-01-30 2004-04-06 Renesas Technology Corp. Non-volatile semiconductor memory device of which bit line withstand voltage can be increased

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19600423A1 (en) * 1996-01-08 1997-07-17 Siemens Ag Electrically programmable memory cell arrangement and method for its production
DE19600422C1 (en) * 1996-01-08 1997-08-21 Siemens Ag Electrically programmable memory cell arrangement and method for its production
US6191459B1 (en) 1996-01-08 2001-02-20 Infineon Technologies Ag Electrically programmable memory cell array, using charge carrier traps and insulation trenches
DE19600423C2 (en) * 1996-01-08 2001-07-05 Siemens Ag Electrically programmable memory cell arrangement and method for its production
WO2002043158A1 (en) * 2000-11-21 2002-05-30 Halo Lsi Design & Device Technology Inc. Dual bit multi-level ballistic monos memory, and manufacturing method, programming, and operation process for the memory
JP2002170891A (en) * 2000-11-21 2002-06-14 Halo Lsi Design & Device Technol Inc Manufacture of dual bit multi-level ballistic monos memory, programming, and operation process
KR100884788B1 (en) * 2000-11-21 2009-02-23 할로 엘에스아이, 인크. Dual bit multi-level ballistic monos memory, and manufacturing method, programming, and operation process for the memory
EP1227518A2 (en) * 2001-01-30 2002-07-31 Halo LSI Design & Device Technology, Inc. Method of manufacturing semiconductor integrated circuit device including nonvolatile semiconductor memory devices
EP1227519A3 (en) * 2001-01-30 2003-08-27 Halo LSI Design & Device Technology, Inc. Semiconductor integrated circuit device including nonvolatile semiconductor memory devices
US6709922B2 (en) 2001-01-30 2004-03-23 Seiko Epson Corporation Method of manufacturing semiconductor integrated circuit device including nonvolatile semiconductor memory devices
US6809385B2 (en) 2001-01-30 2004-10-26 Seiko Epson Corporation Semiconductor integrated circuit device including nonvolatile semiconductor memory devices having control gates connected to common contact section
CN100334737C (en) * 2001-01-30 2007-08-29 精工爱普生株式会社 Semiconductor integrated circuit device contg. nonvolatile semiconductor storage
EP1227518A3 (en) * 2001-01-30 2003-08-27 Halo LSI Design & Device Technology, Inc. Method of manufacturing semiconductor integrated circuit device including nonvolatile semiconductor memory devices
US6717207B2 (en) 2002-01-30 2004-04-06 Renesas Technology Corp. Non-volatile semiconductor memory device of which bit line withstand voltage can be increased

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