JPH05326948A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH05326948A
JPH05326948A JP13212892A JP13212892A JPH05326948A JP H05326948 A JPH05326948 A JP H05326948A JP 13212892 A JP13212892 A JP 13212892A JP 13212892 A JP13212892 A JP 13212892A JP H05326948 A JPH05326948 A JP H05326948A
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JP
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Patent type
Prior art keywords
well
width
pn junction
semiconductor device
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13212892A
Other languages
Japanese (ja)
Inventor
Tomohisa Mizuno
智久 水野
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Abstract

PURPOSE: To provide a MOSFET structure which allows high integration and high driving force by providing an extremely shallow pn junction well on many trenches or on the surface of an Si column and permitting the well to be a channel.
CONSTITUTION: After forming an (n) well 12 on a p-type silicon substrate 11, many grooves 13 of 3μm in depth are formed by etching the silicon substrate 11. Then, a first p-well 14 of 0.1μm in depth is formed by implanting B ions by rotating diagonal ion implantation. After forming a 10-nm-thick gate oxide film 15, polycrystal silicon 16 for a gate electrode is accumulated thicker than the half of the width of the groove 13, a gate electrode 16 is formed in the groove 13 by etching. The depth of the first p-well is smaller than the sum of the width of the channel depletion layer and the width of the depletion layer at the pn junction between the first p-well and the n-well 12. The thickness of a second p-well 18 is larger than the sum of the width of the depleted layer between an n+ layer 17 and the second p-well 18 and the width of the pn junction depleted layer between the second p-well 18 and the n-well 12.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体装置に関するもので、特にトランジスタ構造に使用されるものである。 The present invention relates to the the present invention relates to a semiconductor device, is intended to be used in particular transistor structure.

【0002】 [0002]

【従来の技術】第4図を参照して従来技術のnチャネルMOSFETの構造を説明する。 BACKGROUND OF THE INVENTION With reference to Figure 4 illustrating the structure of the n-channel MOSFET of the prior art. p型シリコン基板(1)にゲート酸化膜(2)を介してゲート電極がある。 The p-type silicon substrate (1) there is a gate electrode via a gate oxide film (2). 又、ソース/ドレイン領域にはn+層(4)が形成されている。 Further, n + layer (4) is formed on the source / drain regions.

【0003】第4図に示した従来構造のMOSFETでは、電流駆動能力を上げるためにチャネル幅を増大する必要がある。 [0003] In MOSFET having the conventional structure shown in FIG. 4, it is necessary to increase the channel width to increase the current driving capability. その上、ゲート長の微細化に対しては、いわゆる短チャネル効果の問題がるため、従来技術のMO Furthermore, for miniaturization of the gate length, for want problems of the so-called short channel effect, MO prior art
SFETでは高駆動能力でかつ高集積化が非常に困難である。 In SFET and a high driving capability higher integration is very difficult.

【0004】 [0004]

【発明が解決しようとする課題】本発明の目的は、高集積化が可能な高駆動能力のMOSFET構造を提供することである。 An object of the present invention is to provide a, it is to provide a MOSFET structure of a high driving capability can be highly integrated.

【0005】 [0005]

【課題を解決するための手段】非常に浅いpn接合のウェルを多数のトレンチまたはSi柱の表面に設け、それをチャネルとすることを特徴とするMOSFET構造。 Provided very shallow pn junction wells [Summary of on the surface of a number of trenches or Si pillar, MOSFET structure, characterized in that it as a channel.

【0006】 [0006]

【作用】すなわち、pタイプSi内のnウェルを形成後、SiをRIEによって、多数のトレンチを形成し、 [Action] That is, after forming the n-well in the p-type Si, by the Si RIE, to form a plurality of trenches,
その後、BF 2を回転斜めイオン注入することによって、非常に浅いpウェルを形成する。 Thereafter, by rotating the oblique ion implantation BF 2, to form a very shallow p-well. その後は、通常通りトレンチの表層にゲート電極、拡散層を形成することによって、一つの新しいMOSFETが形成できた。 Thereafter, the surface layer to the gate electrode of the usual trenches, by forming a diffusion layer, a new MOSFET was formed. この新MOSFETでは、pウェルとpウェル間のpn接合面積が増大する。 This new MOSFET, pn junction area between the p-well and p-well are increased. 従って、反転層からの基板への電子注入数が増大するため、駆動能力が向上する。 Therefore, since the electron injection speed of the substrate from the inversion layer is increased, thereby improving drivability.

【0007】 [0007]

【実施例】第1図の断面図、及び第2図の平面図を参照しながら本発明の実施例を述べる。 EXAMPLES describe examples of reference while the present invention cross-sectional view of FIG. 1, and the plan view of FIG. 2.

【0008】p型シリコン基板(11)にnウェル(1 [0008] n-well in p-type silicon substrate (11) (1
2)を形成後、シリコン基板(11)をRIEによってエッチングすることによって、深さ3μmの多数の溝(13)を形成する(第1図(a))。 After forming the 2), silicon substrate (by etching by a 11) RIE, to form a number of grooves of depth 3 [mu] m (13) (FIG. 1 (a)). この場合、平面的には、第2図(a)に示すように、溝(13)は長方形状の形状をしている。 In this case, the plan view, as shown in FIG. 2 (a), the groove (13) has a rectangular shape. その後、Bイオンを回転斜めイオン注入法によって、深さ0.1μmの第1のpウェル(14)を形成し、また、10nmの厚さのゲート酸化膜(15)を形成した後、ゲート電極用の多結晶シリコン(16)を溝(13)の幅Lの半分より厚く堆積した後、RIEによってエッチングして溝(13)の中にゲート電極(16)を形成する(第1図(b))。 Thereafter, the B ions rotation oblique ion implantation method, to form a first p-well depth 0.1 [mu] m (14), also, after forming a gate oxide film having a thickness of 10 nm (15), a gate electrode after polycrystalline silicon (16) of use thicker deposits than half of the width L of the groove (13) is etched by RIE to form the gate electrode (16) into the groove (13) (FIG. 1 (b )). 平面的には第2図(b)に示すように、ゲート電極(16)をコンタクト用にパターニングして形成する。 As the plan view shown in FIG. 2 (b), it is formed by patterning the gate electrode (16) for the contact. また、As In addition, As
およびBイオンをイオン注入することによって、それぞれn+層(17)及び第2のpウェル(18)を形成でき、これで新しいMOSFETが製作できた(第1図(c))。 And B ions by ion implantation, respectively can form an n + layer (17) and a second p-well (18), The new MOSFET could be fabricated (FIG. 1 (c)). なお、n+層(17)及び第2のpウェル(18)は溝(13)より浅く、かつn+層(17)は第2のpウェル(18)より浅くする必要がある。 Incidentally, the n + layer (17) and a second p-well (18) is shallower than the groove (13), and the n + layer (17) needs to be shallower than the second p-well (18).

【0009】この新しいMOSFETでは、第1のpウェルの深さXjは、チャネルの空乏層幅Waと、第1のpウェルとnウェル(12)間のpn接合の空乏層幅W [0009] This new MOSFET, the depth Xj of the first p-well, the depletion layer width Wa of the channel, the depletion layer width W of the pn junction between the first p-well and n-well (12)
bとの和Wa+Wbより小さい(Xj<Wa+Wb)。 Less than the sum Wa + Wb of the b (Xj <Wa + Wb).
従って、ソース/ドレインを接地し、nウェル電位を印加することによって、反転層とnウェル(12)間でのトランジスタが形成できる。 Therefore, grounding the source / drain, by applying an n-well potential, the transistor between the inversion layer and the n-well (12) can be formed. また、第2のpウェル(1 The second p-well (1
8)の厚さXpは、n+層(17)と第2のpウェル(18)間のpn接合の空乏層幅Wcと、第2のpウェル(18)とnウェル(12)間のpn接合の空乏層幅Wdとの和Wc+Wdより大きい(Xp>Wc+W The thickness Xp of 8), n + layer (17) and the depletion layer width Wc of the pn junction between the second p-well (18), a second p-well (18) and n-well (12) pn between greater than the sum Wc + Wd of the depletion layer width Wd of the junction (Xp> Wc + W
d)。 d). また、溝(13)の平面パターンは第4図に示すように四角形のアレイ状のものでもかまわない。 The planar pattern of the groove (13) may be one array of square as shown in Figure 4.

【0010】 [0010]

【発明の効果】第1及び2図の本発明の実施例に示したように、チャネル部でXj<Wa+Wbの条件のため、 According to the present invention as shown in the embodiment of the present invention the first and 2 showing, for the condition Xj <Wa + Wb in the channel portion,
反転層と基板間のスイッチング動作が、パンチスルー効果により、ゲート電圧によって行うことができる。 Switching operation between the inversion layer and the substrate, the punch-through effect, can be carried out by the gate voltage. しかも、チャネル部が多数の溝構造になっているため、チャネルの面積が飛躍的に増大する。 Moreover, since the channel portion is to a large number of groove structure, the area of ​​the channel increases dramatically. すなわち、平面構造のMOSFETでは、その面積はLef×Wであるが(L That is, in the MOSFET of planar structure, but the area is Lef × W (L
efは実効チャネル長、Wはチャネル幅)、本発明の新MOSFET構造では、溝の深さをD、長さをL、幅をWtとすると(2L+Wt)×Dとなり、溝の深さの分だけチャネルの面積が増大する。 ef is the effective channel length, W is the channel width), a new MOSFET structure of the present invention, D the depth of the grooves, the length L, and the width Wt (2L + Wt) × D, and the amount of depth of the groove area of ​​the channel is increased only. 反転層と基板間の電流は、チャネルの面積に比例するため、本発明の新MOS Inversion layer and the current between the substrates is proportional to the area of ​​the channel, the new MOS of the present invention
FETは高駆動能力が実現できる。 FET is a high driving capability can be realized.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の実施例のMOSFET断面図。 [1] MOSFET sectional view of an embodiment of the present invention.

【図2】 本発明の実施例のMOSFET平面図。 [2] MOSFET plan view of an embodiment of the present invention.

【図3】 本発明の第2の実施例のMOSFET平面図。 [Figure 3] MOSFET plan view of a second embodiment of the present invention.

【図4】 従来技術のMOSFET断面図。 [4] MOSFET sectional view of a prior art.

【符号の説明】 DESCRIPTION OF SYMBOLS

(1),(11):シリコン基板 (12):nウェル (2),(15):ゲート酸化膜 (3),(16):ゲート電極 (4),(17):n+層 (13):溝 (14):第1のpウェル (18):第2のpウェル (1), (11): a silicon substrate (12): n-well (2), (15): gate oxide film (3), (16): Gate electrode (4), (17): n + layer (13) : grooves (14): the first p-well (18): a second p-well

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体基板の溝構造の側面および底面がチャネルである一つのトランジスタにおいて、半導体基板の溝が多数形成されていることを特徴とする半導体装置。 1. A one transistor sides and bottom is a channel of the trench structure of the semiconductor substrate, a semiconductor device characterized by grooves in the semiconductor substrate are formed a number.
  2. 【請求項2】半導体基板の溝が直方体の列、またはマトリックスのアレイ状態であることを特徴とする請求項1 2. A method according to claim, wherein the groove of the semiconductor substrate is an array state of the rectangular column or matrix, 1
    記載の半導体装置。 The semiconductor device according.
  3. 【請求項3】チャネル領域の第1のウェルの厚さXj 3. A thickness of the first well in the channel region Xj
    が、チャネル空乏層幅Wa、及び第1のウェルと第1のウェルを被う反対型のウェルとのpn接合の空乏層幅W But the channel depletion layer width Wa, and the first well and the depletion layer width W of the pn junction between the opposite type well covering the first well
    bと、 Xj<Wa+Wb の関係があることを特徴とする請求項1記載の半導体装置。 b and, Xj <semiconductor device according to claim 1, characterized in that there is a relationship of Wa + Wb.
  4. 【請求項4】ソース/ドレイン拡散層領域の第2のウェルの厚さXpが、拡散層と第2のウェルとのpn接合の空乏層幅Wc、及び第2のウェルと第2のウェルを被う反対型のウェルとのpn接合の空乏層幅Wdと、 Xp>Wc+Wd の関係があることを特徴とする請求項1記載の半導体装置。 4. A thickness Xp of the second well of the source / drain diffusion layer regions, the pn junction between the diffusion layer and the second well depletion layer width Wc, and a second well and a second well opposite type and depletion layer width Wd of the pn junction between the well, Xp> Wc + Wd semiconductor device according to claim 1, wherein there are relationships covering.
  5. 【請求項5】ソース/ドレインを接地し、第1及び第2 5. A grounding the source / drain, first and second
    のウェルを被う反対型のウェルに電圧を印加することによって、反転層からキャリアを基板へ注入することを特徴とする請求項1記載の半導体装置。 By applying a voltage to the opposite type well covering the wells, the semiconductor device according to claim 1, wherein the injecting from the inversion layer carrier to the substrate.
JP13212892A 1992-05-25 1992-05-25 Semiconductor device Pending JPH05326948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13212892A JPH05326948A (en) 1992-05-25 1992-05-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13212892A JPH05326948A (en) 1992-05-25 1992-05-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05326948A true true JPH05326948A (en) 1993-12-10

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Family Applications (1)

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JP (1) JPH05326948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1205980A1 (en) * 2000-11-07 2002-05-15 Infineon Technologies AG A method for forming a field effect transistor in a semiconductor substrate
CN101924135A (en) * 2009-06-11 2010-12-22 索尼公司 Semiconductor device, method for manufacturing same, and solid-state image sensing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1205980A1 (en) * 2000-11-07 2002-05-15 Infineon Technologies AG A method for forming a field effect transistor in a semiconductor substrate
CN101924135A (en) * 2009-06-11 2010-12-22 索尼公司 Semiconductor device, method for manufacturing same, and solid-state image sensing device

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