JPH05326922A - Semiconductor crystal growth - Google Patents

Semiconductor crystal growth

Info

Publication number
JPH05326922A
JPH05326922A JP14901492A JP14901492A JPH05326922A JP H05326922 A JPH05326922 A JP H05326922A JP 14901492 A JP14901492 A JP 14901492A JP 14901492 A JP14901492 A JP 14901492A JP H05326922 A JPH05326922 A JP H05326922A
Authority
JP
Japan
Prior art keywords
gaas
layer
crystal
superlattice
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14901492A
Other languages
Japanese (ja)
Other versions
JP2733725B2 (en
Inventor
Hisao Saito
久夫 斎藤
Kunihiko Uei
邦彦 上井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14901492A priority Critical patent/JP2733725B2/en
Publication of JPH05326922A publication Critical patent/JPH05326922A/en
Application granted granted Critical
Publication of JP2733725B2 publication Critical patent/JP2733725B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To improve flatness in the plane on the substrate crystal surface by controlling the height of step on the grown crystal surface to the single atom layer and the width of terrace with the equal interval. CONSTITUTION:A vertical type semiconductor superlattice is formed through the processes that a GaAs buffer layer 5 is brown by the organic metal vapor growth method in the thickness of about 600Angstrom on a substrate crystal surface of a GaAs inclined substrate 1, thereafter a superlattice is grown in the 20 periods, each period thereof including formation of three-atom layers of AlAs crystal layer 10 and three-atom layers of GaAs crystal layer 11 on this GaAs buffer layer 5, next a semiconductor superlattice is grown for 900 periods, each period thereof including formation of 0.5 atom layer of AlAs and next 0.5-atom layer of GaAs on this superlattice.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えば超高速の低次元
電子トランジスタ,低発振閾値を持つ量子井戸あるいは
量子井戸細線構造レーザなどの形成に適用される半導体
結晶成長法に係わり、特に基板結晶表面上の面内での平
坦制御方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor crystal growth method applied to the formation of, for example, an ultrafast low-dimensional electron transistor, a quantum well having a low oscillation threshold, or a quantum well thin-line structure laser, and more particularly to a substrate crystal. The present invention relates to an in-plane flatness control method on a surface.

【0002】[0002]

【従来の技術】加熱炉内に複数の有機金属化合物ガス等
の原料を順次切り替えて導き、この原料に応じた基板結
晶表面上に析出する結晶成長法(MOCVD法)を用
い、GaAs(001)面から[バー110]方向へ傾
いた基板結晶表面上の[110]方向の沿ってできる原
子ステップを利用してそのステップから優先的に横方向
成長を行い、図4に示すような縦型半導体超格子構造4
や量子細線構造を形成しようとする場合、GaAs傾斜
基板1の基板結晶表面のステップ(段差)2が一原子層
あるいはテラス3の幅(ステップとステップとの間隔)
が等間隔でなければならない。
2. Description of the Related Art GaAs (001) is formed by using a crystal growth method (MOCVD method) in which a plurality of raw materials such as organometallic compound gases are sequentially introduced into a heating furnace and deposited on a substrate crystal surface according to the raw materials. Using the atomic step formed along the [110] direction on the substrate crystal surface tilted from the plane toward the [Bar 110] direction, the lateral growth is preferentially performed from that step, and the vertical semiconductor as shown in FIG. Superlattice structure 4
When a quantum wire structure is to be formed, the step (step) 2 on the substrate crystal surface of the GaAs tilted substrate 1 is the width of one atomic layer or the terrace 3 (interval between steps).
Must be evenly spaced.

【0003】しかしながら、結晶成長に用いるGaAs
傾斜基板1の基板表面は、加工ダメージや数十原子層の
段差を有するステップが多く存在し、また、テラス間隔
も不均一である。このため、基板結晶上にバッファ層と
してGaAsを数百Å以上形成したり、あるいはGaA
sとAlAsとを交互に40〜100Åを一周期として
20から100周期形成した超格子を基板結晶と縦型半
導体超格子との間に挿入して単原子ステップやテラス幅
を制御する試みが行われていた。
However, GaAs used for crystal growth
On the substrate surface of the inclined substrate 1, there are many steps having processing damage and steps of several tens of atomic layers, and the terrace intervals are also non-uniform. Therefore, several hundred Å or more of GaAs is formed as a buffer layer on the substrate crystal, or GaA
An attempt has been made to control a monatomic step and a terrace width by inserting a superlattice in which s and AlAs are alternately formed with 40 to 100Å as one cycle for 20 to 100 cycles between the substrate crystal and the vertical semiconductor superlattice. It was being appreciated.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、前述し
た従来の半導体結晶成長方法においても、成長結晶表面
上の平坦性が制御されないため、図5に示すようにGa
As傾斜基板1上に形成したGaAsバッファ層5の成
長表面にはステップ6の高さが数原子層以上の凹凸が存
在し、しかもテラス7の幅も等間隔ではなく、幅の広い
(数百Å)テラス7aと幅の狭い(40〜50Å以下)
テラス7bとが混在する。このため、縦型半導体超格子
4を形成した場合、周期の不均一や超格子界面の混晶化
が起こるという問題があった。また、量子細線構造にお
ける細線幅の面内寸法が均一でなく、特性のばらつきが
多くなるという問題があった。
However, even in the above-described conventional semiconductor crystal growth method, since the flatness on the surface of the grown crystal is not controlled, as shown in FIG.
On the growth surface of the GaAs buffer layer 5 formed on the As-graded substrate 1, there are irregularities whose step 6 has a height of several atomic layers or more, and the terraces 7 are not evenly spaced but wide (several hundreds). Å) Terrace 7a and narrow width (40-50 Å or less)
The terrace 7b is mixed. Therefore, when the vertical semiconductor superlattice 4 is formed, there are problems that the period is nonuniform and the superlattice interface is mixed. In addition, there is a problem in that the in-plane dimension of the thin line width in the quantum thin line structure is not uniform, and the variations in the characteristics increase.

【0005】したがって本発明は、前述した従来の課題
を解決するためになされたものであり、その目的は、成
長結晶表面上のステップの高さを一原子層およびテラス
幅を等間隔に制御し、基板結晶表面上の面内での平坦性
を向上させることができる半導体結晶成長方法を提供す
ることにある。
Therefore, the present invention has been made to solve the above-mentioned conventional problems, and its purpose is to control the height of steps on the surface of a grown crystal by one atomic layer and the terrace width at equal intervals. Another object of the present invention is to provide a semiconductor crystal growth method capable of improving in-plane flatness on the surface of a substrate crystal.

【0006】[0006]

【課題を解決するための手段】このような目的を達成す
るために本発明は、複数の有機金属化合物等の原料を順
次切り替えて導き、この原料に応じた半導体を基板結晶
表面上に析出する結晶成長法を用い、GaAs(00
1)面から[バー110]方向へ傾いた基板結晶表面上
に2種類の半導体として例えばGaAsとAlAsとを
一原子層または数原子層覆うごとに交互に供給し、一原
子層づつまたは数原子層を一周期とする超格子を十〜数
十周期形成するものである。
In order to achieve such an object, the present invention is directed by sequentially switching a plurality of raw materials such as organometallic compounds, and depositing a semiconductor according to the raw materials on the crystal surface of the substrate. GaAs (00
1) Two kinds of semiconductors, for example, GaAs and AlAs are alternately supplied every one atomic layer or several atomic layers on the surface of the substrate crystal inclined in the [Bar 110] direction from the plane, and one atomic layer or several atomic layers are supplied. A superlattice having a layer as one period is formed for ten to several tens of periods.

【0007】[0007]

【作用】本発明においては、GaAs(001)面から
[バー110]方向へ傾いた基板結晶表面上が多くのス
テップ(段差)や不均一なテラスを有した場合であって
も、成長表面上は一原子層のステップを有し、かつ等間
隔のテラス幅か形成される。
In the present invention, even when the substrate crystal surface inclined from the GaAs (001) plane in the [Bar 110] direction has many steps (steps) and uneven terraces, the growth surface is Have steps of one atomic layer and are formed with evenly spaced terrace widths.

【0008】[0008]

【実施例】以下、図面を用いて本発明の実施例を詳細に
説明する。図1は、本発明による半導体結晶成長方法の
一実施例を説明するための模式図であり、前述の図と同
一部分には同一符号を付してある。同図において、8は
ステップを示し、9はテラスを示す。ここでは、GaA
s(001)面の[バー110]方位に対して角度θ=
2度、さらに面内の垂直方位の[110]に対して角度
θ=0.1度傾いた結晶表面を有するGaAs傾斜基板
1を用いた。まず、第1の工程として、GaAs傾斜基
板1の基板結晶上に有機金属気相成長法によりGaAs
バッファ層5を約600Å成長し、基板表面の加工ダメ
ージの影響をなくした。次に第2の工程として、AlA
s結晶層10を三原子層と、GaAs結晶層11を三原
子層とを成長させ、これを一周期とする超格子を20周
期成長させた。その後、第3の工程として、図4に示す
ようなAlAsを0.5原子層,次にGaAsを0.5
原子層を一周期とする半導体超格子を900周期成長し
て縦型半導体超格子4を形成した。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic diagram for explaining an embodiment of a semiconductor crystal growth method according to the present invention, and the same parts as those in the above-mentioned drawings are designated by the same reference numerals. In the figure, 8 indicates a step and 9 indicates a terrace. Here, GaA
The angle θ = with respect to the [bar 110] direction of the s (001) plane
A GaAs tilted substrate 1 having a crystal surface tilted at an angle θ of 0.1 degree with respect to [110] in the in-plane vertical direction was used. First, as the first step, GaAs is formed on the substrate crystal of the GaAs inclined substrate 1 by metal organic vapor phase epitaxy.
The buffer layer 5 was grown to about 600Å to eliminate the influence of processing damage on the substrate surface. Next, as the second step, AlA
The s crystal layer 10 and the GaAs crystal layer 11 were grown as a triatomic layer and a triatomic layer, and 20 cycles of a superlattice were grown. After that, as a third step, 0.5 atomic layer of AlAs as shown in FIG.
A vertical semiconductor superlattice 4 was formed by growing 900 cycles of a semiconductor superlattice having an atomic layer as one cycle.

【0009】このような方法において、第2の工程で成
長した超格子表面のステップ8の高さおよびテラス9の
幅をTEMにより観察した結果、ステップが一原子層で
かつ幅の広いテラスと狭いテラスのテラス幅の差は10
Å以下(約3原子層)であり、成長表面上が完全に制御
されていることを確認した。また、図1中のAlAs結
晶層10とGaAs結晶層11とを一原子層づつあるい
は二原子層を一周期として60周期程度成長させた場合
でも、同様な効果が得られた。
In such a method, the height of the step 8 and the width of the terrace 9 on the surface of the superlattice grown in the second step were observed by TEM. As a result, the step was one atomic layer and the terrace was wide and narrow. The difference in the width of the terrace is 10
It was Å or less (about 3 atomic layers), and it was confirmed that the growth surface was completely controlled. The same effect was obtained when the AlAs crystal layer 10 and the GaAs crystal layer 11 in FIG. 1 were grown for about 60 cycles with one atomic layer or two atomic layers as one cycle.

【0010】図2は本発明に係わる超格子周期と表面上
のテラス幅との関係を示したものである。同図におい
て、横軸はAlAs結晶層とGaAs結晶層の一周期の
原子層の厚さ(ML:モノレーヤ)を示し、縦軸は幅の
広いテラス(Tw)と狭いテラス(Tn)とのテラス幅
の差(Å)を示している。同図から明かなように超格子
周期が26原子層では、150Å以上のテラス幅のばら
つきがあるのに対し、6原子層では10Å以下である。
このように本実施例によれば、成長表面上のテラス幅の
均一性が約15倍改善されたことが解る。
FIG. 2 shows the relationship between the superlattice period and the terrace width on the surface according to the present invention. In the figure, the horizontal axis represents the thickness (ML: monolayer) of the atomic layer of one period of the AlAs crystal layer and the GaAs crystal layer, and the vertical axis represents the terrace of the wide terrace (Tw) and the narrow terrace (Tn). The width difference (Å) is shown. As can be seen from the figure, the 26-atom superlattice period has a terrace width variation of 150 Å or more, while the 6-atom layer has a terrace width of 10 Å or less.
As described above, according to this example, it is understood that the uniformity of the terrace width on the growth surface is improved by about 15 times.

【0011】次に前述した結晶成長条件の詳細について
説明する。高周波加熱の横型炉を用い、約76torr
の減圧下で結晶成長を行った。原料としてトリエチルア
ルミ(TEAl),トリエチルガリウム(TEGa),
アルシン(AsH3 )を用いた。反応管内の分圧は、そ
れぞれ5.9×10-4torr,5.8×10-4tor
r,5.3×10-1torrであり、水素キャリアガス
も含め、全ガス流量は4リッタ/分である。また、成長
温度は約600℃である。この条件での成長速度は、
0.47Å/秒であり、約6秒間でテラス(平坦部)9
の前面が覆われ、丁度一原子層の厚さに相当する。
Next, the details of the above-mentioned crystal growth conditions will be described. Approximately 76 torr using horizontal furnace of high frequency heating
The crystal was grown under reduced pressure. As a raw material, triethylaluminum (TEAl), triethylgallium (TEGa),
Arsine (AsH 3 ) was used. The partial pressures in the reaction tube are 5.9 × 10 −4 torr and 5.8 × 10 −4 torr, respectively.
r, 5.3 × 10 −1 torr, and the total gas flow rate including the hydrogen carrier gas is 4 liters / minute. The growth temperature is about 600 ° C. The growth rate under this condition is
0.47Å / sec, and terrace (flat part) 9 in about 6 seconds
The front surface of is covered and corresponds to exactly one atomic layer thickness.

【0012】図3は本発明による半導体結晶成長方法に
より形成された半導体超格子を光素子への応用として活
性層をInAsとした量子細線構造レーザに適用した場
合を示す模式図である。同図において、21は前述した
GaAs傾斜基板1に相当するn-GaAs基板、22
はn-(AlAs)3(GaAs)3 超格子、23はGa
As層、24はInAs活性層、25はp-AlGaA
sクラッド層、26はp-GaAsキャップ層、27電
極、28は電極である。
FIG. 3 is a schematic view showing a case where the semiconductor superlattice formed by the semiconductor crystal growth method according to the present invention is applied to a quantum wire laser having an active layer of InAs as an application to an optical element. In the figure, 21 is an n-GaAs substrate corresponding to the GaAs tilted substrate 1 described above, and 22
Is n- (AlAs) 3 (GaAs) 3 superlattice, and 23 is Ga
As layer, 24 is InAs active layer, 25 is p-AlGaA
s clad layer, 26 is a p-GaAs cap layer, 27 electrodes, 28 are electrodes.

【0013】このような構成によれば、電極27に正,
電極28に負の電圧を加えることにより、p-AlGa
Asクラッド層25から正孔,n-(AlAs)3(Ga
As)3 超格子22から電子が細線構造であるInAs
活性層24中に供給され、その電子および正孔の状態密
度が一次元化することにより、不連続となり、発振閾値
が低下し、かつ温度に対して安定化する。
According to this structure, the electrode 27 is positive,
By applying a negative voltage to the electrode 28, p-AlGa
From the As clad layer 25, holes, n- (AlAs) 3 (Ga
In) InAs in which electrons have a fine wire structure from the As) 3 superlattice 22.
When the density of states of electrons and holes supplied to the active layer 24 becomes one-dimensional, they become discontinuous, the oscillation threshold is lowered, and the temperature is stabilized with respect to temperature.

【0014】[0014]

【発明の効果】以上、説明したように本発明によれば、
GaAs(001)面から[バー110]方位に傾いた
基板結晶表面上に多数のステップ(段差)を有し、かつ
不均一なテラス幅が存在する場合においても、ステップ
の高さ(段差)を一原子層にかつテラス幅を等間隔に制
御することができる。したがって縦型半導体超格子の周
期の均一性や界面が改善され、かつ超高速の低次元電子
トランジスタあるいは低発振閾値を持つ量子井戸または
量子細線構造レーザなどの製作および特性の向上に優れ
た効果がある。
As described above, according to the present invention,
Even when there are a large number of steps (steps) on the substrate crystal surface tilted from the GaAs (001) plane in the [bar 110] direction and there is a non-uniform terrace width, the step heights (steps) are It is possible to control the monolayer and the terrace width at equal intervals. Therefore, the uniformity of the period and the interface of the vertical semiconductor superlattice are improved, and an excellent effect is obtained in the fabrication and improvement of characteristics of ultrafast low-dimensional electron transistors or quantum wells or quantum wire lasers with a low oscillation threshold. is there.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するための模式図であ
る。
FIG. 1 is a schematic diagram for explaining an embodiment of the present invention.

【図2】超格子周期とテラス幅との関係を示す図であ
る。
FIG. 2 is a diagram showing a relationship between a superlattice period and a terrace width.

【図3】本発明の応用例を示す量子細線構造レーザの模
式図である。
FIG. 3 is a schematic view of a quantum wire laser showing an application example of the present invention.

【図4】従来の(AlAs)1/2(GaAs)1/2縦型半
導体超格子の構成を示す模式図である。
FIG. 4 is a schematic diagram showing a configuration of a conventional (AlAs) 1/2 (GaAs) 1/2 vertical semiconductor superlattice.

【図5】従来の縦型半導体超格子におけるステップの高
さおよびテラス幅が制御されていない場合のGaAsバ
ッファ層表面を示す模式図である。
FIG. 5 is a schematic diagram showing the surface of a GaAs buffer layer when the step height and the terrace width in the conventional vertical semiconductor superlattice are not controlled.

【符号の説明】[Explanation of symbols]

1 GaAs傾斜基板 2 ステップ 3 テラス 4 縦型半導体超格子 5 GaAsバッファ層 6 ステップ 7 テラス 7a 幅の広いテラス 7b 幅の狭いテラス7 8 ステップ 9 テラス 10 AlAs結晶層 11 GaAs結晶層 21 n-GaAs傾斜基板 22 n-(AlAs)3(GaAs)3 超格子 23 GaAs層 24 InAs活性層 25 p-AlGaAsクラッド層 26 p-GaAsキャップ層 27 電極 28 電極1 GaAs inclined substrate 2 step 3 terrace 4 vertical semiconductor superlattice 5 GaAs buffer layer 6 step 7 terrace 7a wide terrace 7b narrow terrace 7 8 step 9 terrace 10 AlAs crystal layer 11 GaAs crystal layer 21 n-GaAs inclination Substrate 22 n- (AlAs) 3 (GaAs) 3 Superlattice 23 GaAs Layer 24 InAs Active Layer 25 p-AlGaAs Clad Layer 26 p-GaAs Cap Layer 27 Electrode 28 Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数の原料原子または原料化合物を順次
切り替えてGaAs(001)面から[バー110]方
向へ傾いた基板結晶表面上に前記原料に応じた少なくと
も2種類の半導体を析出する結晶成長法を用いて縦型半
導体超格子を形成する半導体結晶成長方法において、前
記縦型半導体超格子を形成するに先だって前記基板結晶
表面上に2種類の半導体を一原子層づつまたは数原子層
を一周期とする超格子を数十周期形成することを特徴と
した半導体結晶成長方法。
1. Crystal growth in which a plurality of source atoms or source compounds are sequentially switched to deposit at least two kinds of semiconductors according to the source material on a substrate crystal surface inclined from the GaAs (001) plane in the [bar 110] direction. In a method for growing a semiconductor crystal of a vertical type semiconductor using a vertical method, prior to forming the vertical type semiconductor superlattice, two kinds of semiconductors, one atomic layer or several atomic layers, are formed on the surface of the substrate crystal. A method for growing a semiconductor crystal, which comprises forming several tens of superlattices each having a periodicity.
JP14901492A 1992-05-18 1992-05-18 Semiconductor crystal growth method Expired - Fee Related JP2733725B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14901492A JP2733725B2 (en) 1992-05-18 1992-05-18 Semiconductor crystal growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14901492A JP2733725B2 (en) 1992-05-18 1992-05-18 Semiconductor crystal growth method

Publications (2)

Publication Number Publication Date
JPH05326922A true JPH05326922A (en) 1993-12-10
JP2733725B2 JP2733725B2 (en) 1998-03-30

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Country Status (1)

Country Link
JP (1) JP2733725B2 (en)

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US7064357B2 (en) 2000-01-14 2006-06-20 Sharp Kabushiki Kaisha Nitride compound semiconductor light emitting device and method for producing the same
US7352012B2 (en) 2000-01-14 2008-04-01 Sharp Kabushiki Kaisha Nitride compound semiconductor light emitting device and method for producing the same
US7663158B2 (en) 2000-01-14 2010-02-16 Sharp Kabushiki Kaisha Nitride compound semiconductor light emitting device and method for producing the same
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