JPH05316092A - Frame synchronization detector - Google Patents

Abstract

PURPOSE:To obtain a frame synchronization detector whose circuit scale is reduced and in which all of STM-N (N>=1) of SDH are all coped with the same configuration. CONSTITUTION:A frame synchronization byte number in response to an STM-N is stored in a frame synchronization byte number storage register 6. A counter 7 counts number of times when the synchronization is coincident by a frame synchronization pattern collation device 2. A comparator 9 compares contents of the frame synchronization byte number storage register 6 and the counter 7. When the result of comparison is equal, a counter 8 counts number of times when the synchronization is coincident by a frame synchronization pattern collation device 3. A comparator 10 compares contents of the frame synchronization byte number storage register 6 and the counter 8 to detect the synchronization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to SDH (Synchronous
Digital Hierarchy: Synchronous Digital Hierarchy) is related to the frame synchronization detector used for transmission such as.

[0002]

2. Description of the Related Art FIG. 3 shows the structure of a conventional frame synchronization detector. In FIG. 3, 31 is a data input terminal,
Reference numeral 32 is a plurality of frame synchronization pattern matching devices cascade-connected to the data input terminal 31, 33 is a frame synchronization determination device,
Reference numeral 34 is a frame sync coincidence pulse output terminal.

The above structure will be described in more detail below along with the operation thereof. On the transmission side of the transmission device, a frame synchronization signal is added to the data to indicate the frame position in the data string. Since the receiving side takes out the data, it is necessary to detect the frame synchronization signal in the data string. Then, the data string input to the input terminal 31 is sequentially taken into the register in the frame synchronization pattern matching device 32 and matched with the frame synchronization pattern. In this way, when the frame synchronization patterns in the data string are collated by each frame synchronization pattern collator 32, the frame synchronization determiner 33
Outputs the frame synchronization coincidence pulse to the frame synchronization coincidence pulse output terminal 34, and the frame synchronization can be detected.

[0004]

However, in the above-mentioned conventional frame synchronization detector, it is necessary to have the collator 32 for the frame synchronization pattern having the number of stages corresponding to the number of frame synchronization bytes, and the SDH STM (Synchronous trance).
ansfer module: Synchronous transfer module) -N requires a 3N-stage frame synchronization pattern collator 32, which increases the circuit scale. Further, since the frame synchronization patterns to be compared are fixed, there is a problem that it is necessary to prepare the frame synchronization pattern collating device with the number of stages corresponding to each STM-N of SDH.

The present invention solves such a conventional problem, can reduce the circuit scale, and
It is an object of the present invention to provide a frame synchronization detector capable of supporting STM-N (N ≧ 1) with the same circuit configuration and improving the economical efficiency.

[0006]

In order to achieve the above object, the present invention comprises a collator for detecting a frame synchronization pattern, a counter for counting the number of frame synchronization matches, and a register for storing the number of frame synchronization bytes. A comparator for comparing the number of frame synchronization bytes with the counter value is provided.

[0007]

Therefore, according to the present invention, since the synchronization is detected using the frame synchronization pattern matching device and the counter,
The frame synchronization pattern matching device can be reduced.
Further, by writing the number of frame synchronization bytes corresponding to STM-N of SDH to the register, it is possible to support all STM-N with the same circuit configuration.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the structure of a frame synchronization detector according to an embodiment of the present invention.

In FIG. 1, 1 is a data input terminal, 2,
3 is a frame synchronization pattern collator for collating the frame synchronization pattern in the data string input from the input terminal 1;
Is a channel multiplex number input terminal, 5 is an arithmetic unit for converting the channel multiplex number input from the input terminal 4 into the number of frame synchronization bytes, 6 is a register for storing the number of frame synchronization bytes converted by the arithmetic unit 5, 7, 8 is a counter that counts the number of times of synchronization coincidence in the frame synchronization pattern matching devices 2 and 3, and 9 is a frame synchronization byte number storage register 6
Is a comparator for comparing the value of 1 to the values of the counters 7 and 8, and 11 is a frame sync coincidence pulse output terminal for outputting a sync coincidence pulse.

The above construction will be described in more detail below together with its operation with reference to the flow chart shown in FIG.

First, the channel multiplex number N is input from the channel multiplex number input terminal 4 (step 21). Next, the channel multiplexing number N is converted into the number of frame synchronization bytes by the arithmetic unit 5 and written in the frame synchronization byte number storage register 6 (step 22). Next, the frame synchronizing pattern collator 2 collates the data string input from the input terminal 1 with the frame synchronizing pattern (step 23). If the collation results do not match, the counter 7 is reset (step 23-1). On the other hand, if the collation results match, the counter 7 counts up by 1 (step 24), and the value of the frame synchronization byte number storage register 6 and the value of the counter 7 are compared by the comparator 9 (step 25). As a result of the comparison, if they do not match, the process returns to step 23. If they match, the data string input from the input terminal 1 and the frame sync pattern are checked by the frame sync pattern checker 3 (step 26). If the collation results do not match, the counter 8 is reset (step 26-1), the process returns to step 23-1, the counter 7 is reset, and the process returns to step 23. On the other hand, if the collation result by the frame synchronization pattern collator 3 is the same in step 26,
The counter 8 counts up by 1 (step 27).
Next, the value of the frame synchronization byte number storage register 6 and the value of the counter 8 are compared by the comparator 10 (step 28).
If they do not match as a result of the comparison, the process returns to step 26. If they match, it is considered that a frame synchronization pattern has been detected, and a frame synchronization matching pulse is output to the output terminal 11.

As described above, according to the above embodiment, the counter 7 counts up when the frame sync pattern collator 2 continuously detects pattern matches, and the counter 8 when the frame sync pattern collator 3 continuously detects pattern matches. Will count up. When the same frame synchronization pattern continues as in SDH, counters 7 and 8 are provided instead of connecting the collating devices in cascade as in the above-mentioned conventional example, and the number of times of frame synchronization coincidence for two stages is counted. , The synchronization can be detected, so the number of stages of the frame synchronization pattern matching device is reduced to two, that is, 2
This has an advantage that the number of (3N-1) (N ≧ 1) stages of frame synchronization pattern matching devices can be reduced. Also,
According to the above-described embodiment, the STM can be formed in the same circuit by only changing the channel multiplex number input to the channel multiplex number input terminal 4.
It has the advantage that it can handle all -N (N ≧ 1).

[0014]

As described above, according to the present invention, the frame synchronization is detected using the frame synchronization pattern collator and the counter, so that it is possible to reduce the number of frame synchronization pattern collators and therefore the circuit scale is reduced. Can be reduced. Further, since the same circuit can handle all STM-N (N ≧ 1), it is possible to improve the economical efficiency.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a frame synchronization detector according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a control procedure of the frame synchronization detector.

FIG. 3 is a schematic block diagram showing a conventional frame synchronization detector.

[Explanation of symbols]

 1 data input terminal 2 frame sync pattern collator 3 frame sync pattern collator 4 channel multiplexed number input terminal 5 arithmetic unit 6 frame sync byte number storage register 7 counter 8 counter 9 comparator 10 comparator 11 frame sync match pulse output terminal

Claims (1)

[Claims] 1. A collator that detects a frame synchronization pattern, a counter that counts the number of frame synchronization matches, a register that stores the number of frame synchronization bytes, and a comparator that compares the number of frame synchronization bytes with a counter value. Frame sync detector with.