JPH05315814A - Irreversible circuit element - Google Patents

Irreversible circuit element

Info

Publication number
JPH05315814A
JPH05315814A JP4146392A JP14639292A JPH05315814A JP H05315814 A JPH05315814 A JP H05315814A JP 4146392 A JP4146392 A JP 4146392A JP 14639292 A JP14639292 A JP 14639292A JP H05315814 A JPH05315814 A JP H05315814A
Authority
JP
Japan
Prior art keywords
electrode
matching circuit
ferrite
positioning member
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4146392A
Other languages
Japanese (ja)
Other versions
JP3175303B2 (en
Inventor
Keiji Okamura
圭司 岡村
Hiromoto Dejima
弘基 出嶌
Takashi Kawanami
崇 川浪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP14639292A priority Critical patent/JP3175303B2/en
Publication of JPH05315814A publication Critical patent/JPH05315814A/en
Application granted granted Critical
Publication of JP3175303B2 publication Critical patent/JP3175303B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Non-Reversible Transmitting Devices (AREA)

Abstract

PURPOSE:To improve the reliability against the connection and to enhance the productivity by preventing the positional deviation when matching circuit elements are connected while making components small. CONSTITUTION:Plural center conductors 7 arranged interdigitally at every prescribed interval in an electric insulation state are disposed to a ferrite 6 to form a ferrite element 3 and matching circuit elements 19, 20 are connected to one end part 7a of each of center conductors 7 to form the irreversible circuit element 1, then a ferrite element 3 and the matching circuit elefments 19, 20 are disposed on an electrode substrate 10 on which port electrodes 12a-12c are formed. Furthermore, a positioning member 21 having a recessed part 22 with a size to surround the matching circuit elements 19, 20 is formed. Then the positioning member 21 is arranged on the electrode substrate 10 so as to cover the matching circuit elements 19, 20 by its recessed part, one end part 7a of the center conductor 7 is connected to the port electrodes 12a-12c in such state and the matching circuit elements 19, 20 are connected thereto.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、非可逆回路素子、例え
ばアイソレータ,サーキュレータに関し、特に部品の小
型化を図りながら、整合回路素子を接続する際の位置ず
れを防止して接続に対する信頼性を向上できるととも
に、生産性を向上できるようにした構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-reciprocal circuit device such as an isolator and a circulator, and particularly, the miniaturization of parts is prevented, and the positional deviation when connecting the matching circuit device is prevented to improve the reliability of the connection. The present invention relates to a structure capable of improving productivity as well as improving.

【0002】[0002]

【従来の技術】一般に、アイソレータ,サーキュレータ
は、信号の伝送方向のみ通過させ、逆方向への伝送を阻
止する機能を有しており、例えば携帯電話,自動車電話
等の移動通信機器に不可欠な部品である。このようなア
イソレータの一例として、従来、図5に示す構造のもの
がある。このアイソレータ40は、磁性体製金属からな
る下部ヨーク41上にアース板42,誘電体基板43を
配設するとともに、3本の中心導体44にフェライト4
5を配設してなるフェライト素子46を配設し、上記下
部ヨーク41に上部ヨーク47を挿着して磁気閉回路を
構成するとともに、この上部ヨーク47の内面に永久磁
石48を貼着し、該磁石48により上記フェライト素子
46に直流磁界を印加するよう構成されている。このよ
うなアイソレータ40において整合容量を得る場合、従
来、上記誘電体基板43の上面に印刷,エッチング等に
より3つのコンデンサ電極50〜52をパターン形成す
るとともに、下面全面にアース電極53を形成し、該基
板43を挟んで対向する各電極50〜52,53間で容
量をとるようにしている。また上記2つのコンデンサ電
極50,51には入出力端子54が接続されており、1
つのコンデンサ電極52には厚膜印刷により終端抵抗膜
55が形成されている。
2. Description of the Related Art Generally, isolators and circulators have a function of passing signals only in the transmission direction and blocking the transmission in the opposite direction, and are indispensable parts for mobile communication devices such as mobile phones and car phones. Is. As an example of such an isolator, there is conventionally one having a structure shown in FIG. In this isolator 40, a ground plate 42 and a dielectric substrate 43 are arranged on a lower yoke 41 made of a magnetic metal, and three central conductors 44 are provided with a ferrite 4 core.
A ferrite element 46 including 5 is arranged, an upper yoke 47 is inserted into the lower yoke 41 to form a magnetic closed circuit, and a permanent magnet 48 is attached to the inner surface of the upper yoke 47. The magnet 48 is configured to apply a DC magnetic field to the ferrite element 46. To obtain a matching capacitance in such an isolator 40, conventionally, three capacitor electrodes 50 to 52 are patterned on the upper surface of the dielectric substrate 43 by printing, etching, etc., and the ground electrode 53 is formed on the entire lower surface, Capacitance is set between the electrodes 50 to 52, 53 facing each other with the substrate 43 interposed therebetween. An input / output terminal 54 is connected to the above two capacitor electrodes 50 and 51.
A terminating resistance film 55 is formed on one of the capacitor electrodes 52 by thick film printing.

【0003】[0003]

【発明が解決しようとする課題】ところで上記アイソレ
ータ40においては、その用途からして部品の小型化が
要求されている。しかしながら上記従来のアイソレータ
40では、整合容量を誘電体基板43にパターン形成し
たコンデンサ電極50〜52で得る構造であるから、必
要容量を得るには電極面積を大きくしなければならず、
それだけ誘電体基板43が大型化し、部品の小型化に対
応できないという問題がある。
By the way, in the above-mentioned isolator 40, miniaturization of parts is required due to its application. However, in the above-mentioned conventional isolator 40, since the matching capacitance is obtained by the capacitor electrodes 50 to 52 patterned on the dielectric substrate 43, the electrode area must be increased to obtain the required capacitance.
As a result, the size of the dielectric substrate 43 becomes large, and there is a problem that it is not possible to cope with the miniaturization of parts.

【0004】ここで、本件発明者らは、図3に示すよう
に、整合容量をチップコンデンサで得ることに着目し
た。これは樹脂等からなる電極基板30に図示しない各
中心導体の一端部が接続されるポート電極31を形成す
るとともに、各ポート電極31に対応した部分にギャッ
プを設けてアース電極32を形成する。そして、この電
極基板30上の各ポート電極31にチップコンデンサ3
3の一方の電極33aを接続し、他方の電極33bを上
記アース電極32に接続するとともに、上記何れか1つ
のポート電極31に終端チップ抵抗34の一方の電極3
4aを、他方の電極34bをアース電極32に接続す
る。これによれば、例えば0.5 ×0.5 ×1.0mm 程度の大
きさのチップコンデンサ33で必要な整合容量を得るこ
とができ、その結果従来の誘電体基板にコンデンサ電極
を形成する場合に比べて基板を小さくでき、それだけ小
型化に対応できる。
Here, the inventors of the present invention have paid attention to obtaining a matching capacitance with a chip capacitor as shown in FIG. This forms a port electrode 31 to which one end of each center conductor (not shown) is connected to an electrode substrate 30 made of resin or the like, and forms a ground electrode 32 by providing a gap at a portion corresponding to each port electrode 31. The chip capacitor 3 is attached to each port electrode 31 on the electrode substrate 30.
3 is connected to one electrode 33a, the other electrode 33b is connected to the ground electrode 32, and one of the electrodes 3 of the terminal chip resistor 34 is connected to any one of the port electrodes 31.
4a, the other electrode 34b is connected to the ground electrode 32. According to this, the required matching capacitance can be obtained with the chip capacitor 33 having a size of, for example, 0.5 × 0.5 × 1.0 mm, and as a result, the substrate can be made smaller than in the case of forming the capacitor electrode on the conventional dielectric substrate. It can be made smaller and can be made smaller accordingly.

【0005】ところで、このような電極基板30に各チ
ップコンデンサ33,チップ抵抗34を半田付け接続す
る場合、各ポート電極31,アース電極32に半田膜を
印刷し、これに各チップ部品の電極を例えばリフロー半
田付けして接続する。この場合、図4(a) に示すよう
に、チップコンデンサ33が位置ずれして接続不良を起
こしたり、あるいは図4(b) に示すように、チップコン
デンサ33が起立したりするツームストーン現象が生じ
る場合があり、接続に対する信頼性を低くするととも
に、生産性を低下させるという問題が生じる。このよう
な位置ずれ等を防止するには、電極基板の各ポート電極
のパターンや半田膜の膜厚等を最適化することが考えら
れるが、現状では確実に位置ずれを防止できる手段とは
言えない。
When the chip capacitors 33 and the chip resistors 34 are soldered to the electrode substrate 30 as described above, solder films are printed on the port electrodes 31 and the ground electrodes 32, and the electrodes of the chip components are printed on the solder films. For example, reflow soldering is used for connection. In this case, there is a tombstone phenomenon in which the chip capacitor 33 is displaced and a connection failure occurs as shown in FIG. 4 (a), or the chip capacitor 33 rises as shown in FIG. 4 (b). This may occur, which lowers reliability of connection and lowers productivity. In order to prevent such misalignment, it is conceivable to optimize the pattern of each port electrode of the electrode substrate, the film thickness of the solder film, etc., but at present it can be said that it is a means that can reliably prevent misalignment. Absent.

【0006】本発明は上記従来の状況に鑑みてなされた
もので、部品の小型化を図りながら、半田付け時の位置
ずれ等を防止して接続に対する信頼性を向上でき、さら
には生産性を向上できる非可逆回路素子を提供すること
を目的としている。
The present invention has been made in view of the above-mentioned conventional situation, and it is possible to prevent misalignment at the time of soldering and to improve the reliability of connection while reducing the size of parts, and further to improve the productivity. An object is to provide a non-reciprocal circuit device that can be improved.

【0007】[0007]

【課題を解決するための手段】そこで本発明は、フェラ
イトに電気的絶縁状態で、かつ所定間隔ごとに交差状に
配置された複数の中心導体を配設してなるフェライト素
子の、該各中心導体の一端部に整合回路素子を接続して
なる非可逆回路素子において、ポート電極が形成された
電極基板上に、上記フェライト素子,及び各整合回路素
子を配置し、該各整合回路素子を囲う大きさの凹部を有
する位置決め部材を形成し、この位置決め部材をこれの
各凹部で各整合回路素子を被せて上記電極基板上に配置
し、この状態で上記ポート電極に上記中心導体の一端部
を接続するとともに、各整合回路素子を接続したことを
特徴としている。
SUMMARY OF THE INVENTION Therefore, the present invention is directed to a ferrite element in which a plurality of center conductors arranged in an electrically insulated state and arranged in a cross shape at predetermined intervals are arranged in the ferrite. In a nonreciprocal circuit element in which a matching circuit element is connected to one end of a conductor, the ferrite element and each matching circuit element are arranged on an electrode substrate on which a port electrode is formed, and each matching circuit element is surrounded. A positioning member having a recess having a size is formed, and the positioning member is placed on the electrode substrate by covering each matching circuit element with each recess of the positioning member. In this state, one end of the center conductor is attached to the port electrode. It is characterized in that each matching circuit element is connected together with the connection.

【0008】ここで、上記位置決め部材には、例えば樹
脂,あるいは半田の着かないアルミ金属を採用できる。
また上記位置決め部材は、これを治具として使用し、接
続後に取り外すようにしてもよく、あるいは部品の1つ
として回路素子内にそのまま組み込んでもよい。
Here, for the positioning member, for example, resin or aluminum metal without solder can be used.
The positioning member may be used as a jig and removed after connection, or may be directly incorporated in the circuit element as one of the components.

【0009】[0009]

【作用】本発明の非可逆回路素子を組立てるには、電極
基板の各ポート電極の表面に例えば印刷によりクリーム
半田を塗布し、この電極基板にフェライト素子,及び各
非可逆回路素子を配置するとともに、上記各ポート電極
上に中心導体の一端部,及び非可逆回路素子を配置す
る。次いで上記電極基板に位置決め部材をこれの各凹部
で上記各非可逆回路素子を被せるように配置する。これ
により各非可逆回路素子の上下,左右方向の移動が規制
されて位置決めされる。この状態で例えばリフロー半田
付けにより、上記各電極同士を接続する。
To assemble the nonreciprocal circuit device of the present invention, cream solder is applied to the surface of each port electrode of the electrode substrate by printing, for example, and the ferrite element and each nonreciprocal circuit device are arranged on this electrode substrate. , One end of the center conductor and the non-reciprocal circuit element are arranged on each of the port electrodes. Next, a positioning member is arranged on the electrode substrate so as to cover the non-reciprocal circuit elements with the recesses of the positioning member. As a result, the vertical and horizontal movements of the non-reciprocal circuit elements are restricted and positioned. In this state, the electrodes are connected to each other by, for example, reflow soldering.

【0010】このように本発明に係る非可逆回路素子に
よれば、位置決め部材に凹部を形成し、この凹部で整合
回路素子を上部から覆い被せて位置決めしたので、半田
付けする際の整合回路素子の位置ずれや起立の問題を確
実に防止できる。その結果、接続に対する信頼性を向上
できるとともに、歩留まりを向上できる分だけ生産性を
向上できる。また、従来の誘電体基板にコンデンサ電極
をパターン形成する場合に比べて基板を小さくでき、上
述の小型化の要求に対応できる。
As described above, according to the non-reciprocal circuit device of the present invention, since the positioning member is formed with the concave portion and the matching circuit element is covered by the concave portion from the upper portion and positioned, the matching circuit element at the time of soldering is formed. It is possible to reliably prevent the problem of misalignment and standing. As a result, the reliability of the connection can be improved, and the productivity can be improved by the yield. Further, the substrate can be made smaller than in the case where the capacitor electrodes are formed by patterning on the conventional dielectric substrate, and the above-mentioned demand for miniaturization can be met.

【0011】[0011]

【実施例】以下、本発明の実施例を図について説明す
る。図1及び図2は本発明の一実施例による非可逆回路
素子を説明するための図であり、本実施例では、集中定
数型のアイソレータに適用した場合を例にとって説明す
る。図において、1は集中定数型のアイソレータであ
り、これは磁性体金属からなる下部ヨーク2内にフェラ
イト素子3を配設し、この下部ヨーク2に同じく磁性体
金属からなる上部ヨーク4を装着して磁気閉回路を構成
するとともに、上記上部ヨーク4の内面に永久磁石5を
貼着し、該永久磁石5により上記フェライト素子3に直
流磁界を印加するように構成されている。
Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are diagrams for explaining a non-reciprocal circuit device according to an embodiment of the present invention. In the present embodiment, a case of application to a lumped constant type isolator will be described as an example. In the figure, reference numeral 1 is a lumped-constant type isolator, in which a ferrite element 3 is arranged in a lower yoke 2 made of magnetic metal, and an upper yoke 4 made of magnetic metal is mounted on the lower yoke 2. And a permanent magnet 5 is attached to the inner surface of the upper yoke 4, and a DC magnetic field is applied to the ferrite element 3 by the permanent magnet 5.

【0012】上記フェライト素子3は円板状のフェライ
ト6の上面,及び下面に、該フェライト6を挟んで対向
する3本の中心導体7を挿着して構成されている。この
各中心導体7は、帯状の金属板を略コ字状に折り曲げ形
成されたもので、各中心導体7は上記フェライト6の両
面の直径方向に延び、かつ絶縁シート8を介して互いに
120 度の角度をなして交差状に配置されている。また、
上記各中心導体7の一端部7aはフェライト6から突出
しており、他端部7bはフェライト6の下面の外縁部に
位置している。
The ferrite element 3 is constructed by inserting three center conductors 7 facing each other with the ferrite 6 sandwiched between the upper surface and the lower surface of a disk-shaped ferrite 6. Each of the central conductors 7 is formed by bending a strip-shaped metal plate into a substantially U shape, and each of the central conductors 7 extends in the diametrical direction on both surfaces of the ferrite 6 and has an insulating sheet 8 therebetween.
They are arranged in a cross shape with an angle of 120 degrees. Also,
One end 7a of each of the central conductors 7 projects from the ferrite 6, and the other end 7b is located at the outer edge of the lower surface of the ferrite 6.

【0013】上記下部ヨーク2の底壁上には平板状の電
極基板10が配設されており、この電極基板10は樹脂
部材に後述する各電極に応じた形状の金属部材をインサ
ート形成して製造されたものである。上記電極基板10
の中央部に形成された凹部10a上には上記フェライト
素子3が配設されており、この凹部10aにより上記フ
ェライト6下面の各中心導体7の重なりによる厚さを吸
収している。
A flat plate-shaped electrode substrate 10 is arranged on the bottom wall of the lower yoke 2. The electrode substrate 10 is formed by inserting a metal member having a shape corresponding to each electrode described later into a resin member. It is manufactured. The electrode substrate 10
The ferrite element 3 is disposed on a recess 10a formed in the center of the ferrite core 3, and the recess 10a absorbs the thickness of the central conductors 7 on the lower surface of the ferrite 6 due to the overlap.

【0014】また、上記電極基板10の凹部10aの周
縁部にはアース電極11が120 度の間隔をあけて形成さ
れており、この各アース電極11は電極基板10の下面
に導出して上記下部ヨーク2に接続されている。上記電
極基板10の各アース電極11の外側には、該電極11
との間にギャップを設けて第1〜第3ポート電極12a
〜12cが形成されている。この各電極12a〜12c
と上記アース電極11との間には溝部13が凹設されて
おり、この溝部13により両電極同士がショートするの
を防止している。
Further, the ground electrodes 11 are formed at intervals of 120 degrees on the periphery of the recess 10a of the electrode substrate 10, and each of the ground electrodes 11 is led out to the lower surface of the electrode substrate 10 and the lower part thereof is formed. It is connected to the yoke 2. Outside the ground electrodes 11 of the electrode substrate 10, the electrodes 11 are
A gap between the first and third port electrodes 12a
~ 12c are formed. These electrodes 12a to 12c
A groove 13 is provided between the ground electrode 11 and the ground electrode 11, and the groove 13 prevents short-circuiting between the electrodes.

【0015】上記電極基板10の一側縁の両端部には上
記第1,第2ポート電極12a,12bとの間にギャッ
プを設けてアース電極14が形成されており、この各ア
ース電極14は下部ヨーク2に接続されている。また、
上記電極基板10の他端縁の両端部分には上記第3ポー
ト電極12cとの間にギャップを設けてアース電極15
が形成されている。さらに上記電極基板10の左, 右側
面の一端部には入出力端子16が形成されており、この
各端子16は上記第1,第2ポート電極12a,12b
に接続されている。また上記電極基板10の左, 右側面
の他端部にはアース端子17が形成されており、この各
アース端子17は上記アース電極15に接続されてい
る。この各端子16,17は下部ヨーク2の開口2aか
ら外方に露出している。
A ground electrode 14 is formed at both ends of one side edge of the electrode substrate 10 with a gap provided between the ground electrode 14 and the first and second port electrodes 12a and 12b. It is connected to the lower yoke 2. Also,
A gap is formed between the other end of the electrode substrate 10 and the third port electrode 12c so that the ground electrode 15 is provided.
Are formed. Further, input / output terminals 16 are formed on one end of the left and right side surfaces of the electrode substrate 10, and each of the terminals 16 has the first and second port electrodes 12a, 12b.
It is connected to the. Further, ground terminals 17 are formed on the other ends of the left and right side surfaces of the electrode substrate 10, and each ground terminal 17 is connected to the ground electrode 15. The terminals 16 and 17 are exposed outward from the opening 2a of the lower yoke 2.

【0016】また、上記電極基板10の第1〜第3ポー
ト電極12a〜12cには上記フェライト素子3の各中
心導体7の一端部7aが接続されており、他端部7bは
上記アース電極11に接続されている。
One end 7a of each central conductor 7 of the ferrite element 3 is connected to the first to third port electrodes 12a to 12c of the electrode substrate 10, and the other end 7b is connected to the earth electrode 11. It is connected to the.

【0017】上記電極基板10の第1,第2ポート電極
12a,12b、及び第3ポート電極12cの一端部に
はそれぞれチップコンデンサ19が配置されており、第
3ポート電極12cの他端部には終端チップ抵抗20が
配置されている。上記各チップコンデンサ19の一方の
電極19aは上記第1〜第3ポート電極12a〜12c
に当接しており、他方の電極19bはアース電極14,
15に当接している。また上記チップ抵抗20の一方の
電極20aは第3ポート電極12cに、他方の電極20
bはアース電極15にそれぞれ当接している。
A chip capacitor 19 is arranged at one end of each of the first and second port electrodes 12a and 12b and the third port electrode 12c of the electrode substrate 10, and at the other end of the third port electrode 12c. Has a terminating chip resistor 20. One electrode 19a of each chip capacitor 19 is the first to third port electrodes 12a to 12c.
The other electrode 19b is in contact with the ground electrode 14,
It is in contact with 15. Further, one electrode 20a of the chip resistor 20 serves as the third port electrode 12c and the other electrode 20a
b contacts the ground electrode 15, respectively.

【0018】そして、上記電極基板10上には、本実施
例の特徴をなす位置決め部材21が配設されている。こ
れは樹脂からなる大略板枠状のもので、これの中央部に
は上記永久磁石5が挿入される大径穴21aとこれに続
いて上記フェライト素子3が挿入される小径穴21bが
形成されている。また、上記位置決め部材21の下面の
四隅には矩形状の凹部22が凹設されている。この各凹
部22は上記各チップコンデンサ19,チップ抵抗20
を囲う大きさのもので、この凹部22により各コンデン
サ19,抵抗20の上部は覆い被せられており、これに
より上下,左右方向への移動が規制されている。そし
て、この状態で各チップコンデンサ19の一方の電極1
9aは上記第1〜第3ポート電極12a〜12cに半田
付け接続されており、他方の電極19bはアース電極1
4,15に半田付け接続されている。また上記チップ抵
抗20の一方の電極20aは第3ポート電極12cに、
他方の電極20bはアース電極15にそれぞれ半田付け
接続されている。
A positioning member 21, which characterizes this embodiment, is provided on the electrode substrate 10. This is a substantially plate frame made of resin, and a large diameter hole 21a into which the permanent magnet 5 is inserted and a small diameter hole 21b into which the ferrite element 3 is inserted are formed in the center of the hole. ing. Further, rectangular recesses 22 are provided at the four corners of the lower surface of the positioning member 21. The recesses 22 are formed by the chip capacitors 19 and the chip resistors 20.
The concave portions 22 cover the upper portions of the capacitors 19 and the resistors 20, thereby restricting the movement in the vertical and horizontal directions. Then, in this state, one electrode 1 of each chip capacitor 19
9a is soldered to the first to third port electrodes 12a to 12c, and the other electrode 19b is the ground electrode 1
4 and 15 are connected by soldering. Further, one electrode 20a of the chip resistor 20 serves as the third port electrode 12c,
The other electrode 20b is soldered and connected to the ground electrode 15.

【0019】次に本実施例の作用効果についけ説明す
る。本実施例のアイソレータ1を組立てるには、電極基
板10の各電極の表面にスクリーン印刷によりクリーム
半田を塗布し、この基板10を下部ヨーク2の底壁上に
配置する。また各チップコンデンサ19,チップ抵抗2
0を各ポート電極12a〜12c,及び各アース電極1
4,15上の所定位置に配置し、さらにフェライト素子
3を凹部10a内に配置するとともに、各中心導体7の
一端部7aをポート電極12a〜12cに、他端部7b
をアース電極11上に配置する。次いで、上記電極基板
10上に位置決め部材21を配置し、これの小径穴21
b内にフェライト素子3を挿入して位置決めするととも
に、これの各凹部22内に上記各チップコンデンサ1
9,チップ抵抗20を嵌め込む。これにより各チップコ
ンデンサ19,チップ抵抗20は凹部22で覆い被せら
れることから、移動することなく位置決めされる。この
状態でリフロー半田付けして接続する。この後下部ヨー
ク2に上部ヨーク4を嵌装する。
Next, the operation and effect of this embodiment will be described. To assemble the isolator 1 of this embodiment, cream solder is applied to the surface of each electrode of the electrode substrate 10 by screen printing, and the substrate 10 is placed on the bottom wall of the lower yoke 2. Also, each chip capacitor 19 and chip resistor 2
0 for each port electrode 12a-12c and each ground electrode 1
4 and 15, the ferrite element 3 is further arranged in the recess 10a, and one end 7a of each central conductor 7 is used as the port electrodes 12a to 12c and the other end 7b.
On the ground electrode 11. Next, the positioning member 21 is arranged on the electrode substrate 10 and the small diameter hole 21 of the positioning member 21 is arranged.
The ferrite element 3 is inserted and positioned in b, and the chip capacitors 1 are placed in the recesses 22 of the ferrite element 3.
9. Insert the chip resistor 20. As a result, the chip capacitors 19 and the chip resistors 20 are covered with the recesses 22, so that they are positioned without moving. In this state, reflow soldering is performed for connection. After this, the upper yoke 4 is fitted on the lower yoke 2.

【0020】このように本実施例によれば、位置決め部
材21の四隅に各チップコンデンサ19,チップ抵抗2
0を囲う凹部22を形成し、この凹部22で覆い被せて
位置決めしたので、半田付けする際の位置ずれや起立を
確実に防止でき、接続に対する信頼性を向上できるとと
もに、生産性を向上できる。また、本実施例では、チッ
プコンデンサ19で整合容量を得ることから、従来の誘
電体基板にコンデンサ電極をパターン形成する場合に比
べて基板を小さくでき、その分だけ小型化に対応でき
る。さらに、上記位置決め部材21に大径穴21a,小
径穴21bを形成し、これに永久磁石5,フェライト素
子3を挿入したので、位置決め部材21の厚さを吸収で
き、部品の大型化を回避できる。
As described above, according to this embodiment, the chip capacitors 19 and the chip resistors 2 are provided at the four corners of the positioning member 21.
Since the concave portion 22 surrounding 0 is formed and the concave portion 22 is covered with the concave portion 22 and positioned, it is possible to reliably prevent the positional deviation and the standing up at the time of soldering, and it is possible to improve the reliability of the connection and the productivity. Further, in the present embodiment, since the matching capacitance is obtained by the chip capacitor 19, the substrate can be made smaller than that in the case where the capacitor electrode is patterned on the conventional dielectric substrate, and the size can be correspondingly reduced. Further, since the large diameter hole 21a and the small diameter hole 21b are formed in the positioning member 21 and the permanent magnet 5 and the ferrite element 3 are inserted therein, the thickness of the positioning member 21 can be absorbed and the enlargement of parts can be avoided. ..

【0021】なお、上記実施例では、位置決め部材21
をそのままアイソレータ1内に組み込んだ場合を例にと
って説明したが、本発明はチップコンデンサを接続した
後、上記位置決め部材を取り外してもよく、また上記位
置決め部材21を半田の着かないアルミ等の金属で構成
してもよい。
In the above embodiment, the positioning member 21
Although the description has been made by taking as an example the case where the above is incorporated into the isolator 1 as it is, the present invention may remove the positioning member after connecting the chip capacitor, and the positioning member 21 may be made of a metal such as aluminum without soldering. You may comprise.

【0022】また、上記実施例ではアイソレータに適用
したが、本発明は勿論サーキュレータにも適用できると
ともに、他の高周波部品にも適用できる。さらに上記実
施例では、樹脂に金属部材をインサートして電極基板を
構成したが、本発明は例えばプリント基板を採用しても
よい。
Although the above embodiment is applied to the isolator, the present invention can of course be applied to a circulator and other high frequency components. Furthermore, in the above-mentioned embodiment, the electrode member is formed by inserting the metal member into the resin, but the present invention may employ a printed circuit board, for example.

【0023】[0023]

【発明の効果】以上のように本発明に係る非可逆回路素
子によれば、整合回路素子を囲う大きさの凹部を有する
位置決め部材を形成し、この位置決め部材をこれの各凹
部で各整合回路素子を被せるようにして電極基板上に配
置し、この状態でポート電極に中心導体の一端部を接続
するとともに、各整合回路素子を接続したので、部品の
小型化を図りながら、半田付けする際の整合回路素子の
位置ずれを防止でき、接続に対する信頼性を向上できる
とともに、生産性を向上できる効果がある。
As described above, according to the non-reciprocal circuit device of the present invention, a positioning member having a recess having a size enclosing the matching circuit device is formed, and the positioning member is provided in each recess of each matching circuit. Since it is placed on the electrode substrate so as to cover the element, and in this state, one end of the center conductor is connected to the port electrode and each matching circuit element is connected, it is possible to reduce the size of the component while soldering. The position shift of the matching circuit element can be prevented, the reliability of connection can be improved, and the productivity can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例によるアイソレータを説明す
るための分解斜視図である。
FIG. 1 is an exploded perspective view illustrating an isolator according to an exemplary embodiment of the present invention.

【図2】上記実施例のアイソレータの各部品を示す分解
斜視図である。
FIG. 2 is an exploded perspective view showing each part of the isolator of the above embodiment.

【図3】本発明の成立過程を説明するための分解斜視図
である。
FIG. 3 is an exploded perspective view for explaining a formation process of the present invention.

【図4】本発明の成立過程を示す斜視図である。FIG. 4 is a perspective view showing a formation process of the present invention.

【図5】従来のアイソレータを示す分解斜視図である。FIG. 5 is an exploded perspective view showing a conventional isolator.

【符号の説明】[Explanation of symbols]

1 アイソレータ(非可逆回路素子) 3 フェライト素子 6 フェライト 7 中心導体 7a 中心導体の一端部 12a〜12c ポート電極 19 チップコンデンサ(整合回路素子) 20 終端チップ抵抗(非可逆回路素子) 21 位置決め部材 22 凹部 1 Isolator (Non-Reciprocal Circuit Element) 3 Ferrite Element 6 Ferrite 7 Central Conductor 7a One End of Central Conductor 12a-12c Port Electrode 19 Chip Capacitor (Matching Circuit Element) 20 Termination Chip Resistor (Non-Reciprocal Circuit Element) 21 Positioning Member 22 Recess

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 フェライトに電気的絶縁状態で、かつ所
定間隔ごとに交差状に配置された複数の中心導体を配設
してなるフェライト素子の、該各中心導体の一端部に整
合回路素子を接続してなる非可逆回路素子において、ポ
ート電極が形成された電極基板上に、上記フェライト素
子,及び各整合回路素子を配置し、該各整合回路素子を
囲う大きさの凹部を有する位置決め部材を形成し、この
位置決め部材をこれの各凹部で各整合回路素子を覆い被
せて上記電極基板上に配置し、この状態で上記各ポート
電極に上記中心導体の一端部を接続するとともに、各整
合回路素子を接続したことを特徴とする非可逆回路素
子。
1. A ferrite element having a plurality of center conductors arranged in an electrically insulated state in a ferrite and arranged in a cross shape at predetermined intervals, and a matching circuit element is provided at one end of each center conductor. In the connected nonreciprocal circuit element, the ferrite element and each matching circuit element are arranged on an electrode substrate on which a port electrode is formed, and a positioning member having a concave portion having a size enclosing each matching circuit element is provided. The positioning member is formed on the electrode substrate by covering the matching circuit elements with the respective recesses, and in this state, one end of the center conductor is connected to each of the port electrodes and each matching circuit is formed. A non-reciprocal circuit element characterized by connecting elements.
JP14639292A 1992-05-12 1992-05-12 Non-reciprocal circuit device Expired - Lifetime JP3175303B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14639292A JP3175303B2 (en) 1992-05-12 1992-05-12 Non-reciprocal circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14639292A JP3175303B2 (en) 1992-05-12 1992-05-12 Non-reciprocal circuit device

Publications (2)

Publication Number Publication Date
JPH05315814A true JPH05315814A (en) 1993-11-26
JP3175303B2 JP3175303B2 (en) 2001-06-11

Family

ID=15406666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14639292A Expired - Lifetime JP3175303B2 (en) 1992-05-12 1992-05-12 Non-reciprocal circuit device

Country Status (1)

Country Link
JP (1) JP3175303B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420941B2 (en) * 1997-09-17 2002-07-16 Murata Manufacturing Co., Ltd. Nonreciprocal circuit device
US6483394B2 (en) * 1999-12-16 2002-11-19 Samsung Electro-Mechanics Co., Ltd. Isolator with capacitors and chip resistors located outside of the housing

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101623911B1 (en) * 2015-11-25 2016-05-24 김예림 Assembly for bisycle handle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420941B2 (en) * 1997-09-17 2002-07-16 Murata Manufacturing Co., Ltd. Nonreciprocal circuit device
US6483394B2 (en) * 1999-12-16 2002-11-19 Samsung Electro-Mechanics Co., Ltd. Isolator with capacitors and chip resistors located outside of the housing

Also Published As

Publication number Publication date
JP3175303B2 (en) 2001-06-11

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