JPH05315595A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPH05315595A JPH05315595A JP11495492A JP11495492A JPH05315595A JP H05315595 A JPH05315595 A JP H05315595A JP 11495492 A JP11495492 A JP 11495492A JP 11495492 A JP11495492 A JP 11495492A JP H05315595 A JPH05315595 A JP H05315595A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- layer
- gaas substrate
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、化合物半導体装置に関
し、より詳細にはショットキーゲート電界効果トランジ
スタ、ヘテロ接合バイポーラトランジスタ等に用いられ
る化合物半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a compound semiconductor device used for Schottky gate field effect transistors, heterojunction bipolar transistors and the like.
【0002】[0002]
【従来の技術】従来、一般に用いられるGaAs、Al
GaAs、InGaAsの半導体基板上に、p型電極と
して、基板に含まれるGa、Al、In原子と置換する
II族元素であるZn、Mg、Be層等が積層されてい
た。図3は、そのような化合物半導体装置の一例を示す
ものであり、p型GaAs基板1上に、II族元素である
Znを抵抗加熱、電子ビーム加熱、スパッタリング等の
方法で低圧蒸着し、Zn層2を形成している。そしてさ
らに同様の方法で、Zn層上にAu層3を積層して、化
合物半導体基板上にp型オーミックコンタクトを形成し
ている。2. Description of the Related Art Conventionally commonly used GaAs and Al
Substituting Ga, Al and In atoms contained in the substrate as a p-type electrode on a GaAs and InGaAs semiconductor substrate
A group II element Zn, Mg, Be layer and the like were laminated. FIG. 3 shows an example of such a compound semiconductor device. Zn, which is a group II element, is vapor-deposited on a p-type GaAs substrate 1 at low pressure by a method such as resistance heating, electron beam heating, or sputtering. Forming layer 2. Then, by the same method, the Au layer 3 is laminated on the Zn layer to form the p-type ohmic contact on the compound semiconductor substrate.
【0003】図4もまた、従来の化合物半導体装置の一
例を示すもので、n型GaAs基板4に、上記と同様の
方法でTi層5、Pt層6及びAu層7を積層して、化
合物半導体基板上にショットキーコンタクトを形成して
いる。FIG. 4 also shows an example of a conventional compound semiconductor device, in which a Ti layer 5, a Pt layer 6 and an Au layer 7 are laminated on an n-type GaAs substrate 4 in the same manner as described above to form a compound. A Schottky contact is formed on the semiconductor substrate.
【0004】[0004]
【発明が解決しようとする課題】このような、従来の化
合物半導体装置においては、その製造工程が高温下で行
われることが多く、これにより、化合物半導体基板と電
極のコンタクト部で、電極材料である金属の化合物半導
体基板への混入・浸透によりオーミックコンタクト性及
びショットキーコンタクト性を低下させるという問題が
あった。In such a conventional compound semiconductor device, the manufacturing process is often carried out at a high temperature, which makes it possible to use the electrode material at the contact portion between the compound semiconductor substrate and the electrode. There is a problem that the ohmic contact property and the Schottky contact property are deteriorated by mixing and permeating a certain metal into the compound semiconductor substrate.
【0005】特に、p型の金属原子は、高温での熱処理
により非常に早く化合物半導体基板中へ拡散するので、
化合物半導体基板が高温で処理される時にオーミックコ
ンタクト性及びショットキーコンタクト性を失うことが
多く、同じことがバイポーラトランジスタのような薄層
の化合物半導体装置にも生じるという問題があった。In particular, p-type metal atoms diffuse very quickly into the compound semiconductor substrate due to heat treatment at high temperature.
When the compound semiconductor substrate is processed at a high temperature, the ohmic contact property and the Schottky contact property are often lost, and the same problem occurs in a thin compound semiconductor device such as a bipolar transistor.
【0006】[0006]
【課題を解決するための手段】上記課題を解決するため
本発明によれば、化合物半導体基板上に少なくとも1層
の導電層からなる電極が形成された化合物半導体装置で
あって、前記化合物半導体基板上に順次炭素層及び導電
層が積層されて電極が形成されるか、あるいは前記化合
物半導体基板上に順次第1の導電層及び炭素層が形成さ
れ、さらに該炭素層上に第2の導電層が積層されて電極
が形成されている化合物半導体装置が提供される。In order to solve the above problems, according to the present invention, there is provided a compound semiconductor device having an electrode formed of at least one conductive layer on a compound semiconductor substrate. An electrode is formed by sequentially stacking a carbon layer and a conductive layer thereon, or a first conductive layer and a carbon layer are sequentially formed on the compound semiconductor substrate, and a second conductive layer is further formed on the carbon layer. There is provided a compound semiconductor device in which electrodes are formed by stacking.
【0007】本発明における化合物半導体基板とは主に
III −V族の化合物、具体的には、GaAs、AlGa
As、InGaAs等があげられる。また、化合物半導
体基板上に形成される電極は1層の導電層から構成され
ていてもよく、2層の導電層又はそれ以上の導電層が積
層されて構成されていてもよい。この際の電極を構成す
る導電層としては、通常の金属、例えば、W、Zn、A
u、AuGeNi、Al、Ti/Pt/Au、Al/T
i/Pt/Au及びTi/Pt等を使用することができ
る。これら電極は抵抗加熱、電子ビーム加熱、スパッタ
リング等の公知の方法で形成することができる。The compound semiconductor substrate in the present invention is mainly
III-V group compounds, specifically GaAs, AlGa
Examples include As and InGaAs. The electrode formed on the compound semiconductor substrate may be composed of one conductive layer, or may be composed of two conductive layers or more conductive layers stacked. In this case, the conductive layer forming the electrode is formed of a common metal such as W, Zn or A.
u, AuGeNi, Al, Ti / Pt / Au, Al / T
i / Pt / Au, Ti / Pt, etc. can be used. These electrodes can be formed by a known method such as resistance heating, electron beam heating, or sputtering.
【0008】本発明における化合物半導体基板上、ある
いは導電層上に形成される炭素層はスパッタ法、あるい
は電子線蒸着法等、公知の方法により形成され、その膜
厚は約10〜50nmが好ましい。The carbon layer formed on the compound semiconductor substrate or the conductive layer in the present invention is formed by a known method such as a sputtering method or an electron beam evaporation method, and its thickness is preferably about 10 to 50 nm.
【0009】[0009]
【作用】上記の構成によれば、化合物半導体基板上に少
なくとも1層の導電層からなる電極が形成された化合物
半導体装置であって、前記化合物半導体基板上に順次炭
素層及び導電層が積層されて電極が形成されるか、ある
いは前記化合物半導体基板上に順次第1の導電層及び炭
素層が形成され、さらに該炭素層上に第2の導電層が積
層されて電極が形成されているので、化合物半導体基板
と電極との間に設けられた炭素層は種々の電極材料であ
る金属原子の基板への拡散を防ぐ、熱的に安定なバリア
として作用する。つまり、化合物半導体基板への炭素の
拡散係数は、通常、不純物として基板内に注入されるII
族元素に比べ非常に低いため、電極材料である金属原子
の化合物半導体基板への拡散を防止し、拡散によるオー
ミックコンタクト性及びショットキーコンタクト性の低
下を防止する。また、特にp型の化合物半導体基板の結
晶内において、炭素が化合物半導体基板の構成原子と一
部置換し、アクセプタとして作用することとなり、化合
物半導体基板と電極とのコンタクト部の抵抗が低減する
こととなる。According to the above structure, a compound semiconductor device having an electrode formed of at least one conductive layer on a compound semiconductor substrate, wherein a carbon layer and a conductive layer are sequentially laminated on the compound semiconductor substrate. Or the first conductive layer and the carbon layer are sequentially formed on the compound semiconductor substrate, and the second conductive layer is further laminated on the carbon layer to form the electrode. The carbon layer provided between the compound semiconductor substrate and the electrode acts as a thermally stable barrier that prevents diffusion of metal atoms, which are various electrode materials, into the substrate. That is, the diffusion coefficient of carbon into a compound semiconductor substrate is usually
Since it is much lower than that of the group element, it prevents diffusion of metal atoms, which are electrode materials, into the compound semiconductor substrate, and prevents deterioration of ohmic contact property and Schottky contact property due to diffusion. In addition, carbon partially substitutes the constituent atoms of the compound semiconductor substrate and acts as an acceptor in the crystal of the p-type compound semiconductor substrate, thereby reducing the resistance of the contact portion between the compound semiconductor substrate and the electrode. Becomes
【0010】[0010]
【実施例】本発明の係る化合物半導体装置の実施例を図
1及び図2にもとづき説明する。図1はp型オーミック
特性を示すコンタクト部に炭素層12を用いた化合物半
導体装置の一実施例を示したものである。図1におい
て、11は化合物半導体基板であるp型GaAs基板で
あり、GaAs基板11上に炭素層12が形成され、さ
らに導電層であるW層13が積層されている。EXAMPLE An example of a compound semiconductor device according to the present invention will be described with reference to FIGS. FIG. 1 shows an example of a compound semiconductor device using a carbon layer 12 in a contact portion showing p-type ohmic characteristics. In FIG. 1, 11 is a p-type GaAs substrate which is a compound semiconductor substrate, a carbon layer 12 is formed on the GaAs substrate 11, and a W layer 13 which is a conductive layer is further laminated.
【0011】炭素層12は、スパッタ法により、膜厚約
30nmで形成し、さらに、炭素層12上に、スパッタ
法によりW層13を、膜厚約200nmで積層した。積
層後、GaAs基板11中のAs原子部位に炭素原子を
移動させるように600〜900℃程度の温度で10秒
間RTA(Rapid thermal Aneal)処理した。さらに、図
示していないが、このGaAs基板11の表面に金属配
線を形成することにより化合物半導体装置が完成する。The carbon layer 12 was formed with a film thickness of about 30 nm by the sputtering method, and the W layer 13 was further laminated on the carbon layer 12 with a film thickness of about 200 nm by the sputtering method. After stacking, RTA (Rapid Thermal Aneal) treatment was performed for 10 seconds at a temperature of about 600 to 900 ° C. so that carbon atoms were moved to As atom sites in the GaAs substrate 11. Further, although not shown, a compound semiconductor device is completed by forming metal wiring on the surface of the GaAs substrate 11.
【0012】このような構造の化合物半導体装置では、
炭素層12がGaAs基板11とW層13との間でバリ
ヤーとして働き、製造工程においてGaAs基板11が
高温にさらされても、W原子がGaAs基板11に拡散
するのを防止することができる。さらに図2は、ショッ
トキー特性を示すコンタクト部に炭素層16を用いた、
本発明の第2の実施例を示す化合物半導体装置を示して
いる。In the compound semiconductor device having such a structure,
The carbon layer 12 acts as a barrier between the GaAs substrate 11 and the W layer 13, and can prevent W atoms from diffusing into the GaAs substrate 11 even if the GaAs substrate 11 is exposed to high temperature in the manufacturing process. Further, in FIG. 2, the carbon layer 16 is used in the contact portion showing the Schottky characteristic,
2 shows a compound semiconductor device showing a second embodiment of the present invention.
【0013】図において、14は化合物半導体基板であ
るn型GaAs基板であり、GaAs基板14上に電極
であるTi層15、炭素層16及びAu層17が積層さ
れている。これらTi層15、炭素層16及びAu層1
7は実施例1と同様に低圧蒸着の一般的方法を用いて形
成した各層の厚さは、Ti層15は約10nm、炭素層
16は約30nm、Au層17は約200nmである。In the figure, 14 is an n-type GaAs substrate which is a compound semiconductor substrate, and a Ti layer 15, a carbon layer 16 and an Au layer 17 which are electrodes are laminated on the GaAs substrate 14. These Ti layer 15, carbon layer 16 and Au layer 1
7 has a thickness of about 10 nm for the Ti layer 15, about 30 nm for the carbon layer 16 and about 200 nm for the Au layer 17 formed by the general method of low pressure vapor deposition as in Example 1.
【0014】さらに、実施例1と同様に、このGaAs
基板14の表面に金属配線を形成することにより化合物
半導体装置が完成する。このような構造の半導体装置で
は、炭素層16の存在によりAu層17のAu原子がG
aAs基板14に拡散するのを防止することができる。Further, as in the first embodiment, this GaAs
The compound semiconductor device is completed by forming metal wiring on the surface of the substrate 14. In the semiconductor device having such a structure, the presence of the carbon layer 16 causes the Au atoms in the Au layer 17 to become G
It can be prevented from diffusing into the aAs substrate 14.
【0015】[0015]
【発明の効果】以上説明したように、本発明の化合物半
導体装置においては、化合物半導体基板上に少なくとも
1層の導電層からなる電極が形成された化合物半導体装
置であって、前記化合物半導体基板上に順次炭素層及び
導電層が積層されて電極が形成されるか、あるいは前記
化合物半導体基板上に順次第1の導電層及び炭素層が形
成され、さらに該炭素層上に第2の導電層が積層されて
電極が形成されているので、化合物半導体基板と電極と
の間に設けられた炭素層は種々の電極材料である金属原
子の基板への拡散を防ぐことができ、熱的に安定なバリ
アとして作用する。つまり、化合物半導体基板への炭素
の拡散係数は、通常、不純物として基板内に注入される
II族元素に比べ非常に低いため、電極材料である金属原
子の化合物半導体基板への拡散を防止するとともに、拡
散によるオーミックコンタクト性及びショットキーコン
タクト性の低下を防止することができる。また、特にp
型の化合物半導体基板の結晶内において、炭素が化合物
半導体基板の構成原子と一部置換し、アクセプタとして
作用することとなり、化合物半導体基板と電極とのコン
タクト部の抵抗を低減することができる。As described above, the compound semiconductor device of the present invention is a compound semiconductor device in which an electrode made of at least one conductive layer is formed on the compound semiconductor substrate, and the compound semiconductor device is provided on the compound semiconductor substrate. To form an electrode by sequentially stacking a carbon layer and a conductive layer, or sequentially forming a first conductive layer and a carbon layer on the compound semiconductor substrate, and further forming a second conductive layer on the carbon layer. Since the electrodes are formed by stacking, the carbon layer provided between the compound semiconductor substrate and the electrode can prevent diffusion of metal atoms, which are various electrode materials, into the substrate, and is thermally stable. Acts as a barrier. That is, the diffusion coefficient of carbon into the compound semiconductor substrate is usually injected into the substrate as an impurity.
Since it is much lower than Group II elements, it is possible to prevent the diffusion of metal atoms, which are the electrode material, into the compound semiconductor substrate, and to prevent the ohmic contact property and the Schottky contact property from being deteriorated due to the diffusion. Also, especially p
In the crystal of the type compound semiconductor substrate, carbon partially replaces the constituent atoms of the compound semiconductor substrate and acts as an acceptor, so that the resistance of the contact portion between the compound semiconductor substrate and the electrode can be reduced.
【0016】従って、化合物半導体装置における電気特
性の信頼性が高く、低抵抗性、熱安定性を実現するとが
でき、バイポーラトランジスタのような超薄型化合物半
導体装置のコンタクト部形成を可能とした。Therefore, the reliability of the electrical characteristics of the compound semiconductor device is high, low resistance and thermal stability can be realized, and the contact portion of an ultra-thin compound semiconductor device such as a bipolar transistor can be formed.
【図1】本発明の化合物半導体装置のオーミックコンタ
クト部の一実施例を示す要部の概略断面図である。FIG. 1 is a schematic sectional view of a main part showing an embodiment of an ohmic contact part of a compound semiconductor device of the present invention.
【図2】本発明の化合物半導体装置のショットキーコン
タクト部の一実施例を示す要部の概略断面図である。FIG. 2 is a schematic cross-sectional view of an essential part showing an embodiment of the Schottky contact part of the compound semiconductor device of the present invention.
【図3】従来の化合物半導体装置のオーミックコンタク
ト部の一実施例を示す要部の概略断面図である。FIG. 3 is a schematic cross-sectional view of a main part showing an embodiment of an ohmic contact part of a conventional compound semiconductor device.
【図4】従来の化合物半導体装置のショットキーコンタ
クト部の一実施例を示す要部の概略断面図である。FIG. 4 is a schematic cross-sectional view of a main part showing an embodiment of a Schottky contact part of a conventional compound semiconductor device.
11 p型GaAs基板(化合物半導体基板) 12、16 炭素層 13 W層(導電層) 14 n型GaAs基板(化合物半導体基板) 15 Ti層(第1の導電層) 17 Au層(第2の導電層) 11 p-type GaAs substrate (compound semiconductor substrate) 12, 16 carbon layer 13 W layer (conductive layer) 14 n-type GaAs substrate (compound semiconductor substrate) 15 Ti layer (first conductive layer) 17 Au layer (second conductivity) layer)
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/73 21/338 29/812 7376−4M H01L 29/80 M Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI Technical display location H01L 29/73 21/338 29/812 7376-4M H01L 29/80 M
Claims (1)
導電層からなる電極が形成された化合物半導体装置であ
って、前記化合物半導体基板上に順次炭素層及び導電層
が積層されて電極が形成されるか、あるいは前記化合物
半導体基板上に順次第1の導電層及び炭素層が形成さ
れ、さらに該炭素層上に第2の導電層が積層されて電極
が形成されていることを特徴とする化合物半導体装置。1. A compound semiconductor device having an electrode formed of at least one conductive layer on a compound semiconductor substrate, wherein a carbon layer and a conductive layer are sequentially laminated on the compound semiconductor substrate to form an electrode. Or a first conductive layer and a carbon layer are sequentially formed on the compound semiconductor substrate, and a second conductive layer is further laminated on the carbon layer to form an electrode. Semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11495492A JP3174135B2 (en) | 1992-05-07 | 1992-05-07 | Compound semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11495492A JP3174135B2 (en) | 1992-05-07 | 1992-05-07 | Compound semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05315595A true JPH05315595A (en) | 1993-11-26 |
JP3174135B2 JP3174135B2 (en) | 2001-06-11 |
Family
ID=14650761
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11495492A Expired - Fee Related JP3174135B2 (en) | 1992-05-07 | 1992-05-07 | Compound semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3174135B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005081296A1 (en) * | 2004-02-10 | 2005-09-01 | Infineon Technologies Ag | Method for depositing a conductive carbon material on a semiconductor for forming a schottky contact and semiconductor contact device |
US7768016B2 (en) | 2008-02-11 | 2010-08-03 | Qimonda Ag | Carbon diode array for resistivity changing memories |
US7894253B2 (en) | 2006-10-27 | 2011-02-22 | Qimonda Ag | Carbon filament memory and fabrication method |
US7915603B2 (en) | 2006-10-27 | 2011-03-29 | Qimonda Ag | Modifiable gate stack memory element |
WO2011040172A1 (en) * | 2009-10-01 | 2011-04-07 | トヨタ自動車株式会社 | Semiconductor device, and process for production of semiconductor device |
US8030637B2 (en) | 2006-08-25 | 2011-10-04 | Qimonda Ag | Memory element using reversible switching between SP2 and SP3 hybridized carbon |
EP4220687A1 (en) * | 2022-02-01 | 2023-08-02 | STMicroelectronics S.r.l. | Manufacturing process of an ohmic contact of a hemt device and hemt device |
-
1992
- 1992-05-07 JP JP11495492A patent/JP3174135B2/en not_active Expired - Fee Related
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005081296A1 (en) * | 2004-02-10 | 2005-09-01 | Infineon Technologies Ag | Method for depositing a conductive carbon material on a semiconductor for forming a schottky contact and semiconductor contact device |
US8030637B2 (en) | 2006-08-25 | 2011-10-04 | Qimonda Ag | Memory element using reversible switching between SP2 and SP3 hybridized carbon |
US7894253B2 (en) | 2006-10-27 | 2011-02-22 | Qimonda Ag | Carbon filament memory and fabrication method |
US7915603B2 (en) | 2006-10-27 | 2011-03-29 | Qimonda Ag | Modifiable gate stack memory element |
US7768016B2 (en) | 2008-02-11 | 2010-08-03 | Qimonda Ag | Carbon diode array for resistivity changing memories |
WO2011040172A1 (en) * | 2009-10-01 | 2011-04-07 | トヨタ自動車株式会社 | Semiconductor device, and process for production of semiconductor device |
JP2011077428A (en) * | 2009-10-01 | 2011-04-14 | Toyota Motor Corp | Semiconductor device and method of manufacturing semiconductor device |
US8633101B2 (en) | 2009-10-01 | 2014-01-21 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method of semiconductor device |
EP4220687A1 (en) * | 2022-02-01 | 2023-08-02 | STMicroelectronics S.r.l. | Manufacturing process of an ohmic contact of a hemt device and hemt device |
Also Published As
Publication number | Publication date |
---|---|
JP3174135B2 (en) | 2001-06-11 |
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