JPH05308120A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To form an integrated circuit and a filter circuit whose cutoff frequency is a desired value, on the same semiconductor chip. CONSTITUTION:A diffusion layer 111 and an MIS type capacitor are formed on the surface of a semiconductor substrate 101. The diffusion layer 111 has a belt type planar shape and used as a resistor. The MIS type capacitor has a belt type planar shape, and its width WC is equal to the width WR of the diffusion layer 111. The diffusion layer 111 and the MIS type capacitor are electrically connected to form a filter circuit. When the diffusion layer and the MIS type capacitor are formed, a P-type diffusion layer 121 is formed in a specified region of a semiconductor substrate, an oxide film 141 is formed on the semiconductor substrate surface, a plurality of belt type apertures having a constant width are formed by using belt type patterns 200A, 200B on the same mask 200, P-type impurities are introduced from a belt type aperture 122 positioned in the region except the P-type diffusion layer 121, a thin oxide film for dielectric is formed on the upper surface of the diffusion layer exposed from the belt type aperture, and an aluminum electrode is formed on the upper surface of the oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology and a technology particularly effective when applied to a semiconductor integrated circuit device having a filter circuit, for example, a semiconductor integrated circuit device having a filter circuit in the same chip. And a technique useful for the manufacturing method thereof.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, such as a bipolar linear IC, into which an analog signal is input, a filter circuit (for example, a low-pass filter) for the input signal usually has a capacitance C1 as shown in FIG. Resistance R1
(Or a coil) are connected and formed. actually,
When forming a filter circuit for an IC, a capacitor and a resistor, which are separate from the semiconductor chip and have a characteristic variation of not more than a predetermined value, are externally attached to a substrate of an electronic device on which the chip is mounted, and these are connected to each other. Was. A filter circuit having a constant characteristic (for example, a constant cutoff frequency) has been achieved by constructing a circuit using such capacitance and resistance with little variation.

In recent years, however, it has become possible to form the filter circuit on a semiconductor chip, thereby reducing costs by reducing the number of parts of electronic equipment, and further reducing the size of products.

[0004]

However, it has been clarified by the inventors of the present invention that there are the following problems in forming a filter circuit on a semiconductor chip. That is, when the filter circuit is formed in the same element manufacturing process as that of other integrated circuits on the semiconductor chip, variations in characteristics occur in the formed capacitance and resistance, which causes noise removal of the filter circuit. The accuracy (the accuracy of the cutoff frequency f) will decrease.

This is caused by a misalignment of mask patterns in a manufacturing process or a misalignment during etching.
This is because the error in resistance and the error in capacitance are different in magnitude. Therefore, even when the resistance and the capacitance are formed according to the same mask pattern (the shifts have the same magnitude), the resistance and the capacitance have different magnitudes of error. It is not possible to control the characteristic (cutoff frequency f) of the filter circuit formed by the combination of the resistance and the capacitance which have different errors to a desired value, and it is possible to form the filter circuit with high accuracy on the chip. There wasn't.

The present invention has been made in view of the above circumstances, and a semiconductor integrated circuit device capable of forming a filter circuit having a desired cutoff frequency on a semiconductor chip on which an integrated circuit is formed with a desired accuracy. And a method for manufacturing the same. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, a first aspect of the present invention comprises a resistor portion having a strip-shaped planar shape formed on a semiconductor substrate, and a capacitive portion having a strip-shaped planar shape having the same lateral width as the resistance of the strip-shaped resistor portion. It is intended to provide a semiconductor integrated circuit device in which a filter circuit is formed by conductively connecting to a capacitor section. Also, the second
In forming the resistor part and the capacitor part having a strip-shaped planar shape and the same lateral width, the invention of claim 1 forms an impurity diffusion region in a predetermined region of a semiconductor substrate and forms an insulating film on the surface of the semiconductor substrate. Then, two or more strip-shaped openings having a constant width are provided in the insulating film thus formed with one mask pattern, and impurities are introduced into the semiconductor substrate through the strip-shaped openings located above the region other than the impurity diffusion region. And forming the resistance portion, a thin insulating film is formed on the surface of the semiconductor substrate exposed from the band-shaped opening formed on the upper surface of the impurity diffusion region, and a conductive layer is formed on the upper surface to form the capacitance portion. A method for manufacturing a semiconductor integrated circuit device to be formed is provided.

[0008]

According to the above-mentioned means, the lateral width of the strip-shaped resistor forming the filter circuit and the lateral width of the strip-shaped capacitor are the same. The manufacturing error due to the time lag substantially affects the resistance value and the capacitance value at the same rate.
Therefore, in the filter circuit configured by the combination of the resistance and the capacitance, these errors can be canceled by the connection pattern.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit device according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a filter circuit 100 of a semiconductor integrated circuit device 10 according to the present invention.
It is a figure which shows the principal part cross section in which was formed.

As shown in FIG. 1, the filter circuit 100 of this embodiment has a resistance forming region 110 and a capacitance forming region 12.
It consists of 0 and. A band-shaped diffusion layer (see FIG. 3) 111 in which p-type impurities are ion-implanted into the n-type semiconductor substrate 101 is formed in the resistance formation region 110, and the diffusion layer 111 is used as a resistance. There is. Further, in the capacitance forming region 120, the semiconductor substrate (epitaxial layer) 10
1, a square p-type diffusion layer 121 (two-dot chain line in FIG. 3) and a plurality of silicon oxide (SiO ₂ ) thin films 122.
(122a to 122c) and the aluminum electrode (Al) 123 formed so as to cover the upper surface of the thin film 122 are stacked, so that the diffusion layer 121 forms the lower part of the capacitance of the MIS (metal-insulator-semiconductor) structure. The aluminum electrode 123 constitutes the upper electrode, and the silicon oxide thin film 122 constitutes the dielectric. Then, the diffusion layer 111 in the resistance formation region 110 and the diffusion layer 121 in the capacitance formation region 120 are conductively connected by a wiring layer (not shown), and the filter circuit 100 having the configuration shown in FIG.
Has been achieved.

By the way, in the thus formed filter circuit 100 of the present embodiment, the resistance value R1 is set to the diffusion layer 1
11 can be determined by the shape of the silicon oxide thin film 122 (122a ...
122c) can be determined (see equations (2) and (3) described later). Therefore, in this embodiment,
The diffusion layer 11 that forms a resistor will be described in detail below.
1 and the silicon oxide thin film 122 (122a to 1)
22c) is formed into a strip having the same width (see the mask pattern in FIG. 3), and the characteristic (cutoff frequency f) of the filter circuit formed by these resistors and capacitors is set to a desired value. ing.

Hereinafter, the manufacturing process of the semiconductor chip 10 including the filter circuit 100 having the above-described structure and the shape of each main portion will be described in detail with reference to FIGS.
FIG. 2 is a cross-sectional view showing a state of the semiconductor substrate 101 on which the filter circuit 100 of this embodiment is formed before the filter circuit is formed. As shown in this figure, a buried layer 131 is formed on the lower side of a semiconductor substrate 101 made of an n-type epitaxial layer, while isolation layers 132, 133, and 134 made of silicon oxide separate the element regions. Has been formed.

In forming the filter circuit 100, first, a p-type diffusion layer (forming a lower electrode of a capacitor) 121 is formed on the substrate surface between the separation layers 133 and 134.
A silicon oxide film 141 is formed on the main surface of the semiconductor substrate 101 thus formed (FIG. 2).

Next, the silicon oxide film 141 is etched in a predetermined pattern to form a strip-shaped opening 142 for forming the resistor R1 and strip-shaped openings 143a to 143c for forming the dielectric of the capacitor. To form. In performing this etching, the silicon oxide film 14 is
A resist is applied to the upper surface of No. 1 and exposed by the pattern of the mask 200 shown in FIG. 3, and then etching is performed using the resist as a mask.

When such etching of the silicon oxide film 141 is performed, the surface shape of the silicon oxide film 141 becomes substantially the same as that shown in FIG. More specifically, as shown in FIG. 3, the mask 200 has a width WR,
One strip-shaped pattern 200A with length LR and width W
Three strip-shaped patterns 200B having a length C and a length C are formed. Therefore, the planar shapes of the band-shaped openings 142, 143a to 143c (FIG. 4) formed in the silicon oxide film 141 are lateral width WR, length LR (142), and lateral width W, respectively.
C, length LC (143a to 143c). As shown in FIG. 3, the band-shaped pattern 200B for forming the band-shaped openings 143a to 143c has a rectangular diffusion layer 122 formed on the surface of the semiconductor substrate 101 (two points in the figure). The mask is aligned so that it is located inside (indicated by a chain line).

When the p-type impurity is ion-implanted by using the silicon oxide film 141 having the band-shaped opening formed therein and having the substantially same shape as that shown in FIG. 3 as a mask, the semiconductor substrate 101 is exposed through the opening 142. Impurities are introduced, and as shown in FIG. 4, a p-type impurity diffusion layer 11 having a width of WR is formed in this region.
1 is formed (the semiconductor substrate below the openings 143a to 143c is the p-type diffusion layer 121).

Then, in this way, the predetermined band-shaped opening 14 is formed.
Silicon oxide film 1 on which 2, 143a to 143c are formed
Thin insulating films (for example, silicon oxide thin films) 122a, 122b, 122c, 12 are formed in regions (band-shaped regions) exposed from the opening of the semiconductor substrate 101 covered with 41.
2d is formed, for example, by heat treatment (FIG. 5). Then, in the region where the silicon oxide thin films 122a to 122d are formed, 11 of the upper surface of the p-type diffusion layer 121 is formed.
Aluminum electrodes 123 are formed on the surfaces of 2a, 112b, and 112c, thereby forming MIS type (metal-insulator-semiconductor) capacitors. The final passivation film 144 is formed on the surface of the semiconductor chip 10 thus formed, and the semiconductor integrated circuit device having the structure shown in FIG. 1 is obtained.

By the way, the diffusion layer 111 forming the resistor R1 of this embodiment is formed according to the mask shown in FIG. 3, and has a strip shape having a substantially horizontal width WR and a length LR. On the other hand, the silicon oxide thin films 122b-12b forming the dielectric of the MIS type capacitor C1.
2d has a plurality of (three) strips each having a substantially horizontal width WC and a length LC. The value of WC is the width WR of the diffusion layer 111.
It has the same value as.

As described above, the band-shaped opening 142 that determines the shape of the diffusion layer 111 and the silicon oxide thin film 12 are formed.
Band-shaped openings 143a to determine the shapes of 2b to 122d
Since 143c is formed on the same mask pattern as shown in FIG. 3, the WR value and the WC value have a pattern error (especially an error in the horizontal direction in FIG. 3) caused by a mask deviation or an etching deviation. ΔW) affects both values evenly.

Next, as described above, the diffusion layer (resistor portion) 1
Width WR of 11 and silicon oxide thin films 122a to 122
When the width c of the c is equivalent to the width WC (corresponding to the width of the capacitor portion) (there is no error, the shape of the diffusion layer 111 and the shapes of the silicon oxide thin films 122a to 122c are the same as the pattern of FIG. 3). The effect on the characteristics of the filter circuit will be described in detail. That is, the cutoff frequency f of the filter circuit 100 shown in FIG. 1 is obtained by the following equation (1). f = 1 / (2.pi.C1.times.R1) (1) Further, the resistance value R1 and the capacitance value C1 made of the band-shaped diffusion layer are expressed by the following equations. R1 = ρS × LR / WR (2) C1 = Co × WC × LC × N (3) where ρS is the resistivity of the diffusion layer forming the resistance, and WR is the diffusion layer 111 forming the resistance. Width, LR of the diffusion layer 11
1 is the length, Co is the capacitance value per unit area of the strip-shaped capacitance, WC is the lateral width of the strip-shaped silicon oxide thin films 122a to 122c that determine the shape of the capacitance, and LC is the length of the thin film. N is the number of the above-mentioned strip-shaped silicon oxide thin films (three in this embodiment).

Therefore, the value of C1 × R1 in the calculation formula (1) for determining the value of the cutoff frequency f of the filter circuit section 100 composed of the resistance value R1 and the capacitance value C1 is the above (2),
From the equation (3), C1 × R1 = Co × WC × 3LC × ρS × LR / WR = Co × ρS × 3LC × LR × WC / WR (4) By the way, as shown in FIG. 3, the lateral widths WC and WR of the capacitors and the resistors are sufficiently smaller than their lengths LC and LR (LC, LR >> WC, WR). Therefore, in the actual manufacturing process, It can be seen that the influence of the error due to the shift of the mask and the shift at the time of etching is large with respect to WR and WC, and the other items are negligibly small compared to this.

Then, paying attention to the above equation (4), WC
= WR, the cutoff frequency f of the filter circuit
Is expressed by f = 1 / (2πC1 × R1) = 1 / (2π × Co × ρS × 3LC × LR) (5), and the value f of the cutoff frequency is an item with a large error (W
C, WR) will be offset and will be expressed as the product of only items with relatively small manufacturing errors.

Therefore, the filter circuit section 10 of this embodiment is
At 0, the diffusion layer 111 that forms the resistance has a strip shape, and the silicon oxide thin film 12 that determines the shape of the capacitance is formed.
2b-122d shape, the width WR of the above-mentioned strip resistance
And a plurality of strips having the same width WC as (WC = W
R).

In a semiconductor device manufacturing process, however, misalignment of mask patterns and misalignment of etching occur to form the shape of the diffusion layer 111 that forms a resistor and the oxidation that forms the dielectric of the MIS type capacitor. The shapes of the silicon thin films 122a to 122c do not match the mask pattern shown in FIG. 3 and an error occurs. Therefore, in consideration of errors due to mask pattern misalignment and etching misalignment, the actual lateral width of the diffusion layer 111 constituting the resistor is WR ′ = WR + ΔW, and the silicon oxide thin film 122a to determine the value of the MIS type capacitance. The width of 122c is WC '
= WC + ΔW (ΔW indicates an error in the horizontal direction in FIG. 3). The length LR of the resistance forming portion and the length LC of the capacitance forming portion
On the other hand, the vertical error (ΔL) is sufficiently small compared to these values and can be ignored in the filter circuit of the present embodiment.

When the error due to the misalignment of the mask patterns is taken into consideration in this way, the resistance value R1 and the capacitance value C1 are
They are expressed by the following equations (6) and (7), respectively. R1 = ρS × LR / (WR + ΔW) (6) C1 = Co × LC × (WC + ΔW) × N (7) where N is the number of strip-shaped silicon oxide thin films (N = in FIG. 1).
3), where LR / (WR + ΔW) represents the area of the diffusion layer 111, and LC × (WC + ΔW) × N represents the total area of the silicon oxide thin film (note that variations in ρS, Co, LR, and LC are mask patterns). Alignment error and error due to etching (Δ
W, ΔL) is small enough to be ignored).

Therefore, using the above equations (6) and (7),
C1 × R1 for determining the cutoff frequency f of the filter 100
When the value of is calculated, the following expression (8) is obtained. C1 × R1 = {ρS × LR / (WR + ΔW)} × Co × LC × (WC + ΔW) × N = Co × ρS × LR × LC × N × (WC + ΔW / WR + ΔW) (8) In this embodiment, As shown in FIG. 1, since WC = WR, all the items (W + ΔW) affected by the error are erased, and the cutoff frequency f due to the error ΔW (and ΔL) such as mask misalignment and etching misalignment. The effect on

In determining the shape of the capacitor, FIG. 6 shows that the shape of the lower electrode of the MIS capacitor is band-shaped and the width WC thereof is the same as the width of the diffusion layer forming the resistor. 6 is a cross-sectional view of a semiconductor device according to a first modified example, which is designed to obtain the same effect as that of the example, in the process of being manufactured, and shows substantially the same manufacturing process as that of FIG. 5 according to the above-described embodiment. is there.

As shown in FIG. 6, in the capacitance forming portion 320 of the filter circuit 300, three strip-shaped n-type diffusion layers 321a to 321c forming the lower electrode of the MIS type capacitance are formed, and on the upper surface thereof. A silicon oxide thin film (insulating film) 322 is formed. Then, this silicon oxide thin film 322
Aluminum is applied to the entire surface of the above to form an aluminum electrode 323 which is an upper electrode electrode.

In such a structure, the shape of the MIS-type capacitor is such that the p-type diffusion layers 321a to 321 forming the lower electrode.
Since it is determined by the shape of c, a band-shaped opening is formed in the silicon oxide film 341 by the same mask pattern as that shown in FIG. 3, and a p-type impurity is introduced into the semiconductor substrate using this as a mask. By doing so, the diffusion layer 311 having the horizontal width WR and the diffusion layers 321a to 321c (WR = WC) having the horizontal width WL as shown in FIG. 6 are obtained. By forming a final passivation film on the semiconductor chip thus formed, a semiconductor integrated circuit device having a desired filter circuit can be obtained. As a result, a filter circuit having a frequency characteristic equivalent to that of the above-described embodiment is achieved.

FIG. 7 is a sectional view showing a second modification in which the shape of the MIS type capacitor of the filter circuit formed on the semiconductor chip is determined by the shape of the aluminum electrode as the upper electrode. In this modification, a silicon oxide thin film 422 serving as a lower electrode and a dielectric is formed in a quadrangle in a predetermined region of a semiconductor substrate (corresponding to a shape shown by a broken line in FIG. 3), and an aluminum electrode 423 formed on the upper surface of the silicon oxide thin film 422 is formed. , Multiples with the same width (3
Book) strip-shaped electrode portions 423a, 423b, 423c. The design pattern (substantially the same as in FIG. 3) is determined so that the lateral width WC is the same as the lateral width WR of the diffusion layer 411 forming the resistance.

Further, FIG. 8 shows the capacitance of the filter circuit as MI.
FIG. 11 is a cross-sectional view of a semiconductor chip showing a third modification in which the diffusion layer is not connected to the S type, but the connection capacitance between the diffusion layers is used, and the shape of the diffusion layer, and thus the capacitance value C1 is determined. That is, in the third modification, the n-type semiconductor substrate 5 is
In the rectangular p-type diffusion layer 521 forming the lower electrode of No. 01, a plurality of strip-shaped n-type diffusion layers 522a to 522 are formed.
c is formed, and the n-type diffusion layers 522a to 522c form the upper electrode. At this time, the junction surface between the plurality of n-type diffusion layers 522a to 522c and the n-type diffusion layer 521 has a substantially capacitance shape.

Therefore, the diffusion layer 511 and the diffusion layers 522a ...
In forming 522c, band-shaped openings 542, 543a, 543b, 543c are formed in the silicon oxide film 541 with the same mask pattern as shown in FIG. 543c width WC
Is set to be the same as the lateral width WR of the strip-shaped opening 542 that forms the resistance, so that the n-type diffusion layers 522a to 522 can be formed.
The width (WC) of c becomes the same as the width (WR) of the diffusion layer 511, and a filter circuit having the same accuracy as that of the embodiment shown in FIG. 1 is achieved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. That is, the method for manufacturing the semiconductor integrated circuit device is not limited to the above-described one, and the strip resistance and the strip capacitance are based on strip shapes formed in the same mask pattern and having the same lateral width. If determined, it may be formed by any other manufacturing process. Although the resistor R1 is formed of the diffusion layer in the above embodiment, the resistor R1 is formed by stacking polysilicon or the like.
May be configured, and the resistor may be configured by another structure. Further, as the dielectric material forming the capacitor, an insulating film other than the silicon oxide film and the nitride film may be used. Further, although the aluminum electrode is used as the upper electrode in the present embodiment, other high conductive films such as a polysilicon film and a polycide film may be used instead.

Further, in the present embodiment, the band-shaped diffusion layer for forming the resistance and the silicon oxide thin film for determining the MIS capacitance are made to have the same longitudinal direction so as to suppress the influence of mask misalignment. Even if the orientation of is different,
A filter circuit with desired characteristics can be formed.

In the above description, an example in which the present invention was mainly applied to the formation of a filter circuit, which is the field of application of the invention made by the present inventor, was shown. However, the resistance value R1 and the capacitance value C1 are It can be applied to pattern design of all elements related to the characteristics.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. By forming the capacitor in a strip shape and making its lateral width the same as the lateral width of the strip resistor, it is possible to improve the accuracy of the cutoff frequency of the filter circuit formed by connecting these.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross section of a main part in which a filter circuit of a semiconductor integrated circuit device according to the present invention is formed.

FIG. 2 is a cross-sectional view showing a state of a semiconductor substrate on which a filter circuit of the present embodiment is formed, before the filter circuit is formed.

FIG. 3 is a plan view showing a mask pattern for forming a band-shaped opening in a silicon oxide film formed on the surface of a semiconductor substrate.

FIG. 4 is a cross-sectional view of a semiconductor chip showing a state in which a band-shaped opening is formed in the silicon oxide film in the pattern of FIG. 3 and ion implantation is performed using this as a mask.

FIG. 5 is a cross-sectional view of a semiconductor chip showing a state in which a silicon oxide thin film is formed into a band shape by oxidizing the surface of a semiconductor chip on which ion implantation has been performed.

FIG. 6 is a cross-sectional view showing a first modification in which the shape of the lower electrode of the MIS capacitor is a strip having the same width as the width of the diffusion layer forming the resistance.

FIG. 7 is a cross-sectional view showing a second modification in which the shape of the aluminum electrode as the upper electrode of the MIS-type capacitor is a strip having the same width as the width of the diffusion layer forming the resistor.

FIG. 8 is a cross-sectional view showing a third modified example in which the capacitance of the filter circuit is used as a connection capacitance between diffusion layers, and the shape of the diffusion layer is a strip having the same width as the width of a diffusion layer forming a resistor. It is a figure.

FIG. 9 is a circuit diagram showing an example of a low-pass filter.

[Explanation of symbols]

101 Semiconductor Substrate 111 Diffusion Layer (Diffusion Layer Used as Resistor) 121 Diffusion Layer (Diffusion Layer Used as Lower Electrode of Capacitor) 122 (122a to 122c) Silicon Oxide Thin Film (Dielectric) 123 Aluminum Electrode (Upper Capacitance) Electrode) 141 silicon oxide film 143a to 143c band-shaped opening 200 mask WR lateral width of diffusion layer used as resistance WC lateral width of silicon oxide thin film

Claims (3)

[Claims] 1. A resistive portion having a strip-shaped planar shape, and a capacitive portion having a strip-shaped planar shape and having a lateral width equal to the lateral width of the resistive portion are formed on a semiconductor substrate surface, and the resistive portion and the capacitive portion are formed. A semiconductor integrated circuit device, comprising a filter circuit which is electrically conductively connected to a section. 2. In forming the resistance portion and the capacitance portion according to claim 1, an impurity diffusion region is formed in a predetermined region of the semiconductor substrate, and an insulating film is formed on the surface of the semiconductor substrate.
The insulating film thus formed is provided with two or more strip-shaped openings having a constant width with one mask pattern, and impurities are introduced into the semiconductor substrate through the strip-shaped openings located above the region other than the impurity diffusion region. A thin insulating film is formed on the surface of the semiconductor substrate exposed from the band-shaped opening formed on the upper surface of the impurity diffusion region, and a conductive layer is formed on the upper surface to form the capacitance section. A method of manufacturing a semiconductor integrated circuit device, comprising: 3. In forming the resistance portion and the capacitance portion according to claim 1, an insulating film having two or more strip-shaped openings with a constant width is formed on a surface of a semiconductor substrate with one mask pattern. An impurity is introduced into the semiconductor substrate through the two or more strip-shaped openings using the insulating film as a mask to form two or more diffusion layers, and at least one of the diffusion layers thus formed forms the resistance portion. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising forming a thin insulating film on a surface of another diffusion layer, and forming a conductive layer on the upper surface of the diffusion film to form the capacitor section. ..