JPH05301380A - Image processor and image processing method - Google Patents

Abstract

PURPOSE:To specify adding position of information by marks so as to easily extract it. CONSTITUTION:A color signal of full color from a CCD line sensor 2101 is processed at an image processing circuit 2102 and binarized by a dummy intermediate tone processing at a binarizing circuit 2103. A density determining circuit 2106 determines density of an image signal and controls operation of a modulating circuit 2105 which adds adding information. The modulating circuit 2105 refers to contents of a ROM 2104. Based on its information, a dot position of the binarized image signal is changed and the adding information is added to the image. An FIFO 2111 compensates delay of the image occurred at the density determining circuit 2106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method applicable to an image forming apparatus for performing full color printing such as a full color printer, a full color copying machine and a full color facsimile machine.

[0002]

2. Description of the Related Art Conventionally, full-color printers, full-color copying machines, full-color facsimile machines, etc. have been put to practical use as output devices for performing color printing. As such a color image forming apparatus becomes cheaper and the quality of an output image is improved, there has been a problem that an original that should not be copied is copied.
For this reason, in recent years, the applicant has proposed a method in which, for example, a device serial number is added to an output image at the time of copying, and then the device serial number is confirmed from the output image as needed to identify the device. Has been done.

[0003]

However, in the above-mentioned conventional example, since an extra signal is added to the output image, the added signal acts as noise on the original image, and the image quality of the output image deteriorates. There was a problem to do. Such a problem is particularly prominent in an apparatus in which image formation is performed by binary processing, that is, pseudo-halftone processing such as a dither method or an error diffusion method. In this case, there is a drawback that image deterioration is easily noticeable. there were.

That is, in the conventional device, when adding the extra information, the density cannot be adjusted so as not to be conspicuous, so that the additional information appears as noise in the image and the quality of the output image is improved. It is a cause of loss.
This is not preferable because the additional information is visible to the user of the apparatus. The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to provide an image processing apparatus and a method thereof in which an additional position of additional information is specified and extraction thereof can be easily performed. There is a point.

[0005]

[Means for Solving the Problems]
In order to achieve the object, an image processing apparatus according to the present invention includes a generation unit that generates a plurality of dot data, a detection unit that detects a dot interval formed according to the dot data generated by the generation unit, and a dot interval. And a dot spacing controlled by the control unit represents predetermined information not included in the dot image formed according to the dot data generated by the generation unit.

The image processing method according to the present invention further includes a generating step of generating a plurality of dot data, a detecting step of detecting a dot interval formed according to the dot data generated by the generating step, and a dot interval. And a control step of controlling, and the dot spacing controlled by the control step represents predetermined information not included in the dot image formed according to the dot data generated by the generation step.

[0007]

According to the image processing apparatus and the method therefor of the present invention, a plurality of dot data are generated, the dot intervals formed according to the generated dot data are detected, the dot intervals are controlled, and the controlled dots are controlled. Since the interval expresses predetermined information that is not included in the dot image formed according to the generated dot data, deterioration of image quality is prevented when the predetermined information is added to the dot image.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. <First Embodiment> In a first embodiment of the present invention, an inkjet output type full-color copying apparatus will be described as an example.

FIG. 1 is a block diagram showing the arrangement of an image processing unit in the full-color copying apparatus of the first embodiment. In the figure, 101 is a CCD line sensor, and 102 is A.
/ D converter, 103 is a shading correction circuit, 1
Reference numeral 04 is a density conversion circuit, 105 is a masking / UCR circuit, 106 is a γ (gamma) correction circuit, 107 is a binarization circuit, and 108 is an ink head drive circuit (hereinafter referred to as “drive circuit”).
, 109-1 to 109-4 are ink heads that eject ink, 110 is a density determination circuit that determines the density of yellow, 111 is an additional pattern generation circuit, 112 is a CPU that controls the entire apparatus, and 113 is a CPU 112. , A ROM storing programs for operating, a RAM having a work area for various programs and a storage area for various parameters, 115 an AND gate, 116
Indicate OR gates, respectively.

The operation of the above structure will be briefly described. FIG. 4 is a flow chart for explaining the operation according to the first embodiment. In the following description, the entire control is performed by the CPU 1.
12 takes charge of each circuit, but each operation is performed by each circuit. The reflected light obtained by irradiating the original is converted into an electric signal which is color-separated into red, green and blue (R, G, B) by the CCD line sensor 101 (step S1). By relatively moving the line sensor 101 and the document in a direction orthogonal to the scanning direction of the line sensor, an image signal can be obtained over the entire surface of the document. The image signal is converted from an analog amount to a digital amount in the A / D converter 102 (step S2), and the shading correction circuit 10
At 3, the light amount unevenness and the sensitivity unevenness in the scanning direction of the CCD line sensor 101 are corrected (step S3).

Thereafter, the density conversion circuit 104 converts the signal representing the intensity of light into a signal representing the magnitude of the density (step S4), and the masking / UCR circuit 105 prints cyan (C) which is the color of the ink.・ Converted to magenta (M), yellow (Y), and black (K) image signals,
Color correction and undercolor removal are performed (step S5). Subsequently, the .gamma. Correction circuit 106 corrects the non-linearity of the output characteristic, and the binarization circuit 107 converts it into binary data by pseudo halftone processing (step S6). The binarization circuit 107 performs binarization processing based on a known error diffusion method (step S7). The binarized image signal is the driving circuit 1
The ink heads 109-1 to 109-4 are driven by 08, and the respective inks of C, M, Y, and K are ejected onto the recording paper to form a color output image. Here, as the ink heads 109-1 to 109-4, so-called bubble jet type ink heads that eject ink by utilizing film boiling due to thermal energy are used.

For a yellow (Y) image signal, 2
The multi-valued data before being digitized is input to the density determination circuit 110, and it is determined whether it is within a predetermined density range (step S8). As a result, if it is determined that the ink is within the predetermined range, the identification signal unique to the device is added to the Y signal by the determination signal (step S9), and the ink of the drive circuit 108 is based on the corrected image data. Head 1
Image formation is performed by driving 09-1 to 109-4 (step S10).

If it is determined that the Y signal is not within the predetermined range (step S9), the identification information unique to the apparatus is not added to the Y signal, and the drive circuit 108 causes the ink head 109-
1 to 109-4 are driven to form an image (step S10). Here, the additional pattern generation circuit 1
Reference numeral 11 stores in advance identification information unique to the apparatus (additional information such as model name and serial number). The additional pattern generation circuit 111 encodes this identification information and sequentially outputs it to generate the additional pattern.

FIG. 2 is a density determination circuit 1 according to the first embodiment.
It is a block diagram which shows the structure of 10. In the figure, 2
01-1, 201-2 are first in first out
out) memory (hereinafter referred to as "FIFO"), 202-1 to
202-6 is a D flip flop, 203 is an averaging circuit, 2
Reference numerals 04-1 and 204-2 denote registers, and 205 denotes a window comparator.

The operation of the above configuration will be briefly described.
The input yellow (Y) image signal is transferred to the FIFO 20.
After being delayed by 2 lines at 1-1, 1201-2, data for 3 lines can be processed simultaneously. The data for these three lines are delayed by one clock by the D flip flop 202, and an image signal of 3 × 3 pixels is obtained. Noise in the image signal is reduced by averaging this signal by the averaging circuit 203. Then, the window comparator 205 causes the registers 204-1 and 204-
It is determined whether or not the image data is between the upper limit value and the lower limit value that are respectively set to 2, and the determination result is output.

Here, when the window comparator 205 obtains a determination result that it falls within the upper limit value and the lower limit value, the signal of the additional pattern generation circuit 111 is added as a yellow (Y) image signal. In order to do so, a true (“1”) determination result is output to the AND gate 115, or if a determination result indicating that it is not contained is obtained, the AND gate 115 does not add the above signal, A false (“0”) determination result is output.

FIG. 3 is a block diagram showing the structure of the additional pattern generation circuit 111 according to the first embodiment. In the figure, 301 is a main scanning counter, 302 is a sub-scanning counter, 303 is a lookup table containing unique information (hereinafter referred to as "unique information LUT"), 304 is a dot pattern lookup for converting unique information into a dot pattern. Tables (hereinafter referred to as "dot pattern LUTs") are shown.

The operation of the above configuration will be briefly described.
The main scanning counter 301 and the sub-scanning counter 302 perform counting operations according to the clock signals in the main scanning direction and the sub-scanning direction of the image signal, respectively, and refer to the unique information lookup table 303 corresponding to the position on the image. The serial number of this device is stored in the unique information lookup table, and the serial number is repeatedly output according to the value of the counter. The dot pattern lookup table 304 is referred to based on this serial number, and an image signal in which the model information is represented by a dot pattern is generated. When the density determination circuit 110 obtains a true determination result, the output of the generated image signal is added to a normal image signal to form an image.

As described above, when the output image in which the identification information is added to the yellow (Y) image signal by using the predetermined dot pattern is read later by the reading means such as a reader or a scanner, Only the yellow component is separated. The added information can be extracted from the separated yellow component. In the present embodiment, the addition operation is performed only when the density determination circuit 110 determines that the image signal to which the dot pattern is added falls within a certain fixed value. Therefore,
For example, since it is not necessary to add a pattern to a portion where an added image is conspicuous such as an image area having a very low density, deterioration of the image can be avoided.

As described above, according to the first embodiment, the image density is determined and the pattern representing the model-specific information is added to the image only when the image density is within the predetermined density range. There is an effect that a pattern can be added while suppressing the influence on the image quality. It should be noted that in the above-described embodiment, an example in which the identification information is added to the yellow (Y) image signal has been described, but the present invention is not limited to this, and may be applied to images of other colors. It goes without saying that the density information may be determined and the identification information may be added, or the identification information may be added to a plurality of colors.

In the above-described embodiment, the density information is determined by using the image signal before binarization.
Depending on the case, it is possible to determine the density based on the signal after being binarized. That is, the average image density can be obtained by counting the number of dots in the unit area. <Second Embodiment> In the first embodiment described above, whether or not information is added is controlled according to the image density. However, not only switching whether or not to add information but also dots to be added. It can also be configured to select a pattern. If a plurality of window comparator parts and a plurality of register parts of the density determination circuit are prepared, the density determination can be performed over a plurality of levels. A plurality of types of dot patterns to be added are prepared with different numbers of dots included in a unit area, and a dot pattern close to the image density is selected and added by selecting an appropriate pattern according to the density level. It is possible. This makes it possible to make the additional pattern less noticeable.

<Third Embodiment> FIG. 5 is a block diagram showing the arrangement of an image processing unit in a full-color copying apparatus according to the third embodiment. In the figure, since the same circuits as those in FIG. 1 have the same configuration, the description thereof is omitted, and the numbers are shown in the 510 series.
With respect to the configuration different from that of FIG. 1, 501 is an additional pattern generation circuit, 502 is an addition circuit, 503 is a drive circuit, and 504-
Reference numerals 1 to 504-4 are laser diodes, 505 is a CPU for controlling the entire apparatus, 506 is a ROM storing programs for operating the CPU 505, and 507 is a RAM having work areas for various programs and storage areas for various parameters. Shown respectively.

The operation of the above configuration will be described. FIG. 7 is a flow chart for explaining the operation according to the third embodiment. In the following description, the CPU 505 takes charge of the overall control, but each operation is performed by each circuit. The operations of the CCD line sensor 511 to the γ correction circuit 516 are the same as the description of the flowchart shown in FIG. 4, and thus the description thereof will be omitted, and the operation of the γ correction circuit 516 and the following will be mainly described.

When generating one of the additional patterns having 256 levels of gradation, the additional pattern generation circuit 501 selects one level of gradation in accordance with the γ-corrected yellow (Y) image signal. The additional pattern generated by the additional pattern generation circuit 501 is added by the addition circuit 50.
In step 2, it is added to the yellow (Y) image signal that has been gamma-corrected by the gamma correction circuit 516 (step S21). The addition circuit 502 determines whether the addition result overflows at the same time as the addition process (step S22). The adder circuit 5
When 02 has overflowed, the clipping operation is performed at the maximum density (step S23). The image signals of yellow (Y) and other colors to which the additional patterns are added by the adding circuit 502 are converted by the driving circuit 503 into signals for driving the laser diodes 504-1 to 504-4. By this drive signal, the laser diode 504-
1 to 504-4 are driven, a latent image of C, M, Y, and K is formed on a photosensitive drum (not shown) by the laser light, and the latent image is developed with toner to form a full-color image. (Step S24).

FIG. 6 is a block diagram showing the structure of an additional pattern generating circuit according to the third embodiment. In the figure,
601 is a main scanning counter, 602 is a sub scanning counter, 6
Reference numeral 03 denotes a unique information LUT containing unique information. Main scanning counter 601, sub-scanning counter 602
Performs a counting operation according to the clock signals in the main scanning direction and the sub scanning direction of the image signal, respectively, and refers to the unique information LUT 603 corresponding to the position on the image. Unique information LUT
The serial number of this device is stored in 603, and the serial number is repeatedly output according to the counter value. Further, the unique information LUT 603 is inputted with a yellow (Y) image signal, that is, a density signal, and acts so that another address bank is selected so that an additional pattern to be generated differs depending on the size thereof. The input density signal does not normally require all 8 bits, and is configured to select 16 banks by using the most significant 4 bits. Of course, if necessary, the number of banks can be set to a size other than this, and a conversion circuit for selecting a bank from the densities can be added for more flexible density level division. .. Unique information L
In the UT 603, the additional pattern is stored with a large value in the bank for the high density portion and the small value in the bank for the low density portion, in which the additional pattern is not conspicuous. In this configuration, the density determination is also performed by the unique information LUT 603.

As described above, when outputting by the electrophotographic method, the density (gradation) of one pixel can be changed unlike the ink jet method. Therefore, by changing the density of the pattern to be added depending on the image density, it is possible to add the pattern at an optimum density level that is detectable even though the image of any density is invisible to the naked eye.

Now, in the first embodiment, the density determination circuit 1
No. 10 decides the pattern addition for the density falling between the preset upper limit value and the lower limit value, but the present invention is not limited to this, and a plurality of types of additional patterns that can be generated by the additional pattern generation circuit are prepared. However, the determination result of the density determination circuit 110 may be represented by multiple values and the additional pattern may be selected according to the multiple values. In this case, a selector may be prepared instead of the AND gate and the multi-valued signal may be treated as a selection signal.

Now, in FIG. 1, a plurality of patterns of the additional pattern generation circuit 111 are prepared, and the density determination circuit 110 is provided.
It is also possible to represent the judgment result of (1) by multi-value and select the pattern by the selector instead of the AND gate according to the multi-value. In this case, the pattern may be selected according to the density position between the upper limit value and the lower limit value. Further, the upper limit value and the lower limit value may be manually set, for example, in the service mode.

As described above, according to the first to third embodiments, the pattern representing the model-specific information is determined only when the image density is judged and is within the predetermined density range. By adding to the image, it is possible to add the pattern while suppressing the influence on the image quality. <Fourth Embodiment> FIG. 8 is a block diagram showing the arrangement of an image processing section of a full-color copying apparatus according to the fourth embodiment of the present invention. In the figure, 2101 is a CCD line sensor, 2102 is an image processing circuit, 2103 is a binarization circuit,
2104 is a ROM, 2105 is a modulation circuit, 2106 is a density determination circuit, 2107 is an ink head drive circuit, 21
Reference numeral 08 is an ink head, 2109 is a timing signal generation circuit, 2110 is a power supply circuit, and 2111 is a FIFO.
Is.

The operation of the above configuration will be briefly described.
The CCD line sensor 2101 captures color-separated light reflected or transmitted from the document while converting it relative to the document in a direction perpendicular to the reading direction, and converts it into an electric signal. The full-color signal thus obtained is subjected to signal processing in the image processing circuit 2102 and then binarized by pseudo halftone processing in the binarization circuit 2103. Also, the density determination circuit 2106
Controls the operation of the modulation circuit 2105 which determines the density of the image signal and adds additional information. The modulation circuit 2105 refers to the contents of the ROM 2104, and based on the information,
The dot position of the binarized image signal is changed, and additional information is added to the image.

The FIFO 2111 is a density determination circuit 210.
It is provided to compensate for the image delay at 6.
The binary signal to which the information is added by the modulation circuit 2105 is driven by the ink head drive circuit 2107 to drive the ink head 2108 for each output color to eject ink onto the recording paper (not shown), thereby forming a full-color image. Form. Further, the timing signal generation circuit 2109 generates a basic image clock and various clock signals and timing signals accompanying the basic image clock, and supplies them to each unit. The power supply circuit 2
Reference numeral 110 supplies electric power required for the operation of each unit of the image processing unit.

FIG. 9 is a block diagram showing the internal structure of the image processing circuit 2102 of FIG. In the figure, 220
1 is an A / D converter, 2202 is a shading correction circuit, 2203 is a density conversion circuit, 2204 is a masking / UCR circuit, 2205 is a filter circuit, and 2206 is γ.
It is a correction circuit. The red / green / blue (R, G, B) color-separated image signals input from the CCD line sensor 2101 are
After being converted into a digital signal by the A / D converter 2201 and corrected by the shading correction circuit 2202 for the light amount distribution and the sensitivity unevenness of the CCD line sensor 2101, the density conversion circuit 2203 converts the bright and dark signals RGB to cyan, magenta, yellow ( C, M, Y) density signals.

The masking / UCR circuit 2204 is a CM.
A black signal (K) is generated from the Y signal, and masking calculation for color correction and under color removal (UCR) are executed. The CMYK signal thus obtained is subjected to edge enhancement or smoothing processing by the filter circuit 2205 to correct the nonlinearity of the output from the γ correction circuit 2206.

The signal processed as described above and the signal obtained as a result are RGB or C as shown in FIG.
The signals of each color of MYK are continuous, and RGB signals
In the case of a signal, a color separation signal of one pixel is formed in each of 4 clocks including a non-image signal section (X in the figure) and is switched in synchronization with the color select signal CSEL1,0.
The basic cycle of these signals is defined by the image clock Vck, and the repetition cycle of each line is the cycle signal Hs.
It is specified by ync. In addition, in a line in which a mark line indicating an additional information addition position is inserted into the image signal,
Coding is performed on the line where the k signal modulates the image signal.
A signal is provided to identify each applicable line.

Further, the timing signal generation circuit 2109
Also generates and supplies a Reset signal and an Up / Down signal necessary for generating the additional information. Coding, Mark, Res generated in the sub-scanning direction
The signals of et, Up / Down are repeatedly generated at a constant cycle during image output, and accordingly, information is repeatedly added to the image signal.

By not resetting the initial value of the timing signal generating circuit 2109 to the same value for each copying operation, the position where information is added in the image is not fixed. In this way, the timing signal generation circuit 210
9 supplies a series of timing signals, and the entire apparatus operates in synchronization with the image signal. Here, the details of the timing signal generation circuit 2109 will be described.

FIG. 21 shows a timing signal generation circuit 210.
It is a block diagram which shows the structure of 9. In the figure, 14
01-1, 1401-2 are counters, 1402-
Reference numeral 1,1402-2 is a lookup table. The counter 1401-1 is for generating a timing signal in the main scanning direction, counts Vck after being reset by Hsync, and refers to the lookup table 1402-1 by its output.

The lookup table 1402-1 is R
OM or RAM, and CSEL0, CSEL1, and Hsync that should be internally generated in order from the beginning of the line
Pattern is written, and the timing signals are sequentially generated according to the reference from the counter. On the other hand, the counter 1401-2 and the lookup table 1402
-2 generates a timing signal in the sub-scanning direction, and counts Hsync to perform the same operation in the sub-scanning direction. At this time, unlike the main scanning direction, the counter 14 is provided for each copying operation.
By not resetting 01-2 to a constant value, the operation is performed so that the information addition position in the sub-scanning direction does not become a constant position for each output.

It should be noted that the counter 1401-for each copy operation
It is also possible to reset the initial value of 2 and operate so that the information addition position is not constant. In this way, information is repeatedly added and the positions to be added are dispersed for each copy operation, so that even if there is a malfunction of a specific ink head or an area where image density is unsuitable for information addition. The possibility that the additional information can be restored by any of the output images can be increased. In particular, it is effective to make the number of nozzles of the ink head and the repetition period relatively prime.

FIG. 11 is a diagram showing the internal structure of the modulation circuit 2105. In the figure, reference numeral 2401 denotes a dot position correction circuit, 2402 denotes a mark addition circuit, 2404-1 and 2404-1.
Reference numeral 404-2 is a selector, and reference numerals 2403-1 and 2403-2 are AND gates. The input image signal is supplied to the dot position correction circuit 2401 and the mark addition circuit 2402, and the selector 2404-1 determines the image signal itself or the dot position correction circuit 2401 according to the logical product of the density determination signal and the Coding signal. One of the image signals whose dot positions have been corrected by is selected.

On the other hand, the selector 2402-2 selects the output of the selector 2404-1 and the output of the mark adding circuit 2402 according to the logical product of the density determination signal and the Mark signal. Therefore, if the density determination signal is logical "0", that is, if the density is not appropriate, the selectors 2404-1 and 2404
The A side of -2 is selected, and the image signal is output as it is without correction.

FIG. 12 is a block diagram showing the configuration of the dot position correction circuit 2401. In the figure, 2501
-1 to 2501-12 are D flip flops, 2502 is a selector, 2503 is an exclusive OR (XOR) gate,
2504-1 and 2504-2 are inverters and 2501-
1-2505-3 are AND gates. The image clock Vck is applied to the D flip-flops 2501-1 to 2501-12 as a clock. Also, selector 2
In 502, the image signal itself and the D flip flop 2
What is delayed by 501-1 to 2501-4 is input.

As described above, in the image processing unit according to the present embodiment, the image signal represents the information of one pixel in the unit of four clock cycles of RGBX or CMYK, and therefore is input to the selector 2502. If the image signal on the delayed side is C, for example, it is a signal of the same color as C and has a delay amount of one pixel. Therefore, the selector 2502 selects the normal image signal side without delay (A side) or the side with delay (B side).
The print position of the output dot changes by one dot depending on whether the (side) image signal is selected.

When the Coding signal is not added, the output of the AND gate 2505-2 becomes logic 0,
Dot position correction is not performed. When the Coding signal is given, whether or not the dot position is corrected is determined by XOR.
It is determined by the logical product of the output of the gate 2503 and the image signal input (AND2505-2). Then, 1/0 of the bits of the additional information read from the ROM 2104 (1 at odd intervals, 0 at even intervals) and the D flip-flop 250.
If the output of 1-8 does not match the inversion by the inverter 2504-3, the dot position correction operation is executed. In addition, D flip flops 2501-5 to 2501
The inverter 8 and the inverter 2504-1 constitute a 1-bit counter and perform a counting operation in units of 4 clocks. That is, the count state is output from the D flip flop 2501-8 in synchronization with the color of the input image signal.

Now, considering one color, when the output of the selector 2502 becomes the logic "1", the output of the AND gate 2505-1 becomes the logic "0" and the reset is applied, and the time point is used as a reference. Vck / 4 that passed after
A representation of whether (which corresponds to the number of pixels) is an odd number or an even number is held as the contents of the counter. This information and the additional information from the ROM 2104 are compared by the XOR gate 2503, and if they do not match, the dot position correction operation is performed.

With the above configuration, the odd / even number of dot intervals in the output image signal is controlled according to 1/0 of the additional information from the ROM 2104. In addition,
The additional information output from the ROM 2104 changes on a line-by-line basis, and as a result, the dot intervals when modulation is performed are standardized to either odd intervals or even intervals in one line. It will be. As an example, FIG. 13 shows a process in the case of generating lines at odd intervals in a table format.

FIG. 14 is a block diagram showing the internal structure of the mark adding circuit 2402. In the figure, 2601
Is a counter, 2602-1 to 2602-4 are D flip flops, 2603-1 and 2603-2 are AND gates,
2604 is an OR gate. D flip-flop 26
The image clock Vck is given to 02-1 to 2602-4 as a clock.

In the above structure, when the Mark signal is not given, the output of the AND gate 2603-1 is always logic "0", so that a mark is added to the image signal.
That is, no changes are made. Further, when the Mark signal is given, the image signal is changed (corrected) as follows. That is, the counter 2601
It is a quaternary counter that counts the number of dots for each color of the image signal according to the color select signal, sends a carry for the corresponding color to the output, and generates a carry each time four dots are printed for each color. This carry signal and an image signal delayed by four clocks, that is, one pixel, are ANDed by an AND gate 2603-2 and added to the original image signal by an OR gate 2604. As a result, two dots are connected and output for every four dots for each color.

FIG. 15 is a diagram showing how the image signal for one color changes when the modulation is performed by the modulation circuit 2105. In the figure, the black circles eject ink onto the recording paper. It corresponds to a pixel for printing. FIG. 15A shows a case where the dot position is corrected, and the dot interval after the correction is either even dots or odd dots for each line.
In the figure, the second and third dots in the first line are laterally shifted by one dot, and the output data of the ROM 2104 matches even and odd dot intervals.

Further, FIG. 15B shows an image signal in the case where a mark is added, and the mark signal is given to the line which has become a mark line. Every four dots, two dots are consecutive. Appears. By modulating the image signal in this way, a serial number and a mark are added to the image. As is well known, the binary signal binarized by the error diffusion method has dots that are appropriately dispersed, especially in a region where the image density is low in the highlight portion, and appear as two dots in series. Things are extremely rare. Therefore, in a line in which two dots are arranged for every fixed number of dots, it is possible to easily find that the dots arranged in a line are arranged by enlarging the output image.

FIG. 15 is a block diagram showing the structure of the density determination circuit 2106. In the figure, 2801-1,
2801-2 is a FIFO, 2802-1 to 2802-6
Is a D flip-flop and 2803 is a NOR gate. When the signal binarized by the binarization circuit 2103 is input to the density determination circuit 2106, the FIFO 28
The lines 01-1 and 2801-2 are delayed one line at a time, and the density determination circuit 2106 can simultaneously process data for three lines.

That is, here, the signal from the binarization circuit 2103 is delayed by one clock by the D flip-flop 2802 to obtain an image signal of 3 × 3 pixels. And
By inputting this signal to the NOR gate 2803, it is possible to determine whether or not another dot exists in the 3 × 3 pixel area around the target pixel. If another dot exists in this area, the output of the NOR gate 2803 becomes logic "0", the modulation operation in the modulation circuit 2105 is not performed, and the image is output as it is. As a result, the high density portion is not modulated, and deterioration of the image quality due to the modulation can be prevented.

FIG. 17 shows R of the image processing unit according to this embodiment.
It is a figure which shows the reference method of OM2104. In the figure, a counter 2901 is an up / down counter and counts up or down Hsync according to the Up / Down signal. Then, by applying the output to the address input (adrs) of the ROM 2902, the additional information is set to 1 for each line of the image signal.
The operation of outputting from the ROM 2104 bit by bit is performed,
The modulation circuit operates based on this additional information.

In this image processing section, when the Reset signal and the Up / Down signal are given at the timings shown in FIG. 10, the Hsync signal is sequentially counted up from the time when it is first reset by the Reset signal, After inputting the Mark signal, Up / Down
Since the signal is switched to the down count, the count down is performed next. Therefore, the address output from the counter 2901 starts from 0, increases by 1 for each line, and decreases toward 0 again after the Mark signal. Then, when the address returns to 0, Codin
The g signal becomes 0, and the operation of adding additional information to the image ends.

As a result of the above operation, the addresses that refer to the ROM 2104 on the lines before and after the line to which the Mark signal is applied are symmetrical, so that the additional information is symmetrical before and after the mark line, as shown in FIG. Exists. Therefore, as long as the mark line is found, it is guaranteed that the same information can be obtained no matter which direction the additional information is read based on the mark line. Moreover, since the timing signal is repeatedly generated, the same additional information is repeatedly added to the same image.

The information stored in the ROM 2104 includes information for checking as well as unique information such as the serial number of the model of the device. The check information here is a code used to guarantee the reliability of the restored information when the additional information is restored from the output image later, and is a general checksum or C.
An error detection / correction code such as an RC code, which is calculated in advance from the unique information and stored in the ROM.

Further, when reading the additional information from the output image, the dot interval is determined with respect to the area where the code is estimated to exist on the basis of the mark line, and the restoration of the information is tried. At this time, by checking the consistency with the check information, it is confirmed that the original additional information is finally detected. As described above, according to the present embodiment, with respect to the image area determined to be suitable for the information to be added with the image density, the information stored in the ROM is subjected to dot-line modulation for each line and the image signal is modulated. By adding information to the inside and providing a line that serves as a mark to indicate the position where the information is added, it is possible to easily find the relevant part when extracting the additional information, and to arrange the dots in that area. There is an effect that the added information can be easily restored by measuring.

<Fifth Embodiment> The fifth embodiment of the present invention will be described below.
An example will be described. Although the information to be added is stored in the ROM prepared in advance in the fourth embodiment, other information may be given here. FIG.
FIG. 9 is a block diagram showing a configuration of an image processing unit of a full-color copying apparatus according to a fifth embodiment of the present invention. In the figure, the same components as those of the image processing unit shown in FIG. 8 are designated by the same reference numerals, and their description will be omitted. Therefore, a configuration different from that of FIG. 8 will be described.

In FIG. 18, 1000 is a CPU, 10
Reference numeral 01 is a ROM storing a program for operating the CPU 1000, and 1002 is an R having a storage area such as a work area used when the CPU 1000 operates.
AM and 1003 are RAs for capturing and storing image signals
M and 1004 are ROMs for writing information to be added, and 1005 is an operation unit for instructing the operation of the apparatus.

The CPU 1000 performs operations such as reading an image signal and writing additional information to the RAM 1004. The RAM 1003 stores the image signal, and C
It can be accessed from the PU 1000. RAM
Reference numeral 1004 denotes a RAM in place of the ROM in the image processing apparatus according to the fourth embodiment. The ROM in FIG. 17 is replaced with the RAM. Then, the contents can be freely rewritten from the CPU 1000.

The operation of the full-color copying apparatus having the above structure will be described. FIG. 19 is a flowchart showing the operation of the full-color copying machine according to this embodiment.
In this full-color copying apparatus, the information to be added in the apparatus as a pattern is read before performing all copying operations. In this apparatus, this pattern is prepared in the form of a bar code and is attached to a part of a normal standard white plate or outside the image area on the CCD line sensor. Then, this data is read in RAM1.
The data is written in 003 and is taken in as an image.
Subsequently, the CPU 1000 accesses the RAM 1003 and extracts information to be added from the read image data (step S101).

Then, in order to check whether the reading error or the tampering with the additional pattern has been made, the check data is calculated from the data portion of the pattern (step S102). By comparing the check data obtained by this calculation with the check data portion of the pattern (step S103), it is determined whether or not the correct information is read (step S104). If it is determined in this step S104 that the data is not correct, a serviceman call is displayed and the subsequent operation is stopped. However, if it is confirmed in step S104 that the data is regular data, the information to be added is added to the RAM 100.
4 is written (step S105), the mode shifts to the normal copying operation mode.

It is not necessary to carry out the above operation for each copying operation, but normally it may be carried out as a part of self-diagnosis immediately after the power is turned on. Further, the copying operation after the information is once set in the RAM 1004 is the same as that of the above-mentioned fourth embodiment, and therefore its explanation is omitted. FIG. 20 is a diagram showing a state in which additional information is mounted on the image reading unit section 1201 in the full-color copying apparatus according to this embodiment. Here, the image reading unit is a document table 1 on which a document is placed.
The CCD line sensor 2101 scans the inside of 202, and the standard white plate used for normal shading operation is provided near the home position of the CCD line sensor. Then, the information to be added is written in a part of the standard white plate with a code that can be read by the CCD line sensor. Here, the known barcode is encoded as described above, and in step S101 of the flowchart shown in FIG. 19, the code is read to obtain information.

As described above, in the present embodiment, the additional information provided as the image pattern is read and then set, and the additional information is provided outside the image processing unit to repair the apparatus. Even if the circuit is exchanged due to, for example, the same additional information can be always held. In addition, a part of the additional information may be set, for example, by a key input unit of the operation unit 1005 of the apparatus.

<Modification> In each of the above-mentioned embodiments, the predetermined information is added, but like the device according to the fifth embodiment, the additional information is once written in the RAM table. By adopting the method of adding by this, the information to be added can be processed when the processing is executed. That is, not only the serial number of the apparatus, but also the time and date of printing of the apparatus is coded and added by incorporating the clock mechanism of the apparatus, and the magnetic card, the IC card, the ID card, etc. used in the copying apparatus. User information can be added together with a means for identifying a user such as a control card.

If the apparatus is a facsimile apparatus, it is possible to add a telephone number or flexibly add information to the output image. In each of the above embodiments, the modulation is performed over the entire line, but it is not always necessary to perform the modulation for the entire line. For example, the modulation operation may be performed only on a part of the line. I don't care. Further, the modulating direction is not limited to the reading direction of the CCD line sensor, and it goes without saying that, even if the modulating is carried out in a direction orthogonal to the reading direction, there is no difference relating to the essence of the invention.

Further, in the method of changing the dot interval, the method of changing the dot interval may be a method other than the method of distinguishing between the even number and the odd number. Further, in each of the above embodiments, the density determination is performed based on the signal after binarization, but the density determination may be performed using a multilevel signal before binarization. In each of the above embodiments, an example in which the present invention is applied to a full-color copying apparatus has been shown, but the symmetrical apparatus is not limited to the copying apparatus, and basically any other apparatus can be used as long as it outputs a binary image. The present invention can also be applied to, for example, a facsimile device or a printer device.

In each of the above embodiments, C, M, Y,
K data was transmitted serially, but C, M, Y, K
It is also possible to perform parallel image processing by independently having a binarization processing circuit. In this case, the modulation circuit described above may be provided for each of C, M, Y, and K colors. Further, the additional information is not limited to the serial number of the device, and may be information such as the date and time of copying and the ID code of the person who copied.

Although binary dot data is modulated in each of the above-described embodiments, it is not limited to binary dots and may be multivalued dots. In the above-described embodiment, the image reader is used as the input unit to read the document to generate the image data. However, the input unit is not limited to the image reader and may be a still video camera, a video camera, a host computer, or the like.

Further, the output means is not limited to the laser beam printer or the ink jet printer, but may be a thermal transfer printer, a dot printer or the like. In particular, a bubble jet type printer of a type that ejects droplets by utilizing boiling due to thermal energy may be used. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

The combination of the above embodiments is included in the concept of the present invention. The present invention may be applied to a system including a plurality of devices, for example, a series of systems such as a scanner, a host computer, and a printer, or an apparatus including one device, such as a copying machine.

[0072]

As described above, according to the present invention,
The effect that the additional information can be easily specified from the output image by modulating the dot interval to the binarized image signal, adding predetermined information, and providing a mark indicating the addition position. There is. Further, by easily specifying the additional dot interval of the predetermined information, it is possible to suppress the deterioration of the image signal and add the information.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image processing unit in a full-color copying apparatus according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a density determination circuit 110 according to the first embodiment.

FIG. 3 is an additional pattern generation circuit 11 according to the first embodiment.
FIG. 3 is a block diagram showing the configuration of No. 1.

FIG. 4 is a flowchart illustrating an operation according to the first embodiment.

FIG. 5 is a block diagram showing a configuration of an image processing unit in a full-color copying apparatus according to a third embodiment.

FIG. 6 is a block diagram showing a configuration of an additional pattern generation circuit according to a third embodiment.

FIG. 7 is a flowchart illustrating an operation according to the third embodiment.

FIG. 8 is a block diagram showing an overall configuration of an image processing unit of a full-color copying apparatus according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing an internal configuration of an image processing circuit 2102 according to a fourth embodiment.

FIG. 10 is a timing chart of an image signal according to the fourth embodiment.

FIG. 11 is a block diagram showing a configuration of a modulation circuit 2105 according to a fourth example.

FIG. 12 is a dot position correction circuit 24 according to a fourth embodiment.
It is a detailed block diagram of 01.

FIG. 13 is a diagram showing, in a tabular form, a process for generating lines of odd intervals according to the fourth embodiment.

FIG. 14 is a detailed configuration block diagram of a mark adding circuit 2402 according to a fourth embodiment.

FIG. 15 is a diagram illustrating a change in an image signal due to the operation of the modulation circuit 2105 according to the fourth example.

FIG. 16 is a block diagram showing a configuration of a density determination circuit 2106 according to the fourth embodiment.

FIG. 17 is a block diagram showing a configuration of a ROM 2104 according to the fourth embodiment.

FIG. 18 is a block diagram showing the arrangement of an image processing unit of a full-color copying machine according to the fifth embodiment of the present invention.

FIG. 19 is a flowchart illustrating an operation of the device according to the fifth embodiment.

FIG. 20 is a diagram for explaining a method of inputting additional information according to the fifth embodiment.

FIG. 21 is a diagram schematically showing how information is added to an image in the fifth embodiment.

FIG. 22 is a block diagram showing the configuration of a timing signal generation circuit 2109 according to the fifth example.

[Explanation of symbols]

101,511,2101 CCD line sensor 102,512 A / D converter 103,513 Shading correction circuit 104,514 Density conversion circuit 105,515 Masking / UCR circuit 106,516 γ correction circuit 107,2103 Binarization circuit 108,503 , 2107 drive circuits 109-1 to 109-4, 504-1 to 504-4, 2
108 ink head 110, 2106 density determination circuit 111, 501 additional pattern generation circuit 112, 505, 1000 CPU 113, 506, 1001, 104 ROM 114, 507, 1002, 1003, 1004 RA
M 115 AND gate 116 OR gate 502 Adder circuit 2102 Image processing circuit 2105 Modulation circuit 2109 Timing signal generation circuit 2110 Power supply circuit 2111 FIFO

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location B41J 2/505 G06F 15/62 310 Z 8125-5L H04N 1/00 C 7046-5C 1/23 101 C 9186-5C 1/40 Z 9068-5C 8306-2C B41J 3/04 101 A 9211-2C 3/10 101 Z

Claims (8)

[Claims] 1. A generating unit for generating a plurality of dot data, a detecting unit for detecting a dot interval formed according to the dot data generated by the generating unit, and a control unit for controlling the dot interval, An image processing apparatus, wherein the dot spacing controlled by the control unit expresses predetermined information not included in a dot image formed according to the dot data generated by the generation unit. 2. A generation step of generating a plurality of dot data, a detection step of detecting a dot interval formed according to the dot data generated by the generation step, and a control step of controlling the dot interval, The image processing method, wherein the dot spacing controlled by the control step expresses predetermined information not included in a dot image formed according to the dot data generated by the generation step. 3. A generation unit that sequentially generates a plurality of types of color dot data in a dot sequence, a detection unit that detects a dot interval of the same color formed in accordance with the color dot data generated by the generation unit, and a same color Control means for controlling the dot spacing, wherein the dot spacing controlled by the control means represents predetermined information not included in the dot image formed according to the dot data generated by the generating means. Image processing device. 4. A generation step of sequentially generating a plurality of types of color dot data, a detection step of detecting dot intervals of the same color formed according to the color dot data generated by the generation step, and a detection step of the same color. A control step of controlling a dot interval, wherein the dot interval controlled by the control step represents predetermined information not included in a dot image formed according to the dot data generated by the generating step. Image processing method. 5. A generation means for generating image data, a judgment means for judging whether or not the level of the image data is within a predetermined range, and an addition means for adding predetermined information to an image represented by the image data. An image processing apparatus comprising: a control unit that controls addition of the addition unit according to the determination of the determination unit. 6. A generating step of generating image data, a judging step of judging whether or not the level of the image data is within a predetermined range, and an adding step of adding predetermined information to an image represented by the image data. And a control step of controlling the addition of the addition step according to the determination of the determination step. 7. The image forming apparatus includes: a generating unit that generates image data; and a processing unit that processes the image data generated by the generating unit and outputs a reproduction signal that forms an image. An image including: an addition unit that adds predetermined information to the image; and a control unit that controls the image density after the addition by the addition unit to substantially store the image density before the addition by the addition unit. Processing equipment. 8. A generation step of generating image data, and a processing step of processing the image data generated by the generation step and outputting a reproduction signal for forming an image, wherein the processing step is performed on the image. An image including an addition step of adding predetermined information to the image, and a control step of controlling the image density after the addition by the addition step to substantially store the image density before the addition by the addition step. Processing method.