JPH05299979A - Pulse generating circuit and pulse width measuring circuit - Google Patents

Abstract

PURPOSE:To generate a clock pulse synchronously with the rising of an input pulse, while a pulse width is kept the same only during the active state period. CONSTITUTION:A flip flop 2 is inverted through a delay circuit 3 by a clock pulse being the output of the flip flop 2 which is turned to an inversion state at the time of the appearance of an input pulse (a) inputted through an AND gate 1. Then, when the AND is taken between the input pulse (a) and the output of a delay circuit 3 through a delay circuit 4 by the gate 1 in order to invert the flip flop 2 again, the clock pulse can be generated synchronously with the rising of the pulse (a), while the pulse width is kept the same only during the active state period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generates a clock pulse having a desired pulse width in synchronization with the rising edge of an input pulse which appears in an active state for a certain time and only during the active state period. And a pulse width measuring circuit for measuring the pulse width of the input pulse by counting the clock pulse.

[0002]

2. Description of the Related Art Heretofore, as a pulse generation circuit for generating a clock pulse having a desired pulse width only when the input pulse appears, in synchronization with the rising edge of the input pulse and only during the active state thereof, for example, The one described in JP-A-55-21639 is known.
In this case, the input pulse that is active for a certain time is delayed and inverted through the AND gate, and then ANDed again with the original input pulse to synchronize with the input pulse. , The clock pulse is generated only during its active period.

[0003]

However, in the case of the above publication, the pulse width of the last clock pulse is changed depending on the timing at which the input pulse shifts to the inactive state. That is, the pulse width of the last clock pulse depends on the timing at which the input pulse shifts to the inactive state, and therefore the pulse width is the pulse width (constant pulse width) of the clock pulse generated before that. In general, the pulse width is not the same, and its pulse width changes variously within a constant pulse width. Therefore, when the clock pulse thus generated is supplied to the external circuit as a clock, the circuit operation in the external circuit (for example, the counter) cannot be guaranteed depending on the pulse width of the last clock pulse. It has become a thing.

A first object of the present invention is to generate a clock pulse having a desired pulse width in synchronization with the rising edge of an input pulse and only during the active state of the input pulse. It is to provide a pulse generation circuit that can be generated as a constant. A second object of the present invention is to provide a pulse width measuring circuit capable of measuring the pulse width of the input pulse itself.

[0005]

The first object of the present invention is to provide a variable delay time by a clock pulse as an output of a flip-flop which is in an inverted state at the output of an input pulse through an AND gate. In order to invert the flip-flop via the delay circuit of the second delay circuit and then to invert the flip-flop again, the output of the first delay circuit is changed to the second delay time variable.
This is achieved by ANDing the input pulse with the AND gate through the delay circuit of. The second purpose is to invert the flip-flop via the first delay circuit having a variable delay time by the output of the flip-flop which is in the inverted state at the output of the input pulse via the AND gate. In order to invert it again, the output of the first delay circuit is logically ANDed with the input pulse by the AND gate through the second delay circuit whose delay time is variable, while the flip-flop, the first delay circuit, the second This is achieved by counting the output of any one of the delay circuits of.

[0006]

For example, when the flip-flop is placed in the set state, its output is delayed by the desired time, and then the flip-flop is automatically placed in the reset state, and after the desired time elapses, the flip-flop is again set to the constant condition. If you want to configure to automatically set under
Since the output of the flip-flop changes at a constant cycle, it can be used as a clock pulse.
That is, when the transition of the flip-flop to the set state is allowed only while the input pulse is in the active state, the transition of the input pulse to the inactive state simply determines whether or not the flip-flop can transit to the set state. The last clock pulse generated has the same pulse width as the pulse width of the clock pulse generated before, since it only makes a decision and does not directly participate in the transition of the flip-flop to the reset state. It is something. By the way, since the clock pulse itself is used as a time reference, if the number of clock pulses corresponding to the size of the pulse width of the input pulse is automatically generated, simply change the number of clock pulses. The pulse width of the input pulse can be measured only by counting with a counter.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS.
FIG. 1 shows a concrete circuit configuration of an example of a pulse width measuring circuit including a pulse generating circuit according to the present invention. In this case, most of the pulse width measuring circuit is configured as a pulse generating circuit, and the pulse width of the input pulse a can be measured by counting the clock pulses from the pulse generating circuit with the counter 8. Has become. The circuit configuration of the pulse generating circuit and its operation will be described below with reference to FIG.

That is, in the initial state, the flip-flop (hereinafter referred to as F / F) 2 is in the reset state, but in such a state, the input pulse (in this example, the "H" level state). Assuming that a appears, the input pulse a acts on the F / F2 as a set signal via the AND gate. As a result, the F / F2 is caused to shift to the set state at the rising edge of the input pulse a, but its Q output c is delayed by the desired time on the delay circuit 3 and the delayed Q output c is obtained from the switch 6. Is becoming The delay time of the Q output c in the delay circuit 3 is determined by the switching connection position of the switch 6. Now, the F / F2 is reset by its delayed Q output c, but at that time, when it is necessary to obtain a clock pulse having a small period (for example, when the pulse width of the input pulse a is measured with high accuracy), F
It is desirable that / F2 be reset by the rising differential pulse of the delayed Q output c.

On the other hand, the delayed Q output c is also delayed by the delay circuit 4 for a time period corresponding to the switching connection position of the switch 7 and then ANDed with the input pulse a via the inverter 5. As a result b, the transition of the F / F2 to the set state is controlled. That is, if the input pulse a is not already in the active state, F / F
2 is not shifted to the set state, but when it is still in the active state, the F / F 2 is placed in the set state again and the above operation is repeated. After all,
As long as the input pulse a is in the active state,
Since the F / F2 is repeatedly shifted to the set state, a clock pulse synchronized with the rising edge of the input pulse a is obtained from the F / F2. At this time, the pulse width of the last generated clock pulse depends only on the delay time in the delay circuit 3 and is independent of the state of the input pulse a, so that the clock pulse is generated as intended. It is a reward.

In the above example, the clock pulse to the counter 8 is from the F / F2. However, if the phase of the input pulse a is not a particular problem, any one of the delay circuits 3 and 4 can be used. It is clear from FIG. 2 that the clock pulse may be obtained from

[0011]

As described above, according to the first aspect of the present invention, when the clock pulse having the desired pulse width is generated only in synchronization with the rising edge of the input pulse and during the active state thereof, it is generated last. A pulse generation circuit capable of generating a clock pulse having a constant pulse width, and in the case of claim 2, a pulse width measurement circuit capable of measuring the pulse width of the input pulse itself are obtained. There is.

[Brief description of drawings]

FIG. 1 is a diagram showing a specific circuit configuration of an example of a pulse width measuring circuit including a pulse generating circuit according to the present invention.

FIG. 2 is a diagram showing an example of input / output signal waveforms in its main part.

[Explanation of symbols]

1 ... AND gate, 2 ... Flip-flop, 3, 4 ... Delay circuit, 5 ... Inverter, 8 ... Counter

Claims (2)

[Claims] 1. A pulse width generation circuit for generating a clock pulse with an arbitrary period and duty ratio for an input pulse which is active for a certain period of time, the input pulse passing through an AND gate. The clock pulse as the output of the flip-flop in the inverted state at the present time causes the flip-flop to be inverted and then inverted again via the first delay circuit having a variable delay time. A pulse generation circuit having a configuration in which an output is logically ANDed with an input pulse by the AND gate through a second delay circuit having a variable delay time. 2. A pulse width measuring circuit for measuring a pulse width of an input pulse which is in an active state for a certain period of time, which comprises a flip-flop which is in an inverted state at the present moment of output of the input pulse through an AND gate. According to the output, the output of the first delay circuit is inverted via the first delay circuit with a variable delay time, and then the flip-flop is inverted again. A pulse width measuring circuit configured such that the output of any one of the flip-flop, the first delay circuit, and the second delay circuit is counted by a counter while being logically ANDed with an input pulse by a gate.