JPH0528408B2 - - Google Patents
Info
- Publication number
- JPH0528408B2 JPH0528408B2 JP62030326A JP3032687A JPH0528408B2 JP H0528408 B2 JPH0528408 B2 JP H0528408B2 JP 62030326 A JP62030326 A JP 62030326A JP 3032687 A JP3032687 A JP 3032687A JP H0528408 B2 JPH0528408 B2 JP H0528408B2
- Authority
- JP
- Japan
- Prior art keywords
- digit
- circuit
- signal
- sum
- addend
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62030326A JPS63197227A (ja) | 1987-02-12 | 1987-02-12 | 加算器 |
| US07/086,967 US4866657A (en) | 1986-07-18 | 1987-08-18 | Adder circuitry utilizing redundant signed digit operands |
| US03/239,243 US5031136A (en) | 1986-06-27 | 1990-05-07 | Signed-digit arithmetic processing units with binary operands |
| US07/599,275 US5153847A (en) | 1986-06-27 | 1990-10-16 | Arithmetic processor using signed digit representation of internal operands |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62030326A JPS63197227A (ja) | 1987-02-12 | 1987-02-12 | 加算器 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63197227A JPS63197227A (ja) | 1988-08-16 |
| JPH0528408B2 true JPH0528408B2 (enrdf_load_stackoverflow) | 1993-04-26 |
Family
ID=12300686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62030326A Granted JPS63197227A (ja) | 1986-06-27 | 1987-02-12 | 加算器 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63197227A (enrdf_load_stackoverflow) |
-
1987
- 1987-02-12 JP JP62030326A patent/JPS63197227A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63197227A (ja) | 1988-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100500855B1 (ko) | 연산장치의연산방법,기억매체및연산장치 | |
| US4878192A (en) | Arithmetic processor and divider using redundant signed digit arithmetic | |
| US6816877B2 (en) | Apparatus for digital multiplication using redundant binary arithmetic | |
| US3842250A (en) | Circuit for implementing rounding in add/subtract logic networks | |
| JPH0619685A (ja) | 並列乗算回路 | |
| JPH0552530B2 (enrdf_load_stackoverflow) | ||
| US4873660A (en) | Arithmetic processor using redundant signed digit arithmetic | |
| JPH0312738B2 (enrdf_load_stackoverflow) | ||
| JPH09222991A (ja) | 加算方法および加算器 | |
| GB1582958A (en) | Digital system for binary multiplication of a number by a sum of two numbers | |
| JPH0528408B2 (enrdf_load_stackoverflow) | ||
| US5206825A (en) | Arithmetic processor using signed-digit representation of external operands | |
| US5153847A (en) | Arithmetic processor using signed digit representation of internal operands | |
| JPH03228122A (ja) | 加算回路 | |
| JPS6349835A (ja) | 演算処理装置 | |
| JPH0370416B2 (enrdf_load_stackoverflow) | ||
| JP2608600B2 (ja) | 2つの数の和のパリティビットの計算装置 | |
| JPS63182739A (ja) | 乗算処理装置 | |
| JPS6371729A (ja) | 演算処理装置 | |
| JPH0652500B2 (ja) | 演算処理装置 | |
| JPS6319035A (ja) | 演算処理装置 | |
| JPH06230933A (ja) | 演算処理装置 | |
| JPH0438520A (ja) | 2進数データ変換装置 | |
| JPS638826A (ja) | 演算処理装置 | |
| JPH05108308A (ja) | 乗算回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |