JPH05283612A - Capacity element - Google Patents

Abstract

PURPOSE:To heighten integration degree of capacitor elements by constituting at least one electrode of an insulator composed of a plurality of elements which exhibit a dielectric constant of 20 or above upon oxidation or an insulator having histeresis in polarization. CONSTITUTION:After forming an SiO2 film 105 on a silicon substrate 106, a polysilicon film 104 is deposited and an alloy film 103 of lead and titanium is further formed thereon. A ferroelectric thin film 102 of BaTiO3 is formed in contact with this alloy film and polysilicon 101 is finally deposited to constitute a capacitor element. The ferroelectric thin film 102 of BaTiO3 has the specific dielectric constant of 20 or above and thereby a capacitor having required capacitance can be constituted with reduced area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high integration of a capacitive element using a ferroelectric material or a high dielectric material, and a semiconductor memory device having a high integration degree using this capacitive element.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM) has been studied vigorously in recent years because of its large storage capacity and high speed as a storage element of a computer, and higher speed and higher integration have been advanced.

FIG. 7 shows a basic circuit diagram of a general DRAM memory cell section. The memory cell is composed of a MOS transistor 1101 and a capacitor 1102 as a pair,
1-bit data is stored according to the amount of charge accumulated in the capacitor 1102. MOS transistor 1101
Is connected to the word line 1103, and the word line 1103 is connected to the decoder driver of the peripheral circuit. The drain electrode of the MOS transistor 1101 is connected to the bit line 1104, and this bit line is connected to peripheral circuits such as the sense amplifier 1105, the read circuit 1106, and the write circuit 1107. The drain electrode is connected to one electrode of the capacitor, and the other electrode is connected to a plate line common to each bit.

The capacitance of the capacitor 1102 is an error (called a soft error) due to the electric charge caused by α rays.
In order to have a resistance to, a charge of 100 fC or more must be accumulated. If 1.5 V of 1/2 Vcc is applied to the plate electrode at a power supply voltage of 3 V, the capacitor 1102 needs to have a capacity of 60 fF or more.

Generally, the capacitance of a capacitor is proportional to the relative permittivity of the insulating film and the electrode area of the capacitor, and is inversely proportional to the film thickness of the insulating film. It is necessary to reduce the film thickness and use an insulating film having a large dielectric constant. However, in the highly integrated DRAM, it is required to reduce the surface area occupied by each memory cell, and it is becoming difficult to obtain a sufficient capacitor electrode area by the techniques used so far. Therefore, research is being conducted to increase the surface area. For example, 1991 Symposium on VLSI Techn
The surface area is being increased through a complex process as described in ology Digestof Technical Papers P7-P13.
The thickness of the insulating film has a limit in reducing the thickness of the insulating film because of its relation to the breakdown electric field strength.

On the other hand, as described in Proceedings of the 8th Ferroelectric Application Conference Proceedings, p3-p29, research is underway to use substances having a large relative dielectric constant of an insulating film. Ta ₂ O ₅ and TiO ₂ are 20 as materials having a large relative dielectric constant.
To about 100 or more, Pb (Z
rTi) O ₃ , (PbLa) (ZrTi) O ₃ , BaTi
A ferroelectric material having a perovskite type crystal structure such as O ₃ or SrTiO ₃ is to be used.

FIG. 37 is a diagram for explaining the spontaneous polarization effect of the ferroelectric substance.

As shown in this figure, there is a phenomenon called spontaneous polarization in a substance, which has polarization in the substance, even when no electric field is applied from the outside. A technique relating to a ferroelectric memory using this spontaneous polarization as a memory is disclosed in Japanese Patent Laid-Open No. 63-20199.
No. 8, JP-A-64-066897, JP-A-1
It is described in JP-A-158691.

FIG. 8 shows an equivalent circuit diagram of a memory cell using the history of polarization of the ferroelectric substance. This memory cell is composed of a pair of transistors and a ferroelectric capacitor.
At this time, the storage state can be retained in a non-volatile manner by utilizing the remanent polarization of the ferroelectric substance. Hereinafter, such a memory is referred to as a ferroelectric memory (FRAM), and DRA
Distinguish from M.

There are various other applications of the dielectric such as an infrared sensor and electro-optics. With the miniaturization and integration of these electronic components, the dielectric is also miniaturized.
Thinning is progressing.

[0011]

In order to reduce the size and increase the speed of a computer, it is necessary to highly integrate the storage device inside the computer. Therefore, in order to miniaturize the semiconductor device used in these internal storage devices, it is desired to reduce the storage cells per bit. Therefore, it is necessary to reduce the capacitance element used in the dynamic type memory and the ferroelectric non-volatile memory, and the dielectric constant used in the capacitance element is increased and the ferroelectric substance spontaneously shown in FIG. Increasing the polarization value is essential.

However, in the above-mentioned prior art, in order to form an oxide insulator having a dielectric constant of 20 or more or a history of polarization to obtain good crystallinity, the substrate temperature is 500 ° C. in an oxygen atmosphere. It is necessary to raise the temperature above. For this reason, the base electrode is exposed to an oxygen atmosphere at a high temperature, and when a metal other than a noble metal such as aluminum or a semiconductor such as polysilicon is used as the base electrode, the surface of the metal or the semiconductor is oxidized. And an insulator is formed.

FIG. 38 is an explanatory diagram of a capacitive element in which a noble metal is used as a base electrode and a ferroelectric substance is formed thereon.

FIG. 39 is an explanatory diagram of a capacitive element when aluminum is used as a base electrode and a ferroelectric substance is formed thereon.

As shown in FIG. 39, the relative permittivity of a substance formed by oxidizing a metal or a semiconductor is, for example, about 4.0 for SiO ₂ and about 9.0 for Al ₂ O ₃ , and the relative permittivity is about 10. 20
Is less than. The film thickness of the oxide formed by oxidizing such a surface is about 5 nm to 20 nm.

As a result, a series junction is formed between the deposited high dielectric constant film and the low dielectric constant film formed by oxidizing the surface,
Even if the film thickness of the high-dielectric-constant film is reduced, it is impossible to obtain a film having a high dielectric constant.

FIG. 40 is a table showing the relationship between the ferroelectric film thickness and the capacitance of the capacitive element formed with the ferroelectric shown in FIGS. 38 and 39.

In this figure, it is assumed that BaTiO ₃ is used as the ferroelectric substance, its dielectric constant is 2000, the base electrode is polysilicon, and the SiO ₂ film is formed to a thickness of 5 nm at the interface with Si.
The results of simulating the relationship between the capacitance of the capacitor and the thickness of the BaTiO ₃ film when the electrode area was 1 × 1 μm ² and the relationship when no oxide film was formed are shown. Even if the high-dielectric-constant film having such a small surface area is made thin, there is a problem that a desired capacitance value cannot be obtained. Further, when the film thickness is reduced in this way, there is a problem that the leak current between the electrodes becomes large and the charge retention characteristics deteriorate. Further, when such a capacitive element is used as the capacitance of a DRAM, the charge accumulated during writing decreases, and a sufficient amount of charge does not remain during reading, so that the film thickness cannot be reduced, and therefore the desired capacitance is obtained. In such a case, there is a problem that the area occupied by the capacitance increases and the element area cannot be reduced.

Even if a metal having no low dielectric constant oxide formed on the surface is used, an oxide insulator having a dielectric constant of 20 or more or having a history of polarization is used as a base material or an insulator. If formed above, the crystallinity of the oxide insulator film deteriorates near the interface due to the mismatch of the lattice constants of the base material and the oxide insulator film, and the dielectric constant near the interface decreases. As a result, if the base material is made of a metal that is not oxidized and this metal is used as one of the electrodes, a capacitor with a high dielectric constant layer and a low dielectric constant layer near the interface between the base material and a series is formed. However, even if this low dielectric constant layer is a thin film of several nm, there is a problem that the effective dielectric constant is lowered.

As a substance which does not form such a low dielectric constant oxide, a noble metal such as platinum or palladium has been used so far as shown in FIG. In these technologies, even if a ferroelectric film with a relatively high crystallinity and a high dielectric constant can be formed and an insulator with a high effective dielectric constant is formed, noble metals such as platinum are processed by dry etching. However, it can be processed only by ion milling or wet etching. With the ion milling and wet etching techniques described above, it is difficult to form a highly integrated capacitive element because it is not possible to perform fine processing as is done by dry etching.

An object of the present invention is to provide a highly integrated capacitive element.

An object of the present invention is to provide a memory using a highly integrated capacitive element.

[0023]

[Means for Solving the Problems] The above-mentioned object is to obtain a dielectric constant of 2
In a capacitive element including 0 or more or an oxide dielectric having a history of polarization and electrodes in contact with both surfaces of the oxide dielectric, at least one electrode is composed of a plurality of elements and is 20 or more when oxidized. This is achieved by using an insulator having a dielectric constant of or a history of polarization.

The above object is to provide a capacitive element comprising a dielectric film formed by oxidation of a plurality of elements and electrodes in contact with both surfaces of the dielectric film, wherein at least one electrode is the dielectric film. This is achieved by including a plurality of contained elements.

The above-mentioned object is that the dielectric film has a relative dielectric constant of 2
This is achieved by having a high dielectric film of 0 or more.

The above object is achieved by the fact that the dielectric film is a ferroelectric film having a history of polarization.

The above objective is accomplished by the fact that the dielectric is formed by oxidation of at least one electrode.

The above object is achieved by the fact that the oxide dielectric and the electrode are in contact with each other through the oxide of the electrode.

The above object is achieved by the fact that the dielectric and the electrode containing a plurality of elements forming the dielectric are in contact with each other through the oxide of the electrode.

The above-mentioned object has a history of polarization of the oxide dielectric of the capacitive element, and one electrode is electrically connected to the active element so that the memory function is determined by the polarization direction of the oxide insulator. This is achieved by providing a non-volatile memory in which the provided memory cells are arranged in a matrix on a semiconductor substrate.

The above object is achieved by providing a dynamic random access memory in which one electrode of the capacitive element is electrically connected to an active element.

The above object can be achieved by providing a semiconductor memory card using the non-volatile memory.

The above object is achieved by providing a semiconductor memory card using the dynamic random access memory.

The above object is achieved by providing a semiconductor disk substrate using the non-volatile memory.

The above object is achieved by providing a semiconductor disk substrate using the dynamic random access memory.

The above object can be achieved by providing a microprocessor using the non-volatile memory.

The above object is achieved by providing a microprocessor using the dynamic random access memory.

The above object can be achieved by providing a computer using any of the nonvolatile memory, dynamic random access memory, semiconductor memory card, semiconductor disk substrate, and microprocessor.

[0039]

[Function] Instead of the conventional material used as the electrode of the capacitive element using the oxide high dielectric or the oxide ferroelectric, it is composed of two or more kinds of elements and has a dielectric constant of 20 or more when oxidized. Even if an oxide film is formed between the electrode and the dielectric in the oxidation step for obtaining the oxide high dielectric or oxide ferroelectric by using a material that becomes an insulator or an insulator having a history of polarization The dielectric constant of the oxide film is high or exhibits ferroelectricity, and even if the electrode, this oxide film, the oxide high dielectric substance or the oxide ferroelectric substance is connected in series, the capacitance value of the entire capacitance element does not decrease and is high. Since the capacitance value is obtained, the degree of integration of the capacitance element can be increased.

By containing two or more kinds of elements contained in the dielectric in the electrode, the electrode whose surface is oxidized does not decrease the capacitance value by the substance whose surface is oxidized, and the electrode whose surface is oxidized is the dielectric. The composition is similar to the above, and the crystallinity is improved, so that the leak current between the electrodes can be reduced and the dielectric constant of the dielectric can be improved.

By using a high-dielectric or ferroelectric film having a relative permittivity of 20 or more as a dielectric of such a capacitive element, a capacitance having a large capacitance value can be obtained and a required capacitance can be constructed with a small capacitance area.

As such a dielectric material, KNbO ₃ , NaT
aO ₃ , KTaO ₃ , SrTiO ₃ , BaTiO ₃ , PbTiO ₃ , SrZrO ₃ , BaZr
O ₃ , BiFeO ₃ , (Na _1/2 Bi _1/2 ) TiO ₃ , (K _1/2 Bi _1/2 ) TiO ₃ , (K
_{1/2 La 1/2) TiO 3} , (Ba 1/2 Pb 1/2) TiO 3, (Ca 1/2 Sr 1/2) Ti
_{O 3, (Na 1/2 Nd 1/2} ) TiO 3, (Ag 1/2 Ce 1/2) TiO 3, (Pb 1/2 Ca
_1/2 ) ZrO ₃ , Ba (Mg _1/2 Te _1/2 ) O ₃ , Ba (Mn _1/2 Te _1/2 ) O ₃ , Ba (C
o _1/2 Te _1/2 ) O ₃ , Ba (Cd _1/2 Te _1/2 ) O ₃ , Pb (Mg _1/2 Te _1/2 ) O ₃ ,
Pb (Mn _1/2 Te _1/2 ) O ₃ , Pb (Co _1/2 Te _1/2 ) O ₃ , Pb (Ni _1/2 Te _1/2 )
O ₃ , Pb (Zn _1/2 Te _1/2 ) O ₃ , Pb (Cd _1/2 Te _1/2 ) O ₃ , Pb (Co _1/2 W _{1
/ 2} ) O ₃ , Pb (Zr _1/2 Ti _1/2 ) O ₃ , Pb (Mg _1/2 Nb _1/2 ) O ₃ , Pb (Sc
_{1/2 Nb 1/2) O 3, Pb} (Mn 1/2 Nb 1/2) O 3, Pb (Fe 1/2 Nb 1/2) O 3, P
_{b (Ni 1/2 Nb 1/2) O} 3, Pb (In 1/2 Nb 1/2) O 3, Pb (Fe 1/2 W 1/2)
O ₃ , Pb (Lu _1/2 Ta _1/2 ) O ₃ , Pb (Yb _1/2 Ta _1/2 ) O ₃ , Pb (Cu _1/2 Sb
_{1/2) O 3, Pb (Al} 1/2 Sb 1/2) O 3, Ca (Mg 1/2 Te 1/2) O 3, Ca (Mn
_1/2 Te _1/2 ) O ₃ is used, and the electrode material is KNb, Na
Ta, KTa, SrTi, BaTi, PbTi, SrZ
r, BaZr, BiFe, NaBiTi, KBiTi,
KLaTi, BaPbTiO ₃ , CaSrTi, NaN
dTi, AgCeTi, PbCaZr, BaMgTe,
BaMnTe, BaCoTe, BaCdTe, PbMg
Te, PbMnTe, PbCoTe, ZnTe, PbC
dTe, PbCoW, PbZrTi, PbMgNb, P
bScNb, PbMnNb, PbFeNb, PbNiN
b, PbInNb, PbFeW, PbLuTa, PbY
bTa, PbCuSb, PbAlSb, CaMgTe,
By using the CaMnTe material, the matching between the dielectric and the electrode is improved.

By oxidizing some of the electrodes of the capacitive element using the above-mentioned dielectric, a dielectric having easy and uniform film characteristics can be formed.

By interposing the oxide of the electrode between the oxide dielectric of such a capacitive element and the electrode, the matching of the dielectric is improved.

The oxides of the electrodes of the above two types of capacitive elements are formed by applying high temperature heat treatment in an oxygen atmosphere. Alternatively, by exposing the electrode oxide to plasma containing oxygen, the dielectric film can be formed at a relatively low temperature, and the process compatibility with other relatively low heat resistance elements is improved. However, it becomes possible to make a multifunctional element on-chip.

By forming the oxide of the electrode in the process of forming the oxide dielectric, the step for intentionally forming the oxide of the electrode can be omitted, and the element cost can be reduced and the variation between the processes can be reduced. it can.

A memory cell having a history of polarization of the oxide insulator of the above-mentioned capacitance element, an electrode of this capacitance element being electrically connected to an active element, and having a storage function depending on the polarization direction of the oxide insulator. By arranging in a matrix on a semiconductor substrate to form a semiconductor memory device, a capacitive element having memory characteristics can be formed in a small occupied area, so that high integration of the element can be achieved.
In addition to miniaturization and high functionality, the processing speed can be improved by high integration and miniaturization.

The electrode of the capacitance element is electrically connected to the source electrode of the MOS transistor, the other electrode is connected to the electrode common to the other storage element, and the storage function is determined by the amount of charge accumulated in the capacitance element. Memory cells provided with are arranged in a matrix, the gate electrode of the MOS transistor is connected to a wiring electrically common to the gate electrode of another MOS transistor connected to the driver circuit, and One electrode is connected to a common line with some other memory cells connected to an amplifier circuit, a read circuit, a write circuit, and a driver circuit to form a dynamic random access memory, so that the data storage capacity is occupied on the chip. The area can be reduced and high integration, miniaturization and high functionality of the device can be achieved as well as the above non-volatile memory. It is possible to improve the processing speed by reduction.

A semiconductor memory card or a semiconductor disk substrate is constructed by using the above random access memory or nonvolatile memory, a microprocessor is constructed by using the random access memory or nonvolatile memory as an internal cache memory, and a computer is constructed by using the above memory. By doing so, an inexpensive and large-capacity solid recording medium can be formed,
High-speed processing is possible, downsizing is possible, and low power consumption is possible. Further, by using the ferroelectric memory, a memory resistant to soft error can be obtained.

[0050]

Embodiments of the present invention will be described in detail below with reference to the drawings.

Example 1 FIG. 1 is a schematic diagram showing a deposited state of an oxide ferroelectric thin film of Example 1 of the present invention. A SiO ₂ film 105 having a thickness of 100 nm is formed on an 8-inch Si substrate 106, a poly-Si film 104 having a thickness of 100 nm is deposited, and a lead-titanium alloy film 1 is formed.
03 is formed to a thickness of 50 nm and is in contact with this alloy film to form BaTi.
A ferroelectric thin film 102 of O ₃ having a thickness of 100 nm is formed, and finally poly-Si 101 is deposited to form a capacitive element.

Although an alloy film is used in this embodiment, the same effect can be obtained by using a conductive sintered metal.

FIG. 2 is a schematic diagram of a capacitive element according to the prior art.

This drawing shows a cross-sectional structure of a capacitor element using only polysilicon as a base electrode. 8 inch S
A SiO ₂ film 105 having a thickness of 100 nm is formed on the i substrate 106, and a poly Si film 201 is deposited to have a thickness of 100 nm.
A ferroelectric thin film 102 of ₃ is formed to a thickness of 100 nm, and finally poly-Si 101 is deposited to form a capacitive element. The film forming method of each film is the same as the film forming method shown in FIG. In addition, the same structure as in FIG.
00 nm, BaTiO ₃ 100 nm, poly-Si 10
0 nm was deposited to form a capacitive element.

[0055] These, capacitance values of the three of the capacitor capacitance 59fF / μm ² of Figure 1, film using poly-Si on the underlying metal out of the capacitive element in FIG. 2 is a 6.5fF / μm ^2,
The film using platinum as the base metal has a film thickness of 62 fF / μm ² .
From this result, the capacitance element of the present invention has a capacitance value about 10 times that of the capacitance element using poly-Si as the base metal, and a capacitance value substantially the same as that of the capacitance element using platinum as the base film is obtained. There is. However, when platinum is used as an electrode, it cannot be processed by dry etching, and can be processed only by aqua regia or ion milling. Therefore, it is difficult to perform microfabrication, and even if microfabrication is performed, there are many variations in the shape, and when a capacitive element having an electrode area of 1 μm ² is formed, it is more difficult than a capacitive element using a PbTiZ ₄ electrode. The variation of the capacitance value is expanded ten times.

The cause of the low capacitance value of the capacitive element using a metal other than a noble metal such as poly-Si or aluminum as an electrode is that the interface with the underlying metal during the formation of the ferroelectric film is based on the analysis result. It was found that an oxide film of the underlying metal was formed between them. SiO ₂ between the poly-Si and the ferroelectric film
A film thickness of 50 nm is formed. The SiO ₂ film has a dielectric constant of 4.0, and this low dielectric constant film is connected in series with the high dielectric constant film, so that the dielectric constant is lowered.

Here, a method of forming a lead titanium alloy film will be described. The alloy is formed by the RF magnetron sputtering method.

FIG. 3 shows a phase diagram of a two-phase alloy of lead and titanium. When lead and titanium are mixed in this way, a stable alloy state is obtained when the molar ratio of lead to titanium is 1: 4. The composition of the target in this embodiment is also a lead titanium alloy of 1: 4. When argon is used as a sputtering gas and sputtering is performed at a substrate pressure of 300 ° C. at a sputtering pressure of 0.3 Pa, a lead-titanium alloy film having a molar ratio of 1: 4 and having substantially the same composition as the target is formed.

The BaTiO ₃ ferroelectric thin film has an ECR
The film is formed by the plasma assisted metal organic CVD method.

FIG. 4 shows ECR plasma assisted organometallic C.
It is explanatory drawing which shows the structure of a VD apparatus. As shown in the figure, a vacuum container provided with a substrate holder 401 on which a substrate is installed, a microwave blast tube is connected to the vacuum container through a microwave introduction window 412 made of quartz, and a microwave generator 403 is further provided. Is connected to the magnetron.
A microwave electric field of 2.45 GHz is generated from the magnetron, propagates through the microwave blast tube, passes through the quartz window, and is introduced into the vacuum container. Although not shown in the figure, the microwave blast tube is provided with a microwave tuner, a microwave propagation detector, etc., and is tuned in advance so that the electric field direction of the microwave is parallel to the substrate. Also,
Although not shown in the drawing, a substrate loading robot chamber is provided via a vacuum container and a gate valve, and the substrate is loaded into the vacuum container by the substrate transfer robot. Further, the robot chamber is connected to another film forming apparatus or the like through the gate valve, and the substrate can be continuously processed including other processing. The substrate holder 401 is equipped with a heater 406 and the substrate can be set to a maximum of 10
It can be heated up to 00 ° C. Further, a magnetic field coil 405 is installed around the vacuum container so that the direction of magnetic force lines on the substrate is perpendicular to the substrate, and a magnetic flux density of up to 1000 gauss can be generated. Carrier gas cylinder 4 so that an organometallic carrier gas can be introduced into the organometallic source container
The pipe is installed from 11, and the temperature of the pipe can be controlled from room temperature to 300 ° C. The temperature of the organometallic sources 407 and 408 and the organometallic source introducing pipe can also be independently controlled by the heater 409 from room temperature to 300 ° C. The gas is introduced in a direction perpendicular to the substrate and has a large number of introduction holes so that the film can be uniformly formed on the substrate.

The BaTiO ₃ film formation process is as follows.

A vacuum vessel was previously set to 1.0 × 10 −6 To.
After exhausting to rr, the substrate is heated by the heater 406 until the surface temperature of the substrate reaches 600 ° C. Ti (OC ₂ H ₅ )
₂ 407 and Ba (DPM) ₂ 408 are heated to 80 ° C. and 200 ° C. by respective container and pipe heaters 409, and the respective material gas vaporized by heating is heated to 50 ml / mi.
Oxygen gas 411 having a flow rate of n and 150 ml / min is introduced as a carrier gas into the vacuum container. The introduced gas causes electron cyclotron resonance by an electric field and a magnetic field of microwaves to be in a plasma state, reacts with the decomposed metal element and oxygen in an excited state, is accelerated toward the substrate, and is subjected to a film forming process.

Example 2 It is known that the ferroelectric material is improved in crystallinity, dielectric constant and leak current by annealing at high temperature of 450 ° C. or higher for a long time after film formation. Therefore, after forming the capacitor, heat treatment was performed at 600 ° C. for 10 hours, and the capacitance value of the capacitor was evaluated. As a result, the capacitance value is lowered in any of the capacitive elements, and each of them is 20 fF / μm
² , 5 fF / μm ² and 19 fF / μm ² . This is because the oxygen in the ferroelectric film is thermally diffused, a low dielectric constant SiO ₂ film is formed at the interface with the upper electrode poly-Si, and a series capacitance with the low dielectric constant film is formed. It has been lowered.

FIG. 5 is a schematic diagram showing a deposited state of the second embodiment of the present invention.

As shown in this figure, the upper electrode is also made of PbTi ₄
And a capacitive element having a multilayer structure of poly-Si was constructed. As a result, the capacitance value after annealing is improved to 65 fF / μm ² .

Embodiment 3 FIG. 6 is a sectional structural view of a DRAM memory cell portion according to Embodiment 3 of the present invention.

FIG. 7 is a circuit diagram including the periphery of a general memory cell.

FIG. 8 is a circuit diagram including the periphery of a general nonvolatile memory.

The nonvolatile memory (FRAM) has almost the same cross-sectional structure, and the read / write peripheral circuits are different as shown in FIG. In FIG. 6, after forming a local oxidation 905 for element isolation, an n-type doped layer 901, a gate oxide film, and a gate electrode 902 on a Si substrate to form a MOS transistor, a bit line 903 is formed and an oxide film is formed. Then, poly-Si 904 and PbTi ₄ 906, which will be storage nodes, were formed, and PbZrTiO ₃ 907 was further formed as a ferroelectric film. Further, poly-Si 908 to be a plate electrode is formed into a film, and aluminum wirings 911, 910, 90 for multilayer wiring are formed.
After disposing 9, etc., a protective film is formed and the DRAM memory cell portion is completed.

The film forming method of PbTi ₄ is the same as that of the first embodiment, but a film having the same characteristics can be obtained by the vapor deposition method or the like. PbZrTiO ₃ is 6 after forming PbTi _4.
It is clear from the results of X-ray diffraction that the crystallinity is improved by performing a heat treatment in an oxygen atmosphere at 00 ° C. for 1 hour to form a PbTiO ₃ film on the surface, the leakage current is small, and the dielectric constant is high. , A ferroelectric film is formed. According to the present embodiment, the electrode area is required to be 0.8 μm ^{2 in} order to obtain the capacitance necessary for reading the DRAM, and the capacitance is 64M.
It can also be applied to highly integrated DRAMs of b or higher.

Example 4 An example of using the above capacitive element in an FRAM will be described. There are various uses of the ferroelectric capacitor, but as one example, a memory having a configuration substantially similar to the DRAM shown in FIG.
The example used for backing up the SRAM data is shown. In the memory structure of the DRAM, the polarization direction of the ferroelectric is inverted not only at the time of writing the data but also at the time of reading the data, whereas in the structure of the SRAM, when the power is turned off or particularly when the data is stored in the ferroelectric. Only the backup word line (BUWL) is applied with voltage and MOS
By turning on the transistor, transferring the data in the SRAM, and applying a rectangular pulse of 1 pulse to the backup control line (BUCL), the ferroelectric memory capacity (F
Since data is written in C) and the dummy ferroelectric memory capacity (FC upper line), the number of polarization inversions is extremely small, the data retention characteristic is good, and the element reliability is high.
The spontaneous polarization of the ferroelectric film obtained in this example is 50 μm.
Since it is C / cm ² , the capacity area required for reading is about 0.2 μm ² , and therefore the cell area is expanded by about 20% including the MOS transistor for backup to form a highly reliable and high-speed memory. be able to.

Fifth Embodiment FIG. 9 is a sectional structural view of a DRAM memory cell portion using a ferroelectric substance according to a fifth embodiment of the present invention.

10 to 16 are sectional views showing the manufacturing process of the fifth embodiment.

This embodiment is designed by the 0.25 μm rule by the 256 Mbit DRAM technology, the power supply voltage is 1.5 V, the sense amplifier pitch is 0.8 μm, and the word line pitch is 0.7 μm. However, the present invention is not limited to the above design dimensions.

As shown in FIG. 10, the source is on the Si substrate,
N-type doped layer 901 serving as a drain, gate electrode 90
2. SiO ₂ insulating film 90 for gate insulating film, element isolation, etc.
5, bit line 14 made of polysilicon is formed and MOS
A transistor is constructed.

On this, a solid solution film of BaTiO ₃ (barium titanate) and SrTiO _{3 is formed to} a film thickness of 0.3 μm. As a film forming method, ozone is used as an organic metal of Ba, Ti, or Sr or an organic metal complex as a carrier gas, and a substrate temperature is 600 ° C. and an organic metal chemical vapor deposition method is used. As the film forming apparatus, the ECR microwave plasma MOCVD apparatus shown in FIG. 4 can be used.

FIG. 12 shows a sectional view after etching the ferroelectric film in the manufacturing process of the fifth embodiment. Then, the ferroelectric film is etched through a lithography process and processed so as to have the cross section shown in FIG. At that time, it is necessary that the ferroelectric substance on the source contact portion of the MOS transistor be removed and that the ferroelectric substance be processed to have a desired thickness. There is no problem even if the ferroelectric is left on the SiO ₂ on the bit line.

As shown in FIG. 13, a PbTi alloy film 16 is formed.
01 and aluminum 1602 are formed by a sputtering method.

A BPSG1701 film is formed as shown in FIG.

As shown in FIG. 15, etching back is performed until the portion of the aluminum thin film deposited on the ferroelectric is exposed.

As shown in FIG. 13, the exposed aluminum 1901 and the underlying PbTi alloy 1902 are etched and processed into an electrode shape. As a result, the ferroelectric sidewalls are electrically separated from each other to form electrodes, thereby forming a capacitive element. The electrode spacing at that time was 0.2 μm. However, the present invention is not limited to the film thickness of about 0.2 μm, but is determined by the required capacitance value and the specific resistance of the film.

Among the aluminum electrodes, the electrode not connected to the MOS transistor is electrically connected to the electrode common to the other capacitance elements and is used as a plate electrode.

Further, a memory cell is formed by forming a SiO ₂ film on the above capacitive element and using it as a protective film. When it is used as a DRAM, aluminum wiring etc.
1, 910, and 909 are provided, contacts with external electrodes are made, and they are enclosed in a package to complete the DRAM having the circuit configuration shown in FIG. Although the peripheral circuits of the sense amplifier and the driver circuit and their processes are omitted, they are naturally included.

In this embodiment, the capacitance value of the capacitive element is 4
0 fF is obtained. Further, the resistivity when utilizing the side wall portion of the ferroelectric substance is about 10 13 Ωcm, and by setting the electrode interval to 0.2 μm, a leak current value sufficiently small to be used as a DRAM memory cell can be obtained. There is.

According to this embodiment, the occupied area of the memory cell can be reduced to about one third or less as compared with the memory cell structure using the conventional SiO ₂ film as the insulator as shown in FIG. .. On the other hand, when platinum is used as the electrode material, ion milling is required to process the platinum, which makes it difficult to miniaturize. Then, the memory cell area is required to be about 1.5 times. Also, aluminum and poly S
When i is used as an electrode, it has excellent workability, but on the other hand, when the ferroelectric film is formed, the electrode is oxidized to form an aluminum oxide or SiO ₂ film having a low dielectric constant. When the capacitive element is constructed with the film thickness and the electrode area, the capacitance value is reduced to about 1/8 of that of the present embodiment.

FIG. 17 is a perspective view of a DRAM memory cell portion using a ferroelectric substance using the high dielectric substance according to the first embodiment of the present invention.

FIG. 18 is a plan view of FIG.

Ferroelectric films 2002 and 2104 are formed so as to surround the source electrode 2105 of the MOS transistor. As a result, the area of the capacitance using the ferroelectric material can be widened and the height of the capacitance value can be lowered, so that the step difference after the memory cell configuration is small, and the step difference that occurs when the aluminum wiring is arranged in the subsequent process is the cause. It is possible to reduce the number of disconnections of wirings, which can improve the yield of the device.

Example 6 An example of forming a ferroelectric memory using Pb (Zr, Ti) O ₃ as a ferroelectric film and utilizing spontaneous polarization will be described. The structure of the memory is as shown in FIG.

The sol-gel method is used as the method for forming the PbZrTiO ₃ film. An electron beam evaporation method is used for forming the PbTi3 film. According to this embodiment, the workability of the electrode is excellent as compared with the conventional technique using platinum as the base metal, so that the fine processing is excellent and the ferroelectricity is also improved.
Further, the cost of the target required for forming the electrodes is also low, which greatly contributes to high integration, high speed, and low cost of the memory.

In the present embodiment, the example in which the storage element is composed of one set of two elements, one for each of the capacitor and the transistor, has been described, but it goes without saying that another structure using the spontaneous polarization of the ferroelectric substance is used. For the non-volatile memory, the cell area can be reduced and high integration can be achieved. Seventh Embodiment FIG. 19 is a sectional view of a DRAM memory cell according to a seventh embodiment of the present invention.

In this figure, the above PbTi ₄ is used as an electrode, and a capacitor using a ferroelectric material is formed on the top of the control transistor, the peripheral circuit for driving, and the wiring-finished substrate.
A cross-sectional view of a RAM memory cell is shown. The storage node of the capacitive element and the electrode of the MOS transistor are connected by tungsten. Ferroelectrics, like the materials above,
It contains many elements such as heavy metals and magnesium that change the characteristics of semiconductors and insulating films. By forming the ferroelectric film in the final step, long-term reliability of the device can be improved.

According to the evaluation by the test elementary group having the element shown in FIG. 10 and the structure shown in FIG. 19, M
If the off-state current of the OS transistor is as shown in FIG.
It is possible to lower the cycle and lengthen the refresh cycle as compared with the case of.

Further, by generating the metal constituting the ferroelectric material so as to use a substance having a long half-life of α-ray decay, the probability of occurrence of soft error could be lowered.

Example 8 In the examples described above, the metal or ferroelectric film was composed of only one layer, but in this example, ferroelectrics having different compositions are formed on the semiconductor substrate. This is an example in which the first layer is used as a buffer layer with the underlying oxide film to improve the crystallinity of the ferroelectric substance of the second layer and bring out the ferroelectricity.

FIG. 20 shows a sectional view of a memory cell using a multilayer ferroelectric substance and a multilayer electrode of Example 8 of the present invention.
This element is designed according to the rule of 0.3 μm, the power supply voltage is 3.0 V, the sense amplifier pitch is 0.8 μm, and the word line pitch is 0.7 μm. After the MOS transistor and the bit line are formed on the Si substrate as shown in FIG. 1, a contact portion titanium 2701 is formed in order to reduce the contact resistance with silicon. The formed titanium reacts with silicon in the subsequent high temperature process to form titanium silicide 2702 of about 0.02 μm at the boundary with silicon. This titanium silicide further reduces the contact resistance. Further, titanium nitride 2703 to be a barrier layer is formed on the titanium. By forming a barrier material on the contact portion of the source electrode of a MOS transistor before forming a ferroelectric film, a heavy metal such as lead or zirconium contained in the ferroelectric or a substance that can become mobile ions in Si such as magnesium Can be prevented from being mixed into Si. When heavy metals are mixed into Si or mobile ions are mixed therein, energy levels of electrons are formed in a deep energy region in the band gap of Si, which causes an increase in leak current of the MOS transistor and a change in threshold voltage. Titanium nitride 2703 is used as a barrier material capable of preventing these.

Furthermore, SrTiO ₃ 2704 and Pb
(Mg, Nb) O ₃ 2705 are formed to a film thickness of 0.1 and 0.45 μm by the CVD method and the sol-gel method, respectively.

Further, through a photolithography process and a dry etching process, Pb (Mg, Nb) O ₃ 270
5 and SrTiO ₃ 2704 have a width of 0.15 μm and a length of 2
It is formed to have a thickness of μm. At that time, the height of the ferroelectric layer is 0.5 μm and is formed so as to surround the contact portion of the source electrode of the MOS transistor as shown in FIG. Furthermore, PbTi ₂ 2706 was added to 0.04 μm.
m polysilicon 2707 is deposited to a thickness of 0.05 μm. Furthermore, boron phosphorus silicate glass (BPSG) 2708
Is deposited and reflowed at a high temperature of 800 ° C. Furthermore, B
The PSG is etched back until the polysilicon on Pb (Mg, Nb) O ₃ is exposed. BPSG is Pb
It has a high solid solubility with heavy metals such as the like and has a gettering effect.

Further, the polysilicon on the ferroelectric upper portion is removed by etching, and the aluminum on the ferroelectric upper portion is removed by sulfuric acid. As a result, the plate electrode 2709 and the storage node 2710 are electrically separated via the ferroelectric substance. As a result, the area of the electrode in contact with Pb (Mg, Nb) O ₃ is 1 μm ² (2 μm × 0.5 μm), and the electrode interval is 0.15 μm.

Further, as a protective film, S is formed on the capacitance element.
A memory cell is formed by forming the iO ₂ film 2711.
When it is used as a DRAM, aluminum wiring 2712 and the like are further provided thereon to make contact with external electrodes, and then sealed in a package for completion. Although processes of peripheral circuits such as the sense amplifier and the driver circuit are omitted, they are naturally included, and the configuration is as shown in FIG.

In the present embodiment, the capacitance value of the capacitance element was about 80 fF. Since the voltage applied to the plate electrode is 1.5V, which is half the power supply voltage of 3V, the accumulated charge amount is 120 fC. In addition, leak current 1
The value is about fA, which is sufficiently small for use as a DRAM memory cell.

Although Pb (Mg, Nb) O ₃ is described as a substance used in such a DRAM, the present invention is not limited to the above film. For example, BaTi
When O ₃ or SrTiO ₃ or a solid solution film containing these films as a main component is used, the relative dielectric constant is smaller than that of Pb (Mg, Nb) O ₃ , so the device dimensions are different from those described above. High response characteristics can be obtained even in a high frequency region of 100 kHz or higher. This is because the mass of Ba and Sr atoms is smaller than the mass of Pb atoms.
Also, Pb (Ti, Zr) O ₃ and (Pb, La) (T
Since i, Zr) O ₃ does not contain Mg which is a constituent element of Pb (Mg, Nb) O ₃ , it does not cause problems such as Mg diffusion or change in MOS transistor characteristics due to Mg becoming mobile ions. Improves reliability.

Although the sol-gel method is taken up in the above-mentioned embodiments, the above-mentioned film can be formed by a sputtering method, a metal organic chemical vapor deposition method, a vapor deposition method, a hydrothermal method or the like. In the sputtering method, the composition of the film can be formed with good controllability by changing the composition of the target, and (Pb, L
a) Pb (Mg, which is a solid solution of (Ti, Zr) O ₃ and copper
A film having a large number of constituent elements such as Nb) O ₃ can be easily formed. In addition, the organometallic vapor deposition method and hydrothermal method are 1
Simultaneous film formation on 0 or more substrates improves throughput.

Regarding the electrodes, the PbTi alloy has been mainly described, but KNb, NaTa, KTa,
SrTi, BaTi, SrZr, BaZr, BiFe,
NaBiTi, KBiTi, KLaTi, BaPbTi
O ₃ , CaSrTi, NaNdTi, AgCeTi, P
bCaZr, BaMgTe, BaMnTe, BaCoT
e, BaCdTe, PbMgTe, PbMnTe, Pb
CoTe, ZnTe, PbCdTe, PbCoW, Pb
ZrTi, PbMgNb, PbScNb, PbMnN
b, PbFeNb, PbNiNb, PbInNb, Pb
FeW, PbLuTa, PbYbTa, PbCuSb,
A combination of PbAlSb, CaMgTe and CaMnTe is considered.

Next, BaT other than the above PbTi alloy is used.
The i and SrTi alloys will be described.

Example 9 FIG. 21 is a schematic diagram showing a deposited state of an oxide ferroelectric thin film of Example 9 of the present invention. An alloy film 2 of Ba and Ti is formed on the Poly-Si film, and a ferroelectric thin film 3 of BaTiO ₃ is continuously formed on the alloy film 2.

The process of forming the ferroelectric thin film of BaTiO ₃ will be specifically described below with reference to FIG. Using a silicon wafer (diameter 100 mm) as a substrate in the vacuum evaporation system, introduce oxygen gas from the gas blowing pipe at a flow rate of 200 ml / min, adjust the exhaust volume so that the pressure becomes 0.3 Pa, and then use the gas blowing pipe. Monosilane and SiH ₄ were introduced at a flow rate of 20 ml / min to form a Poly-Si layer.

After Ba and Ti are continuously vapor-deposited simultaneously on this to form an alloy film of Ba and Ti, oxygen gas is introduced to form an oxygen-deficient BaTiOn layer, on which a BaTiO ₃ layer is sputtered. Formed by. Argon gas was used as the sputtering gas, and barium and titanium were mixed and sintered at a molar ratio of 1: 1 as the target. The substrate was heated so that the temperature of the substrate was around 600 ° C., and a layer having a perovskite crystal structure was formed with the composition of BaTiO ₃ . 0.2 μm of Ti was deposited as an electrode material on this. The capacity of the BaTiO ₃ film having a film thickness of 5000 Å obtained at this time is 53.1 fF.

FIG. 22 is a schematic diagram showing the state of deposition of an oxide ferroelectric thin film according to the prior art. In this conventional technique, a BaTiO ₃ oxide high dielectric thin film is formed on poly-Si by MOCVD using an organic metal, which is a type of chemical vapor deposition (CVD) method. However, in this case, the Poly-Si crystal surface is immediately oxidized and an insulating layer of SiO ₂ which is a thin oxide film is formed on the surface. Even if a BaTiO ₃ layer which is a ferroelectric film is formed on this, an SiO ₂ insulating layer is formed. The capacity of the _two layers becomes dominant, and the BaTiO ₃ film thickness is 500
The capacitance was 13.3 fF when the SiO ₂ film thickness was 20 Å at 0 Å.

Compared with the conventional method described above, according to the method for forming a ferroelectric thin film of the present invention, the ferroelectric property can be prevented from lowering, and a ferroelectric thin film of BaTiO ₃ composition which does not react with the poly-Si electrode material can be obtained. ..

In this example, the alloy film of Ba and Ti shown in FIG. 21 is also formed by sputtering. Argon gas was used as the sputtering gas and Ba was used as the target.
And Ti were individually sintered. Substrate temperature is 60
It is around 0 ° C.

Further, an alloy film of Ba and Ti can be formed by using the heating vapor deposition method. BaTiO ₃ can also be formed by using the MOCVD method instead of the sputtering method. As the evaporation raw material, β-diketone complex was used for Ba and alkoxide was used for Ti, and nitrogen was used as a carrier gas when the raw material was supplied.

Example 10 FIG. 23 is a schematic diagram showing a deposited state of an oxide ferroelectric thin film of Example 10 of the present invention. An alloy film of Sr and Ti is formed on poly-Si, and a high dielectric thin film of SrTiO ₃ is continuously formed on the alloy film.

A process for forming a high dielectric thin film of SrTiO ₃ will be specifically described. Form a Poly-Si layer in the vacuum evaporation system,
Sr and Ti were simultaneously vapor-deposited on this to form an alloy film of Sr and Ti. After this, oxygen gas was introduced to remove oxygen-deficient SrTiO _n.
Layers were formed. By sputtering is continuously deposited SrTiO ₃ on the layer, after forming the SrTiO ₃ layer, a layer having a perovskite crystal structure by heating the substrate with the composition of SrTiO ₃ such that the front and rear 600 ° C. Formed. As an electrode material on this
Ti was deposited to form a layer.

FIG. 24 is a schematic view showing a deposited state of a high dielectric oxide thin film according to the prior art. This conventional technology is Poly
-The SrTiO ₃ oxide high dielectric thin film is obtained on the -Si crystal substrate by the MOCVD method using an organic metal which is one of the chemical vapor deposition (CVD) methods. However, in this case Poly-Si crystal face is immediately oxidized surface a thin insulating layer of oxide film and a SiO ₂ is produced, SiO ₂ be formed of SrTiO ₃ layer is a high dielectric film on the It has been confirmed that the dielectric constant of the layer becomes dominant, the relative dielectric constant is determined, and the dielectric constant is lowered.

Compared with the above-mentioned conventional method, the method of forming a high dielectric thin film of the present invention can prevent the deterioration of high dielectric property, and a high ferroelectric thin film of SrTiO ₃ composition that does not react with the lower electrode material during formation can be obtained. can get.

As the method of forming the alloy film of Sr and Ti, a sputtering method, a heating vapor deposition method, a CVD method or the like can be used.
As a film forming method of SrTiO _3, a film may be formed by a MOCVD method or the like in addition to the sputtering method.

Example 11 FIG. 25 is a schematic diagram showing a deposited state of an oxide ferroelectric thin film of Example 11 of the present invention.

A process for forming a ferroelectric thin film of BaTiO ₃ will be specifically described. After forming a Poly-Si layer by the CVD method and depositing Ti on this to form the lower electrode, continuously
After Ba and Ti were simultaneously vapor-deposited to form a Ba and Ti alloy film, oxygen gas was introduced to form an oxygen-deficient BaTiOn layer 117, and a BaTiO ₃ layer was formed thereon by sputtering. Argon gas was used as the sputtering gas, and a mixture of Ba and Ti at a molar ratio of 1: 1 was used as the target. The substrate was heated so that the temperature of the substrate was around 600 ° C, and a layer having a composition of BaTiO ₃ and having a perovskite crystal structure 11
Formed 15. On top of this, 0.2 μm of Ti was deposited as an upper electrode to form a layer.

Since BaTiO ₃ which is the ferroelectric film of the present invention utilizes Ti which is a constituent composition as the upper and lower electrodes, it is possible to obtain a ferroelectric thin film capable of preventing the deterioration of the ferroelectric property.

Example 12 FIG. 26 is a schematic diagram showing a deposited state of an oxide high dielectric constant thin film of Example 11 of the present invention.

A process of forming a high dielectric thin film of SrTiO ₃ will be specifically described. Poly-Si layer is formed by CVD method, Ti is vapor-deposited on this, lower electrode is formed, and then continuously.
After Sr and Ti were vapor-deposited at the same time to form an alloy film of Sr and Ti, oxygen gas was introduced to form an oxygen-deficient SrTiOn layer, and an SrTiO ₃ layer 1312 was formed thereon by sputtering.
Argon gas was used as the sputtering gas, and a mixture of Sr and Ti at a molar ratio of 1: 1 was used as the target.
Heat the substrate so that the temperature of the substrate is around 600 ℃, and press the SrT
A layer 1315 having a perovskite crystal structure was formed with a composition of iO ₃ . On this, 0.2 μm of Ti was deposited as an upper electrode to form a layer 1316.

Since SrTiO ₃ which is the high dielectric film of the present invention utilizes Ti which is a composition component as the upper and lower electrodes, a high dielectric thin film capable of preventing deterioration of high dielectric property can be obtained.

Next, examples of applied products using the capacitive element of the present invention will be described.

Embodiment 13 FIG. 27 shows a layout of a system LSI of Embodiment 13 of the present invention. This figure shows a system LSI in which the memory device of the present invention described in the above-described embodiment is integrated on a chip.
In the present embodiment, the communication system will be compatible with analog networks, digital networks, narrowband intelligent service digital networks (N-ISDN), and broadband (B) -ISDN in the future, and high-definition natural moving images can be reproduced. It is a high-integrated high-speed memory compatible with multimedia communication including the above, and a driver-receiver circuit and the like are made on-chip to directly input signals from the communication circuit.

FIG. 28 is a logic LSI of the thirteenth embodiment of the present invention.
Shows the layout of. This figure shows FRAM, DRAM, SR
2 shows a microprocessor incorporating an AM as a cache memory. If the memory device of the present invention is used as a built-in cache memory as in the present embodiment, since it has a large capacity and low power consumption as described above, a logic device having an advanced function is operated with low power consumption. be able to. Furthermore, there is an effect that a microprocessor that is resistant to soft errors can be obtained.

Embodiment 14 FIG. 29 shows a layout of a semiconductor disk substrate of Embodiment 14 of the present invention. As shown in this figure, the FRA of the present invention
If M, DRAM, or SRAM is used as a semiconductor disk substrate, it is extremely advantageous as an inexpensive and large-capacity solid recording medium as described above. In particular, if a FRAM desk is used, since it is non-volatile, there is no need for electrical backup even in the event of a power failure, there is no need to copy the stored contents to another storage medium (eg, magnetic disk, magnetic tape, etc.) as a backup, and it is movable. Since there are no parts, it is strong against impact and has the advantages of extremely low power consumption. Furthermore, there is an effect that a semiconductor disk substrate that is resistant to soft errors can be obtained.

FIG. 30 shows the layout of the memory card of Embodiment 14 of the present invention. The FRAM and SRAM of the present invention can be applied not only to the semiconductor disk substrate but also to the memory card as shown in this figure. In particular, a card using FRAM (FRAM card) has the same application as a conventional floppy disk because it does not need to have a battery for storing data in the card unlike a conventional memory card, and is significantly larger than a floppy disk. There is an advantage that access time can be shortened. Therefore, if a memory card using the FRAM SRAM is used as a replaceable auxiliary storage medium in a small-sized portable computer system below a workstation like a conventional floppy disk, a motor or the like required for rotating the disk can be driven. Since the power supply for the system and the drive is not required, the entire system can be downsized, the power consumption can be reduced, and a large amount of information can be read and written at high speed, so that the processing capability of the entire system is improved.

Embodiment 15 The above logic device (microprocessor), the memory device (FRAM, DRAM, SRAM) according to the present invention, the semiconductor disk substrate according to the present invention, and the memory card according to the present invention are a super computer, a large-sized, general-purpose device. The effect is great when used in small and medium-sized computers and workstations, as well as personal computers, portable computers, laptop computers, and notebook personal computers.

FIG. 31 is an explanatory diagram showing the configuration of a computer system according to the fifteenth embodiment of the present invention. In this figure, as semiconductor disks, DRAM and SRAM disks are used in the same manner as in the prior art, but since they have a large capacity and are inexpensive as compared with the prior art, performance such as processing capacity can be improved. These are especially effective for small and medium-sized models.

Further, the FRAM disk has advantages such as nonvolatility, large capacity, and low power consumption as compared with the conventional semiconductor disk. In particular, since it is non-volatile, it does not require electrical backup, and therefore has the advantage that it does not require a storage battery for power outages as seen in small and medium-sized models and can downsize the entire system. In addition, since it is not necessary to copy the stored contents onto a magnetic disk with a slow access time, it can process a large amount of information faster than conventional systems, thus speeding up the entire system, improving performance, downsizing, and lowering the price. Has the advantage that

Further, from a portable personal computer to a notebook computer, since a magnetic disk is not required, a system structure resistant to vibration can be constructed, and low power consumption enables long-term battery operation. Therefore, it is possible to ensure stable operation even in a moving body or the like, because of widespread use for portable use.

Further, when the above microprocessor is used for the signal processing section and the memory device of the present invention is used for the main storage section,
Since a large amount of information can be accessed at high speed, extremely sophisticated and complicated information processing can be performed in a short time.

Sixteenth Embodiment Further, in the system using the logic element, the memory element, the semiconductor disk, and the memory card of the present invention, in addition to the above computer, an OA such as a word processor and a printer is provided.
There is equipment.

FIG. 32 is an explanatory diagram showing the structure of a word processor according to the sixteenth embodiment of the present invention. FIG. 33 is an explanatory diagram showing the configuration of the printer shown in FIG.

In such OA equipment, as in the above-mentioned small to portable computer system, conventionally,
A magnetic disk system is used as a large-capacity auxiliary storage device, and a floppy disk system is used as a replaceable small-capacity auxiliary storage device. Therefore, for the same reason as described in the above computer system, by using the memory device, the semiconductor disk and the memory card according to the present invention, the speed of the entire system can be increased, and the function can be improved, the size can be reduced, and the size can be reduced. There is an advantage that price and high reliability become easy.

Seventeenth Embodiment FIG. 34 is an explanatory diagram showing the structure of a game computer system according to a seventeenth embodiment of the present invention. By applying the present invention to a game computer, a large-capacity memory can be provided at low cost, so that a game with high content can be easily designed, and its program operates at high speed. This effect is particularly great in a portable game machine.

Embodiment 18 FIG. 35 is an explanatory diagram showing the configuration of an electronic desk calculator according to Embodiment 18 of the present invention.

FIG. 36 is an explanatory diagram showing the structure of the electronic notebook according to the eighteenth embodiment of the present invention.

The electronic desk calculator shown in FIGS. 35 and 36,
The electronic notebook also has the advantages of low power consumption, small size, high speed, high performance, low price, and low power consumption.

[0141]

According to the present invention, as an electrode of a capacitive element using an oxide high dielectric or an oxide ferroelectric, it is composed of two or more kinds of elements and becomes a high dielectric or a ferroelectric when oxidized. By using the material, even if an oxide film is formed between the electrode and the dielectric in the oxidation process for obtaining the above-mentioned dielectric, the oxide film exhibits a high dielectric constant or ferroelectricity, and the capacitance value of the entire capacitance element is high. Since a high capacitance value can be obtained without decreasing the value, the effect of increasing the integration degree of the capacitance element can be obtained.

A capacitor having this high degree of integration is used as a random access memory or a non-volatile memory, and products equipped with these memories can be highly integrated, miniaturized and highly functionalized, and also highly integrated and miniaturized. As a result, the effect of improving the processing speed can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a deposited state of an oxide ferroelectric thin film according to an example of the present invention.

FIG. 2 is a schematic diagram of a capacitive element according to a conventional technique.

FIG. 3 is a phase diagram of a general lead-titanium two-phase alloy.

FIG. 4 General ECR plasma-assisted organometallic CV
It is explanatory drawing which shows the structure of D device.

FIG. 5 is a schematic diagram showing a deposition state of an example of the present invention.

FIG. 6 is a cross-sectional structure diagram of a DRAM memory cell portion according to an embodiment of the present invention.

FIG. 7 is a circuit diagram including the periphery of a general memory cell.

FIG. 8 is a circuit diagram including the periphery of a general nonvolatile memory.

FIG. 9 is a cross-sectional structural view of a DRAM memory cell portion using a ferroelectric substance according to an example of the present invention.

FIG. 10 is a cross-sectional view in the manufacturing process of the example of the present invention.

FIG. 11 is a cross-sectional view in the manufacturing process of the example of the present invention.

FIG. 12 is a cross-sectional view in the manufacturing process of the example of the present invention.

FIG. 13 is a cross-sectional view in the manufacturing process of the example of the present invention.

FIG. 14 is a cross-sectional view in the manufacturing process of the example of the present invention.

FIG. 15 is a cross-sectional view in the manufacturing process of the example of the present invention.

FIG. 16 is a cross-sectional view in the manufacturing process of the example of the present invention.

FIG. 17 is a perspective view of a DRAM memory cell portion using a ferroelectric substance that uses a high dielectric substance according to an example of the present invention.

FIG. 18 is a plan view of FIG.

FIG. 19 is a cross-sectional view of a memory cell of a DRAM according to an embodiment of the present invention.

FIG. 20 is a cross-sectional view of a memory cell using a multilayer ferroelectric substance and a multilayer electrode according to an example of the present invention.

FIG. 21 is a schematic view of a deposited state of an oxide ferroelectric thin film according to an example of the present invention.

FIG. 22 is a schematic diagram of a deposited state of a conventional oxide ferroelectric thin film.

FIG. 23 is a schematic diagram of a deposited state of an oxide ferroelectric thin film according to an example of the present invention.

FIG. 24 is a schematic view of a deposited state of an oxide high dielectric thin film according to a conventional technique.

FIG. 25 is a schematic view of a deposited state of an oxide ferroelectric thin film according to an example of the present invention.

FIG. 26 is a schematic view of a deposited state of an oxide high dielectric thin film of an example of the invention.

FIG. 27 is a layout of the system LSI according to the embodiment of the present invention.

FIG. 28 is a layout of a logic LSI according to an embodiment of the present invention.

FIG. 29 is a layout of a semiconductor disk substrate according to an example of the present invention.

FIG. 30 is a layout of a memory card according to an embodiment of the present invention.

FIG. 31 is an explanatory diagram of a configuration of a computer system according to the embodiment of this invention.

FIG. 32 is an explanatory diagram of a configuration of a word processor according to the embodiment of this invention.

FIG. 33 is an explanatory diagram of a configuration of the printer shown in FIG. 32.

FIG. 34 is an explanatory diagram of a configuration of a game computer system according to an embodiment of the present invention.

FIG. 35 is an explanatory diagram of a configuration of an electronic desk calculator according to an embodiment of the present invention.

FIG. 36 is an explanatory diagram of a configuration of an electronic notebook according to the embodiment of this invention.

FIG. 37 is a diagram illustrating a spontaneous polarization action of a general ferroelectric substance.

FIG. 38 is an explanatory diagram of a capacitive element when a conventional noble metal is used as a base electrode and a ferroelectric is formed on the base electrode.

FIG. 39 is an explanatory diagram of a capacitive element in the case where a conventional aluminum is used as a base electrode and a ferroelectric is formed thereon.

FIG. 40 is a chart showing the relationship between the ferroelectric film thickness and the capacitance of the capacitive element formed with the ferroelectric shown in FIGS. 38 and 39.

[Explanation of symbols]

101 poly-Si 102 BaTiO ₃ 103 PbTi ₄ 104 poly-Si 105 SiO ₂ 106 Si 201 poly-Si 401 substrate 402 vacuum container 403 microwave destructive tube 404 microwave generator 405 magnetic field coil 406 substrate heater 407 Ba (DPM) ₃ 408 Ti (DPM) ₃ 409 Heater 410 Gas flow rate controller 901 n-type diffusion layer 902 Word line 903 Bit line 904 Storage node (poly Si) 905 Local oxide film 906 PbTi ₄ film 907 BaTiO ₃ 908 pre - gate electrode (poly Si) 909 titanium tungsten 910 aluminum 911 titanium tungsten 1001 ferroelectric film 1002 PbTi ₄ film 1003 pre - gate electrode (poly Si) 1101 MOS transistor 1102 capacitive element 1103 Wa Word line 1104 bit lines 1105 sense amplifiers 1106 readout amplifier 1107 write amplifier 1201 word - word line 1202 bit lines 1203 dummy - Strong bit line 1204 dielectric capacitor element 1301 SiO ₂ film 1401 ferroelectric film 1501 ferroelectric after etching Film 1601 PbTi ₄ film 1602 Aluminum 1701 BPSG film 1801 Etched back BPSG film 1901 Poly Si 1902 after processing into electrode shape PbTi ₄ film after processing into electrode shape 2001 Storage node 2002 Ferroelectric film 2003 plate Electrode 2004 Bit line 2005 Word line 2006 n-type diffusion layer 2201 Contact electrode (tungsten) 2701 Titanium 2702 Titanium silicide 2703 Titanium nitride 2704 Strontium titanate Um 2705 PbZrTiO ₃ 2706 PbTi ₄ 2707 Poly Si 2708 BPSG 2709 pre - gate electrode 2710 stress - Gino - de 2711 repatriation insulating film 2712 aluminum wiring 2713 titanium tungsten

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 10

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0060

[Correction method] Change

[Correction content]

FIG. 4 is an explanatory diagram showing the configuration of the ECR plasma assisted organometallic CVD apparatus. A vacuum vessel having a substrate holder 401 installed in the substrate as shown in the figure, microwave waveguide through a quartz microwave introducing window 412 is connected to the vacuum vessel, further microwave generator 403 Is connected to the magnetron.
Microwave electric field of 2.45GHz is introduced to the generated vacuum chamber through the quartz window propagates microwave waveguide is from the magnetron. Although omitted in the drawings, a micro-wave wave <br/> microwave tuner in tube, a microwave propagation detector and the like are provided, in advance tuned electric field direction of the microwave is parallel to the substrate on the substrate Has been done. Also,
Although not shown in the drawing, a substrate loading robot chamber is provided via a vacuum container and a gate valve, and the substrate is loaded into the vacuum container by the substrate transfer robot. Further, the robot chamber is connected to another film forming apparatus or the like through the gate valve, and the substrate can be continuously processed including other processing. The substrate holder 401 is equipped with a heater 406 and the substrate can be set to a maximum of 10
It can be heated up to 00 ° C. Further, a magnetic field coil 405 is installed around the vacuum container so that the direction of magnetic force lines on the substrate is perpendicular to the substrate, and a magnetic flux density of up to 1000 gauss can be generated. Carrier gas cylinder 4 so that an organometallic carrier gas can be introduced into the organometallic source container
The pipe is installed from 11, and the temperature of the pipe can be controlled from room temperature to 300 ° C. The temperature of the organometallic sources 407 and 408 and the organometallic source introducing pipe can also be independently controlled by the heater 409 from room temperature to 300 ° C. The gas is introduced in a direction perpendicular to the substrate and has a large number of introduction holes so that the film can be uniformly formed on the substrate.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0076

[Correction method] Change

[Correction content]

As shown in FIG . 11 , BaTiO 3 is formed on top of this .
₃ (barium titanate) and SrTiO ₃ solid solution film 140
1 is deposited to a film thickness of 0.3 μm. As a film forming method, Ba,
An organometallic chemical vapor deposition method is used in which ozone is used as an organic metal of Ti or Sr or an organometallic complex as a carrier gas and the substrate temperature is 600 ° C. As the film forming apparatus, the ECR microwave plasma MOCVD apparatus shown in FIG. 4 can be used.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0081

[Correction method] Change

[Correction content]

As shown in FIG . 16 , the exposed aluminum 1901 and the PbTi alloy 1902 below it are etched and processed into an electrode shape. As a result, the ferroelectric sidewalls are electrically separated from each other to form electrodes, thereby forming a capacitive element. The electrode spacing at that time was 0.2 μm. However, the present invention is not limited to the film thickness of about 0.2 μm, but is determined by the required capacitance value and the specific resistance of the film.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0084

[Correction method] Change

[Correction content]

In the present embodiment, the capacitance value of the capacitive element is
40 fF is obtained. Further, the resistivity when utilizing the side wall portion of the ferroelectric substance is about 10 ¹³ Ωcm, and by setting the electrode interval to 0.2 μm, a sufficiently small leak current value can be obtained for use as a DRAM memory cell.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0092

[Correction method] Change

[Correction content]

In this figure, PbTi ₄ is used as an electrode as described above, and a capacitor using a ferroelectric is formed on the top of the substrate where the control transistor, the driving peripheral circuit and the wiring are completed.
A cross-sectional view of a RAM memory cell is shown. The storage node of the capacitive element and the electrode of the MOS transistor are made of tungsten .
It is connected by a contact electrode 2201 . Ferroelectrics, like the above materials, contain many elements such as heavy metals and magnesium that change the characteristics of semiconductors and insulating films. By forming the ferroelectric film in the final step, long-term reliability of the device can be improved.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0096

[Correction method] Change

[Correction content]

FIG. 20 shows a sectional view of a memory cell using a multilayer ferroelectric substance and a multilayer electrode of Example 8 of the present invention. This element is designed according to the rule of 0.3 μm, the power supply voltage is 3.0 V, the sense amplifier pitch is 0.8 μm, and the word line pitch is 0.7 μm. After the MOS transistor and the bit line are formed on the Si substrate as shown in FIG. 10 , a contact portion titanium 2701 is formed in order to reduce the contact resistance with silicon.
The formed titanium reacts with silicon in the subsequent high temperature process to form titanium silicide 2702 of about 0.02 μm at the boundary with silicon. This titanium silicide further reduces the contact resistance. Further, titanium nitride 2703 to be a barrier layer is formed on the titanium. By forming a barrier material on the contact portion of the source electrode of a MOS transistor before forming a ferroelectric film, a heavy metal such as lead or zirconium contained in the ferroelectric or a substance that can become mobile ions in Si such as magnesium Can be prevented from being mixed into Si. When heavy metals are mixed into Si or mobile ions are mixed therein, energy levels of electrons are formed in a deep energy region in the band gap of Si, which causes an increase in leak current of the MOS transistor and a change in threshold voltage. Titanium nitride 2703 is used as a barrier material capable of preventing these.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0100

[Correction method] Change

[Correction content]

Further, a SiO ₂ film 2711 is formed as a protective film on the capacitive element to form a memory cell. When it is used as a DRAM, aluminum wiring 2712 and the like are further provided thereon to make contact with external electrodes, and then sealed in a package for completion. Although processes of peripheral circuits such as the sense amplifier and the driver circuit are omitted, they are naturally included, and the configuration is as shown in FIG .

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0107

[Correction method] Change

[Correction content]

A process for forming a BaTiO ₃ ferroelectric thin film will be described below in detail with reference to FIG . Using a silicon wafer (diameter 100 mm) as a substrate in the vacuum evaporation system, introduce oxygen gas from the gas blowing pipe at a flow rate of 200 ml / min, adjust the exhaust volume so that the pressure becomes 0.3 Pa, and then use the gas blowing pipe. Monosilane and SiH ₄ were introduced at a flow rate of 20 ml / min to form a Poly-Si layer.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Name of item to be corrected] 0128

[Correction method] Change

[Correction content]

FIG. 30 shows the layout of the memory card of Embodiment 14 of the present invention. FRAM and SRAM of the present invention
Can be applied not only to the semiconductor disk substrate but also to the memory card shown in this figure. In particular, a card using FRAM (FRAM card) has the same application as a conventional floppy disk because it does not need to have a battery for storing data in the card unlike a conventional memory card, and is significantly larger than a floppy disk. There is an advantage that access time can be shortened. Therefore, if a memory card using the above FRAM or SRAM is used as a replaceable auxiliary storage medium in a small-sized portable computer system below a workstation like a conventional floppy disk, a motor required for rotating the disk, etc. Since the driving system and the driving power source are not required, the entire system can be downsized, the power consumption can be reduced, and a large amount of information can be read and written at high speed, so that the processing capability of the entire system is improved.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0131

[Correction method] Change

[Correction content]

Further, the FRAM disk has advantages such as nonvolatility, large capacity, and low power consumption as compared with the conventional semiconductor disk. In particular, since it is non-volatile, it does not require electrical backup, and therefore has the advantage that it does not require a storage battery for power outages as seen in small and medium-sized models and can downsize the entire system. In addition, since it is not necessary to copy the stored contents onto a magnetic disk with a slow access time, it can process a large amount of information faster than conventional systems, thus speeding up the entire system, improving performance, downsizing, and lowering the price. Has the advantage that Further, from a portable personal computer to a notebook computer, since a magnetic disk is not required, a system configuration that is resistant to vibration can be configured, and low power consumption allows battery operation for a long time. It is possible to ensure stable operation even in a moving body or the like due to the wide range of uses.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Name of item to be corrected] 0133

[Correction method] Change

[Correction content]

Further, if the above microprocessor is used for the signal processing unit and the memory element of the present invention is used for the main storage unit , a large amount of information can be accessed at high speed, and therefore extremely sophisticated and complicated information processing can be performed in a short time. It can be carried out.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0134

[Correction method] Change

[Correction content]

[0134] Example 16 Further, the logic device of the present invention, a memory element and 及 beauty semiconductor disk, the system using a memory card word processor in addition to the computer, there is OA equipment such as a printer.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Explanation of reference numerals] 101 poly-Si 102 BaTiO ₃ 103 PbTi ₄ 104 poly-Si 105 SiO ₂ 106 Si 201 poly-Si 401 substrate 402 vacuum container 403 microwave waveguide 404 microwave generator 405 magnetic field coil 406 substrate heater 407 Ba (DPM) ₃ 408 Ti (DPM) ₃ 409 Heater 410 Gas flow rate controller 901 n-type diffusion layer 902 Word line 903 Bit line 904 Accumulation node (poly Si) 905 Local oxide film 906 PbTi ₄ film 907 BaTiO ₃ 908 pre - gate electrode (poly Si) 909 titanium tungsten 910 aluminum 911 titanium tungsten 1001 ferroelectric film 1002 PbTi ₄ film 1003 pre - gate electrode (poly Si) 1101 MOS transistor 1102 volume containing Child 1103 Word line 1104 Bit line 1105 Sense amplifier 1106 Read amplifier 1107 Write amplifier 1201 Word line 1202 Bit line 1203 Dummy bit line 1204 Ferroelectric capacitor 1301 SiO ₂ film 1401 Ferroelectric film 1501 After etching processing Ferroelectric film 1601 PbTi ₄ film 1602 Aluminum 1701 BPSG film 1801 BPSG film after etching back 1901 Poly Si 1902 after processing into electrode shape PbTi ₄ film after processing into electrode shape 2001 Storage node 2002 Ferroelectric film 2003 plate electrode 2004 bit line 2005 word line 2006 n-type diffusion layer 2201 contact electrode (tungsten) 2701 titanium 2702 titanium silicide 2703 titanium nitride 2704 chi Strontium titanate 2705 PbZrTiO ₃ 2706 PbTi ₄ 2707 Poly-Si 2708 BPSG 2709 Plate electrode 2710 Storage node 2711 SiO ₂ film 2712 Aluminum wiring 2713 Titanium tungsten

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI technical display location // B41J 29/00 8804-2C B41J 29/00 S (72) Inventor Michio Oue Tamura, Fukushima Prefecture Miharu-cho, Gunma Omi 16 Ohira, Hiratachi AIC Co., Ltd. Miharu Factory

Claims (23)

[Claims] 1. In a capacitive element including an oxide dielectric having a dielectric constant of 20 or more or having a history of polarization, and electrodes in contact with both surfaces of the oxide dielectric, at least one electrode having a plurality of elements. The capacitive element, which becomes an insulator having a dielectric constant of 20 or more or an insulator having a history of polarization when oxidized. 2. In a capacitive element comprising a dielectric film formed by oxidation of a plurality of elements and electrodes in contact with both surfaces of the dielectric film, at least one electrode is included in the dielectric film. A capacitive element comprising a plurality of elements. 3. The capacitive element according to claim 2, wherein the dielectric film is a high dielectric film having a relative dielectric constant of 20 or more. 4. The capacitive element according to claim 2, wherein the dielectric film is a ferroelectric film having a history of polarization. 5. The capacitive element according to claim 1, wherein the dielectric is formed by oxidizing at least one electrode. 6. The capacitive element according to claim 1, wherein the oxide dielectric and the electrode are in contact with each other through the oxide of the electrode. 7. The dielectric according to any one of claims 2 to 4, wherein the dielectric and an electrode containing a plurality of elements forming the dielectric are in contact with each other through an oxide of the electrode. The capacitive element according to the claim. 8. The capacitive element according to claim 5, wherein the oxide of the electrode is formed by applying a high temperature heat treatment in an oxygen atmosphere. 9. The capacitive element according to claim 5, wherein the oxide of the electrode is formed by being exposed to plasma containing oxygen. 10. The oxide of the electrode is formed in a process of forming the oxide dielectric.
Alternatively, the capacitive element according to claim 7. 11. The capacitor according to any one of claims 1 to 10, wherein the polarization of the oxide dielectric of the capacitive element has a history, and one electrode is electrically connected to the active element. A non-volatile memory, in which memory cells having a memory function depending on the polarization direction of the oxide insulator are arranged in a matrix on a semiconductor substrate. 12. A dynamic random access memory, wherein one electrode of the capacitive element according to any one of claims 1 to 10 is electrically connected to an active element. .. 13. A semiconductor memory card using the nonvolatile memory according to claim 11. 14. A semiconductor memory card using the dynamic random access memory according to claim 12. 15. A semiconductor disk substrate using the non-volatile memory according to claim 11. 16. A semiconductor disk substrate using the dynamic random access memory according to claim 12. 17. A microprocessor using the non-volatile memory according to claim 11. Description: 18. A microprocessor using the dynamic random access memory according to claim 12. 19. A computer using the non-volatile memory according to claim 11. 20. A computer using the random access memory according to claim 12. 21. A computer using the semiconductor memory card according to claim 13 or 14. 22. A computer using the semiconductor disk substrate according to claim 15 or 16. 23. A computer using the microprocessor according to claim 17 or 18.