JPH0527967B2 - - Google Patents

Info

Publication number
JPH0527967B2
JPH0527967B2 JP60006548A JP654885A JPH0527967B2 JP H0527967 B2 JPH0527967 B2 JP H0527967B2 JP 60006548 A JP60006548 A JP 60006548A JP 654885 A JP654885 A JP 654885A JP H0527967 B2 JPH0527967 B2 JP H0527967B2
Authority
JP
Japan
Prior art keywords
self
bias voltage
cathode electrode
substrate
frequency power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60006548A
Other languages
Japanese (ja)
Other versions
JPS61166028A (en
Inventor
Katsuzo Ukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Anelva Corp
Original Assignee
Anelva Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anelva Corp filed Critical Anelva Corp
Priority to JP654885A priority Critical patent/JPS61166028A/en
Publication of JPS61166028A publication Critical patent/JPS61166028A/en
Publication of JPH0527967B2 publication Critical patent/JPH0527967B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、プラズマ放電を利用して基板にエ
ツチング処理をするドライエツチング装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a dry etching apparatus for etching a substrate using plasma discharge.

(従来の技術) この種の装置として、平行平板型ドライエツチ
ング装置が従来から知られている。
(Prior Art) As this type of apparatus, a parallel plate type dry etching apparatus has been conventionally known.

この平行平板型ドライエツチング装置は、第4
図aに示すように、真空室1内にカソード電極2
とアノード電極3とを対向させる一方、カソード
電極2には高周波電源4を接続するとともに、こ
のカソード電極2に基板5を直接載置するように
している。
This parallel plate type dry etching device has a fourth
As shown in Figure a, a cathode electrode 2 is placed inside the vacuum chamber 1.
and an anode electrode 3 are opposed to each other, while a high frequency power source 4 is connected to the cathode electrode 2, and a substrate 5 is placed directly on the cathode electrode 2.

このようにした真空室1に所定のガスを導入し
て、カソード電極2に高周波電力を印加すると、
両電極2,3間にプラズマが発生する。
When a predetermined gas is introduced into the vacuum chamber 1 and high frequency power is applied to the cathode electrode 2,
Plasma is generated between both electrodes 2 and 3.

このようにプラズマが発生すると、第4図bに
示すように、プラズマのポテンシヤル電圧Vpと、
カソード電極2のセルフバイアス電圧Vsとで電
位差が生じるが、この電位降下(Vp−Vs)でイ
オンが加速されて基板5に照射する。したがつ
て、上記電位差が大きければ大きいほど、換言す
れば、セルフバイアス電圧Vsの絶対値が大きけ
れば大きいほど、基板5に対するイオンの照射エ
ネルギーも大きくなる。
When plasma is generated in this way, as shown in FIG. 4b, the plasma potential voltage Vp and
A potential difference occurs with the self-bias voltage Vs of the cathode electrode 2, and the ions are accelerated by this potential drop (Vp-Vs) and irradiate the substrate 5. Therefore, the greater the potential difference, in other words, the greater the absolute value of the self-bias voltage Vs, the greater the ion irradiation energy to the substrate 5.

このようにイオンエネルギーを大きくすれば、
異方性の強いエツチングが可能になり、その加工
精度も向上することになるが、そのために高周波
電力を大きくすると、こん度は、イオンエネルギ
ーが大きくなりすぎて、基板5を損傷することが
あつた。
By increasing the ion energy in this way,
Etching with strong anisotropy becomes possible and the processing accuracy improves, but if the high frequency power is increased for this purpose, the ion energy will become too large and the substrate 5 may be damaged. Ta.

特に、エツチング作業が一通り終つた後に、細
部についてエツチングするオーバーエツチングの
ときに、このイオン衝撃による損傷が大きくな
り、当該基板5のデバイス特性等を損なうことが
あつた。
Particularly, during over-etching, in which details are etched after the etching process has been completed, the damage caused by the ion bombardment becomes large, and the device characteristics of the substrate 5 are sometimes impaired.

(本発明が解決しようとする問題点) 上記のイオン衝撃を小さくするために、従来は
真空室1内の圧力を高くしたり、高周波電力を小
さくしてセルフバイアス電圧Vsを小さくしたり
していた。
(Problems to be Solved by the Invention) In order to reduce the above-mentioned ion bombardment, conventional methods have been to increase the pressure inside the vacuum chamber 1 or reduce the self-bias voltage Vs by reducing the high-frequency power. Ta.

しかし、真空室1内の圧力を高くしたり、高周
波電力を小さくすると、プラズマの発生が不安定
になり、しかもオーバーエツチング以外のエツチ
ング時に十分なイオンエネルギーが得られなくな
るので、その異方性が弱くなるとともに、加工精
度が落ちる等の問題があつた。
However, if the pressure inside the vacuum chamber 1 is increased or the high-frequency power is decreased, plasma generation becomes unstable, and sufficient ion energy cannot be obtained during etching other than over-etching, resulting in the anisotropy being reduced. As it became weaker, there were problems such as a decrease in processing accuracy.

また、このイオンエネルギーを制御するものと
して、特開昭58−202531号に記載された装置が知
られているが、この装置は、アノード電極に基板
を載置しているために、アノード電極のセルフバ
イアス電圧Vpしか制御できない。そのために、
第4図bに示すように、その電圧の制御範囲が小
さくなる。したがつて、この従来の装置では、イ
オンエネルギーの制御範囲も小さくならざるを得
ないという問題があつた。
Additionally, a device described in Japanese Patent Application Laid-Open No. 58-202531 is known as a device for controlling this ion energy, but since this device places a substrate on the anode electrode, Only the self-bias voltage Vp can be controlled. for that,
As shown in FIG. 4b, the voltage control range becomes smaller. Therefore, this conventional device has a problem in that the control range of ion energy must also be narrowed.

この発明は、異方性の強いエツチング特性を維
持しながら、オーバーエツチング時には当該基板
に対するイオン衝撃が少ないドライエツチング装
置の提供を目的にする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a dry etching apparatus that causes less ion bombardment on the substrate during over-etching while maintaining highly anisotropic etching characteristics.

(問題点を解決するための手段) この発明は、真空室内に、高周波電力を印加す
るカソード電極と、接地された真空室から絶縁さ
れたアノード電極とを備えるとともに、カソード
電極に基板を載置し、アノード電極には、コンダ
クタンス及びキヤパシテイーを可変にした同調回
路を接続する構成にしている。
(Means for Solving the Problems) This invention includes a cathode electrode to which high-frequency power is applied in a vacuum chamber, and an anode electrode insulated from the grounded vacuum chamber, and a substrate is placed on the cathode electrode. However, a tuned circuit with variable conductance and capacitance is connected to the anode electrode.

(本発明の作用) 上記の構成のもとでは、同調回路のコンダクタ
ンスやキヤパシテイー等を調整することによつ
て、両電極の電圧の位相を任意に調整できる。
(Operation of the present invention) With the above configuration, the phase of the voltages of both electrodes can be arbitrarily adjusted by adjusting the conductance, capacitance, etc. of the tuned circuit.

そして、上記位相を180度ずらすと、セルフバ
イアス電圧が最大になり、その位相差をゼロにす
るとセルフバイアス電圧が最少になる。
When the phase is shifted by 180 degrees, the self-bias voltage becomes maximum, and when the phase difference is made zero, the self-bias voltage becomes minimum.

(本発明の効果) この発明の装置によれば、高周波電力が一定で
も、セルフバイアス電圧を任意に調整できるの
で、その使用条件等に応じて最適なセルフバイア
ス電圧を選択できる。
(Effects of the Present Invention) According to the device of the present invention, the self-bias voltage can be arbitrarily adjusted even when the high-frequency power is constant, so that the optimal self-bias voltage can be selected depending on the conditions of use.

したがつて、安定なプラズマを発生させるため
に必要な最小の高周波電力を用いつつ、通常のエ
ツチング時にはセルフバイアス電圧を高くして、
異方性が強く、しかも加工精度の高いエツチング
特性を維持できる。また、オーバーエツチング時
には、セルフバイアス電圧を低くしてイオン衝撃
を少なくできるので、当該基板を損傷したりする
問題も解決できる。
Therefore, while using the minimum high-frequency power necessary to generate stable plasma, the self-bias voltage is increased during normal etching.
It has strong anisotropy and can maintain etching characteristics with high processing accuracy. Furthermore, during over-etching, the self-bias voltage can be lowered to reduce ion bombardment, thereby solving the problem of damage to the substrate.

また、カソード電極に基板を乗せているので、
ポテンシヤル電圧とセルフバイアス電圧とを同時
に制御できるので、その制御範囲を十分に大きく
保つことができる。
Also, since the substrate is placed on the cathode electrode,
Since the potential voltage and the self-bias voltage can be controlled simultaneously, the control range can be kept sufficiently large.

(本発明の実施例) 第1図に示した第1実施例は、真空室11内に
カソード電極12とアノード電極13とを対向さ
せるとともに、これら両電極12,13は絶縁体
14,15で真空室11から絶縁している。
(Embodiment of the present invention) The first embodiment shown in FIG. It is insulated from the vacuum chamber 11.

上記カソード電極12は、高周波整合回路16
を介して高周波電源17に接続し、アノード電極
13を同調回路18に接続している。
The cathode electrode 12 has a high frequency matching circuit 16
The anode electrode 13 is connected to a high frequency power source 17 through a tuning circuit 18 .

この同調回路18は、コイル18aとコンデン
サー18bとを並列に接続するとともに、それら
のコンダクタンス及びキヤパシテイーを可変にし
ている。
This tuning circuit 18 connects a coil 18a and a capacitor 18b in parallel, and makes their conductance and capacitance variable.

さらに、上記真空室11には、流量調整器19
及びカツトバルブ20を有するガス導入路21を
接続する一方、カツトバルブ22及び圧力調整器
23を介して真空ポンプ24にも接続している。
Furthermore, a flow rate regulator 19 is provided in the vacuum chamber 11.
and a gas introduction path 21 having a cut valve 20, and is also connected to a vacuum pump 24 via a cut valve 22 and a pressure regulator 23.

しかして、カソード電極12に基板25を載置
するとともに、カツトバルブ22を開いて真空ポ
ンプ24を駆動して、当該真空室11内を排気す
る。このようにして真空室11内が十分に排気さ
れたら、カツトバルブ20を開き、流量調整器1
9を介して所定のガスを導入する。
Then, the substrate 25 is placed on the cathode electrode 12, the cut valve 22 is opened, the vacuum pump 24 is driven, and the inside of the vacuum chamber 11 is evacuated. When the inside of the vacuum chamber 11 is sufficiently evacuated in this way, the cut valve 20 is opened and the flow rate regulator 1
A predetermined gas is introduced through 9.

そして、圧力調整器23を動作させて真空室1
1内を所定の圧力にするとともに、高周波電源1
7を動作させ、高周波整合回路16を介してカソ
ード電極12に高周波電力を印加する。
Then, by operating the pressure regulator 23, the vacuum chamber 1
1 to a predetermined pressure, and a high frequency power source 1.
7 is operated to apply high frequency power to the cathode electrode 12 via the high frequency matching circuit 16.

このようにカソード電極12に高周波電力を印
加すると、真空室11内にプラズマ放電が生じる
ので、プラズマのポテンシヤル電圧Vpと、カソ
ード電極12のセルフバイアス電圧Vsとで電位
差が生じる。そして、この電位降下(Vp−Vs)
でイオンが加速されて基板25を照射するので、
当該基板25はエツチングされる。
When high-frequency power is applied to the cathode electrode 12 in this manner, a plasma discharge is generated within the vacuum chamber 11, so that a potential difference is generated between the plasma potential voltage Vp and the self-bias voltage Vs of the cathode electrode 12. And this potential drop (Vp−Vs)
Since the ions are accelerated and irradiate the substrate 25,
The substrate 25 is etched.

このとき、アノード電極13に接続した同調回
路18のコイル18aのコンダクタンスとコンデ
ンサー18bのキヤパシテイーとを調整すること
によつて、カソード電極12に接続された高周波
電力に対して、アノード電極13側の位相をずら
すことができる。
At this time, by adjusting the conductance of the coil 18a of the tuned circuit 18 connected to the anode electrode 13 and the capacitance of the capacitor 18b, the phase of the anode electrode 13 side with respect to the high frequency power connected to the cathode electrode 12 is adjusted. can be shifted.

そして、この位相を180度ずらすと、両電極1
2,13間の電位差、換言すれば、上記ポテンシ
ヤル電圧Vpとセルフバイアス電圧Vsとの電位差
(Vp−Vs)が大きくなるので、電極12の表面
に発生するセルフバイアス電圧Vsも相対的に高
くなる。このようにセルフバイアス電圧Vsが高
くなれば、イオン衝撃も大きくなるので、異方性
の強いエツチングができ、しかも、その加工精度
も向上する。
Then, by shifting this phase by 180 degrees, both electrodes 1
Since the potential difference between 2 and 13, in other words, the potential difference (Vp - Vs) between the potential voltage Vp and the self-bias voltage Vs increases, the self-bias voltage Vs generated on the surface of the electrode 12 also becomes relatively high. . As the self-bias voltage Vs increases in this way, the ion bombardment also increases, so that highly anisotropic etching is possible and the processing accuracy is also improved.

また、位相差をゼロにすると電位差(Vp−
Vs)が小さくなるので、セルフバイアス電圧Vs
も相対的に低くなり、それだけイオンの衝撃力も
小さくなる。
Also, when the phase difference is set to zero, the potential difference (Vp−
Vs) becomes smaller, so the self-bias voltage Vs
becomes relatively low, and the impact force of the ions also becomes smaller accordingly.

このように高周波電力が一定でも、上記位相を
調整することで、カソード電極12側のセルフバ
イアス電圧Vsを制御できるので、例えば、安定
なプラズマ放電が可能な範囲で当該高周波電力を
最小に保ちながら、上記セルフバイアス電圧Vs
を最大にすることも可能になる。
Even if the high frequency power is constant in this way, the self-bias voltage Vs on the cathode electrode 12 side can be controlled by adjusting the above-mentioned phase. , above self-bias voltage Vs
It is also possible to maximize.

つまり、最小な高周波電力を用いながら、セル
フバイアス電圧Vsを最大にして、イオン衝撃を
大きくし、異方性の強い加工ができるし、オーバ
ーエツチング時には、上記位相差をゼロにしてセ
ルフバイアス電圧を低くし、イオン衝撃を少なく
できる。
In other words, while using the minimum high-frequency power, the self-bias voltage Vs can be maximized to increase ion bombardment and process with strong anisotropy. During over-etching, the above-mentioned phase difference can be set to zero and the self-bias voltage can be increased. can be lowered to reduce ion bombardment.

なお、カソード電極12に印加された高周波電
力に対して、アノード電極13の位相をずらして
セルフバイアス電圧Vsを制御するということは、
両電極12,13間の放電インピーダンスを制御
して当該セルフバイアス電圧Vsを制御すること
と原理的には同一である。つまり、放電インピー
ダンスを小さくすれば、セルフバイアス電圧が低
くなり、逆に放電インピーダンスを大きくすれ
ば、セルフバイアス電圧が高くなる。
Note that controlling the self-bias voltage Vs by shifting the phase of the anode electrode 13 with respect to the high-frequency power applied to the cathode electrode 12 means that
The principle is the same as controlling the self-bias voltage Vs by controlling the discharge impedance between the electrodes 12 and 13. In other words, if the discharge impedance is decreased, the self-bias voltage will be decreased, and if the discharge impedance is increased, the self-bias voltage will be increased.

第2図に示した第2実施例は、真空室11の外
側にソレノイドコイル26及び27を設けるとと
もに、カソード電極12側では絶縁体14以外に
絶縁体28を設け、この絶縁体28で、カソード
電極12のプラズマ照射面以外の部分を隠蔽する
ようにしいている。
In the second embodiment shown in FIG. 2, solenoid coils 26 and 27 are provided outside the vacuum chamber 11, and an insulator 28 is provided in addition to the insulator 14 on the cathode electrode 12 side. The portion of the electrode 12 other than the plasma irradiation surface is hidden.

そして、上記以外の構成は、上記第1実施例と
同様である。
The configuration other than the above is the same as that of the first embodiment.

しかして、ソレノイドコイル26,27に直流
電力を印加すると、矢印29方向の磁界が発生す
るが、そのために電子は、磁界の影響で擬似サイ
クロイド運動をする。
When DC power is applied to the solenoid coils 26 and 27, a magnetic field in the direction of the arrow 29 is generated, and therefore the electrons undergo pseudo-cycloid motion under the influence of the magnetic field.

このように電子が擬似サイクロイド運動をする
と、そのプラズマが一層高密度化するので、それ
だけ放電インピーダンスを小さくできる。
When the electrons make pseudo-cycloid motion in this way, the plasma becomes even more dense, so the discharge impedance can be reduced accordingly.

このように放電インピーダンスを小さくすれ
ば、カソード電極12側に発生するセルフバイア
ス電圧Vsをさげられるので、イオン衝撃による
基板25の損傷をなくすことができる。
By reducing the discharge impedance in this manner, the self-bias voltage Vs generated on the cathode electrode 12 side can be reduced, so that damage to the substrate 25 due to ion bombardment can be eliminated.

なお、両電極12,13間に発生させる磁界
は、上記のように一方向の磁界だけでなく、交番
磁界でも回転磁界でもよい。特に、交番磁界や回
転磁界の方が、プラズマの高密度化を達成しやす
いので、その効果が一層顕著になる。
Note that the magnetic field generated between both electrodes 12 and 13 may be not only a unidirectional magnetic field as described above, but also an alternating magnetic field or a rotating magnetic field. In particular, an alternating magnetic field or a rotating magnetic field can more easily achieve high plasma density, so the effect is even more pronounced.

第3図に示した第3実施例は、両電極12,1
3に沿つて一対の磁石30,31及び32,33
を設けたもので、より高密度化したプラズマを発
生させることができる。
The third embodiment shown in FIG.
A pair of magnets 30, 31 and 32, 33 along 3
It is possible to generate plasma with higher density.

【図面の簡単な説明】[Brief explanation of drawings]

図面第1図は第1実施例の概略図、第2図は第
2実施例の概略図、第3図は第3実施例の概略
図、第4図aは従来の概略図、第4図bはプラズ
マのポテンシヤル電圧Vpとセルフバイアス電圧
Vsとの関係を示すグラフである。 12…カソード電極、13…アノード電極、1
8…同調回路。
Figure 1 is a schematic diagram of the first embodiment, Figure 2 is a schematic diagram of the second embodiment, Figure 3 is a schematic diagram of the third embodiment, Figure 4a is a conventional schematic diagram, Figure 4 b is the plasma potential voltage Vp and self-bias voltage
It is a graph showing the relationship with Vs. 12... Cathode electrode, 13... Anode electrode, 1
8... Tuned circuit.

Claims (1)

【特許請求の範囲】 1 真空室内に、高周波電力を印加するカソード
電極と、接地された真空室から絶縁されたアノー
ド電極とを備えるとともに、カソード電極には基
板を載置し、アノード電極には、コンダクタンス
及びキヤパシテイーを可変にした同調回路を接続
してなるドライエツチング装置。 2 基板が載置されるカソード電極に沿つて、か
つ両電極間に直交する磁場を発生させる手段を設
けた特許請求の範囲第1項記載のドライエツチン
グ装置。
[Claims] 1. A vacuum chamber is provided with a cathode electrode to which high-frequency power is applied and an anode electrode insulated from the grounded vacuum chamber, a substrate is placed on the cathode electrode, and a substrate is placed on the anode electrode. , a dry etching device connected to a tuned circuit with variable conductance and capacitance. 2. The dry etching apparatus according to claim 1, further comprising means for generating a magnetic field along the cathode electrode on which the substrate is placed and orthogonal between both electrodes.
JP654885A 1985-01-17 1985-01-17 Dry etching equipment Granted JPS61166028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP654885A JPS61166028A (en) 1985-01-17 1985-01-17 Dry etching equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP654885A JPS61166028A (en) 1985-01-17 1985-01-17 Dry etching equipment

Publications (2)

Publication Number Publication Date
JPS61166028A JPS61166028A (en) 1986-07-26
JPH0527967B2 true JPH0527967B2 (en) 1993-04-22

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Application Number Title Priority Date Filing Date
JP654885A Granted JPS61166028A (en) 1985-01-17 1985-01-17 Dry etching equipment

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JP (1) JPS61166028A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040118344A1 (en) 2002-12-20 2004-06-24 Lam Research Corporation System and method for controlling plasma with an adjustable coupling to ground circuit
US20080006205A1 (en) * 2006-07-10 2008-01-10 Douglas Keil Apparatus and Method for Controlling Plasma Potential
US20170213734A9 (en) * 2007-03-30 2017-07-27 Alexei Marakhtanov Multifrequency capacitively coupled plasma etch chamber
US8450635B2 (en) 2007-03-30 2013-05-28 Lam Research Corporation Method and apparatus for inducing DC voltage on wafer-facing electrode
CN108480053B (en) * 2018-02-08 2020-05-05 中国矿业大学 Automatic nonlinear electric field adjusting device for triboelectric separation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5440079A (en) * 1977-09-05 1979-03-28 Fujitsu Ltd Plasma etching method
JPS57181376A (en) * 1981-04-30 1982-11-08 Toshiba Corp Dry etching device
JPS58158929A (en) * 1982-03-17 1983-09-21 Kokusai Electric Co Ltd Plasma generator
JPS58202531A (en) * 1982-05-21 1983-11-25 Hitachi Ltd Reactive sputter etching device
JPS60187025A (en) * 1984-03-07 1985-09-24 Ulvac Corp Self-bias voltage controller in plasma discharge device
JPS61159735A (en) * 1985-01-07 1986-07-19 Hitachi Ltd Method and apparatus for plasma treatment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5440079A (en) * 1977-09-05 1979-03-28 Fujitsu Ltd Plasma etching method
JPS57181376A (en) * 1981-04-30 1982-11-08 Toshiba Corp Dry etching device
JPS58158929A (en) * 1982-03-17 1983-09-21 Kokusai Electric Co Ltd Plasma generator
JPS58202531A (en) * 1982-05-21 1983-11-25 Hitachi Ltd Reactive sputter etching device
JPS60187025A (en) * 1984-03-07 1985-09-24 Ulvac Corp Self-bias voltage controller in plasma discharge device
JPS61159735A (en) * 1985-01-07 1986-07-19 Hitachi Ltd Method and apparatus for plasma treatment

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