JPH05275565A - Manufacture of thin film circuit board - Google Patents

Manufacture of thin film circuit board

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Publication number
JPH05275565A
JPH05275565A JP7101292A JP7101292A JPH05275565A JP H05275565 A JPH05275565 A JP H05275565A JP 7101292 A JP7101292 A JP 7101292A JP 7101292 A JP7101292 A JP 7101292A JP H05275565 A JPH05275565 A JP H05275565A
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Prior art keywords
layer
formed
thin film
solution
electroless
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Granted
Application number
JP7101292A
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Japanese (ja)
Inventor
Kazuo Kondo
和夫 近藤
Original Assignee
Sumitomo Metal Ind Ltd
住友金属工業株式会社
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Abstract

PURPOSE: To prevent generation of blister after multilayer interconnections are formed by forming a thin film on a surface of a ceramic board having through holes by an electroless plating method and then forming a metal film.
CONSTITUTION: Conductors 13 are filled in through holes, and an electroless copper-plated layer 12 is formed on a surface of a ceramic board 11 by using electroless copper plating solution. Then, a Ti layer 16, an Mo layer 17 and a Cu layer 18 are formed, and then an electroless copper plated layer 19 is formed. That is, cavities in the conductors 13 are immersed with the solution to be filled with the solution, and electrolessly plated films 12 are formed. Accordingly, even if it is thereafter electrolessly plated, the porous materials 13 are not immersed with the solution. Thus, generation of blister after multilayer interconnections are formed can be prevented.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は薄膜配線基板の製造方法に関し、より詳細にはIC、LSI等を搭載する薄膜配線基板の製造方法に関する。 The present invention relates to a method for manufacturing a thin film wiring board BACKGROUND OF THE, and more IC, a method for manufacturing a thin film wiring board for mounting the LSI and the like.

【0002】 [0002]

【従来の技術】近年、薄膜配線基板の材料としてセラミックスなどを用いることにより、絶縁性、熱伝導性に優れた半導体集積回路の高密度実装用基板の作製が可能となり、広く実用化されている。 In recent years, by using as the material of the thin film wiring board and ceramics, insulating property, the production of high-density mounting substrate of semiconductor integrated circuit with excellent thermal conductivity is possible, it has been widely put into practical use .

【0003】前記薄膜配線基板の製造方法としては、C As a method for producing the thin film wiring board, C
r、Cu等を用いる方法(特開平3−149896号公報)、Ti、Ni、Cu等を用いる方法(特開平3−1 r, a method using Cu or the like (JP-A-3-149896), Ti, Ni, a method using Cu or the like (JP-A-3-1
08797号公報)、Ti、Mo、Cu等を用いる方法(特開平3−108788号公報)等が開示されている。 08797 JP), Ti, Mo, a method using Cu or the like (JP-A-3-108788) have been disclosed. これらの方法によれば、Cr、Ti、Ni、Mo等の金属薄膜をスッパタリング等の乾式法を用いて形成し、その上層にある程度の厚みを有するCuめっき層を電解めっき法を用いて形成している。 According to these methods, by using Cr, Ti, Ni, a thin metal film of Mo or the like is formed by a dry method such Suppataringu, electrolytic plating of Cu plating layer having a certain thickness thereon formed doing.

【0004】図2はスルーホールが多数形成された基板に例えば特開平3−108788号公報記載の方法を用いて作製された薄膜配線基板を示した断面図である。 [0004] FIG. 2 is a sectional view showing a thin film wiring board fabricated using the method of through-holes in the substrate which is formed a number, for example, Japanese Unexamined 3-108788 JP. 図中21はセラミックス基板を示しており、このセラミックス基板21には多数のスルーホールが形成され、これらスルーホールに導体23が充てんされている。 Figure 21 shows a ceramic substrate, the ceramic substrate 21 is a large number of through holes are formed, the conductor 23 is filled in these through holes. この導体23の上方にはTi・W合金層26、Ti層27、C Ti · W alloy layer 26 is above the conductors 23, Ti layer 27, C
u層28の順で金属薄膜が形成され、さらにCu層28 Metal thin film is formed in the order of u layer 28, further Cu layer 28
の上方には厚みのある電解銅めっき層29が形成されている。 Electroless copper plating layer 29 is formed with a thickness of the upper. 図3は図2における導体23を形成する工程を示した断面図であり、スルーホール30を有するセラミックス基板21の上面に導体ペースト31を塗布する工程(図3(a))と、加圧を行い、スルーホール30部に導体ペースト31を押し込みことにより導体23を形成し、その後セラミックス基板21上の余分な導体ペースト31を取り除く(図3(b))工程とを含んでいる。 Figure 3 is a sectional view showing a step of forming a conductor 23 in FIG. 2, the step of applying the conductive paste 31 on the upper surface of the ceramic substrate 21 having through holes 30 (FIG. 3 (a)), the pressure performed, the conductor 23 is formed by pushing the conductive paste 31 in the through hole 30 parts, then remove excess conductive paste 31 on the ceramic substrate 21 (FIG. 3 (b)) and a step.

【0005】 [0005]

【発明が解決しようとする課題】図3に示した導体23 THE INVENTION Problems to be Solved] conductor 23 shown in FIG. 3
は、上記したようにセラミックス基板21上に塗布された導体ペースト31を加圧してスルーホール30に押し込むことにより形成されるが、導体ペースト31をスルーホール30内に十分に均一に押し込むことは困難で、 Is formed by pressing in the through hole 30 by pressurizing the conductive paste 31 coated on the ceramic substrate 21 as described above, it is difficult to push the conductive paste 31 sufficiently uniformly in the through hole 30 so,
このため導体23は焼成の段階で多孔質なものとなっていた。 Therefore conductor 23 had become a porous at the stage of firing.

【0006】この多孔性の導体23を有するセラミックス基板21上に、薄膜配線を図2に示したように特開平3−108788号公報記載の方法を採用して作製した場合、導体23の上部にTi・W合金層26、Ti層2 [0006] On a ceramic substrate 21 having the porous conductor 23, in the case of manufacturing a thin film wiring by employing a method of JP-A-3-108788 JP As shown in FIG. 2, the upper portion of the conductor 23 Ti · W alloy layer 26, Ti layer 2
7、Cu層28からなる金属薄膜をスパッタリング等の乾式法で形成することとなるが、この乾式法では導体2 7, although the metal thin film made of Cu layer 28 becomes to be formed by a dry method such as sputtering, in this dry method conductors 2
3の表面にのみ形成され、前記多孔質導体23の内部にTi26が充てんされない。 3 of the surface only formed, inside Ti26 of the porous conductor 23 is not filled. その結果、次の電解銅めっき層29を形成する工程において、電解銅めっき液が多孔質導体23に含浸されて残留する。 As a result, in the step of forming the next electrolytic copper plating layer 29, electrolytic copper plating solution remains impregnated in the porous conductor 23. このため多層薄膜配線後、多孔質導体23内に残留した電解めっき液が気化し、薄膜配線を押し上げることがあり、ブリスタを生じるという問題があった。 After Accordingly multilayer thin film wiring, porous conductive electroplating solution is vaporized remaining in the 23, may push up the thin-film wiring, there is a problem that results in a blister.

【0007】本発明はこのような課題に鑑み発明されたものであって、多層配線形成後におけるブリスタの発生を防止することができる薄膜配線基板の製造方法を提供することを目的としている。 [0007] The present invention was invented in view of such problems, and its object is to provide a method of manufacturing a thin film wiring board capable of preventing the occurrence of blisters after forming multilayered wirings.

【0008】 [0008]

【課題を解決するための手段】上記目的を達成するために本発明に係る薄膜配線基板の製造方法は、スルーホールを有するセラミックス基板の表面に無電解めっき法による薄膜を形成し、その後金属膜を形成することを特徴としている。 Method for manufacturing a thin film wiring board according to the present invention in order to achieve the above object, according to an aspect of a thin film is formed by electroless plating on the surface of the ceramic substrate having through holes, then the metal film It is characterized by forming a.

【0009】 [0009]

【作用】本発明の方法によれば、セミックス基板の表面に無電解めっきを施す工程で、スルーホール多孔質導体中の空洞内部にまで無電解めっき液が浸透することとなり、前記空洞部には無電解めっきが充てんされ、無電解めっき膜が形成される。 According to the method of the present invention, in the step of electroless plating on the surface of the Semikkusu substrate, it becomes possible to electroless plating solution to the cavity inside in the through-hole porous conductors to penetrate, the cavity electroless plating is filled, the electroless plating film is formed. 従って、その後電解めっきを施しても電解めっき液が前記多孔質導体中に浸透することがなくなる。 Therefore, it is not possible to subsequently electroplating solution be subjected to electrolytic plating from permeating into the porous conductor.

【0010】 [0010]

【実施例】以下、本発明に係る薄膜配線基板の製造方法の実施例を図面に基づいて説明する。 BRIEF DESCRIPTION OF THE PREFERRED example of a method of manufacturing a thin film wiring board according to the present invention with reference to the drawings. 図1(a)〜 Figure 1 (a) ~
(n)は本実施例に係る薄膜配線基板の製造方法を説明するための各工程における断面図である。 (N) is a sectional view in each step for explaining a method for manufacturing a thin film wiring board according to the present embodiment. まず、直径2 First, a diameter of 2
00μmのスルーホールに導体13が充てんされ、96 Conductor 13 is filled in the through hole of 00μm, 96
%Al 23からなるセラミックス基板11の表面に無電解銅めっき液を用いて無電解銅めっき層12を形成する(図1(a))。 % Al 2 on the surface of the O 3 made of ceramic substrate 11 by using an electroless copper plating solution to form an electroless copper plating layer 12 (Figure 1 (a)). なお、無電解銅めっき液の配合組成は表1に示したとおりである。 Incidentally, the composition of the electroless copper plating solution is as shown in Table 1.

【0011】 [0011]

【表1】 [Table 1]

【0012】この無電解銅めっき層12上からレジスト14aを塗布し、この後プリベークを行なってレジスト14a中の有機溶剤を蒸発させる(図1(b))。 [0012] The electroless copper plating layer 12 resists 14a from above was coated, the organic solvent in the resist 14a is evaporated by performing prebaking after this (Figure 1 (b)).

【0013】次にレジスト14aの上方からマスク15 [0013] Then the mask 15 from above the resist 14a
aをかけ、マスク15a上から露光してマスクパターンをレジスト14a上に転写し(図1(c))、その後レジスト14aを現像して所望パターンのレジスト14a Over a, to transfer the mask pattern on the resist 14a is exposed from the mask 15a (FIG. 1 (c)), the resist 14a of a desired pattern by developing the subsequent resist 14a
のみを選択的に残し、次にポストベークを行なって後、 Only selectively leave, then later subjected to post-baking,
現像により膨潤したレジストを硬化させ、下地との密着性を良くする(図1(d))。 The resist swelled by the developing is cured, to improve the adhesion between the base (FIG. 1 (d)). さらにレジスト14aにより保護されていない部分の無電解銅めっき層12のみを過硫酸アンモニウム溶液を用いてエッチング処理し(図1(e))、次に不要となったレジスト14aを溶かして除去する(図1(f))。 The resist 14a only electroless copper plating layer 12 of the portion that is not protected by the etching process using ammonium persulfate solution (FIG. 1 (e)), it is then removed by dissolving the resist 14a which is no longer necessary (Fig. 1 (f)). セラミックス基板11 Ceramic substrate 11
及び配線パターン上からスパッタリングすることによりTi層16、Mo層17、Cu層18をそれぞれ厚さ0.6μmで形成し(図1(g))、このCu18層上にレジスト14bを塗布し、レジスト14bの上方からマスク15bをかけ、このマスク15b上から露光してマスクパターンをレジスト14b上に転写する(図1 And Ti layer 16, Mo layer 17, Cu layer 18 was formed to a thickness 0.6μm respectively by sputtering from above the wiring pattern (FIG. 1 (g)), the resist 14b is applied to the Cu18 layers on the resist masked 15b from above the 14b, to transfer a mask pattern onto the resist 14b is exposed from the mask 15b (FIG. 1
(h))。 (H)). その後レジスト14bを現像して所望パターンのレジスト14のみを選択的に残し(図1(i))、 Thereafter, the resist 14b developed to selectively leave only the resist 14 having a desired pattern (FIG. 1 (i)),
さらに、レジスト14bにより保護されていない部分に電解銅めっきを施し、電解銅めっき層19を形成する(図1(j))。 Moreover, subjected to electrolytic copper plating to the portion that is not protected by the resist 14b, to form an electrolytic copper plating layer 19 (FIG. 1 (j)). 一旦レジスト14bを除去し(図1 Once the resist 14b is removed (FIG. 1
(k))、さらに電解銅めっき層19及びCu層18上にレジスト14cを塗布し、レジスト14cの上方からマスク15cをかけ、このマスク15c上のパターンを露光によりレジスト14c上に転写し(図1(l))、 (K)), further a resist 14c is applied on the electroless copper plating layer 19 and Cu layer 18, masked 15c from above the resist 14c, to transfer the pattern on the mask 15c on the resist 14c by exposure (Fig. 1 (l)),
その後レジスト14cを現像して電解銅めっき層19のパターンに対応するレジスト14cのみを選択的に残す(図1(m))。 Only then resist 14c of the resist 14c developed to correspond to the pattern of the electroless copper plating layer 19 selectively leave (Fig 1 (m)). さらにレジスト14cにより保護されていない部分の金属薄膜Ti層16、Mo層17、Cu Portions of the metal thin Ti layer 16 that is not protected by the resist 14c, Mo layer 17, Cu
層18にエッチング処理を施し、その後不要となったレジスト14cを除去する(図1(n))。 The etching processing to the layer 18, is removed thereafter resist 14c that has become unnecessary (Fig. 1 (n)).

【0014】上記(a)〜(n)の工程に従って薄膜配線基板を製造した。 [0014] was prepared a thin film wiring board according to the above described process (a) ~ (n).

【0015】また別の実施例ではTi層16、Mo層1 [0015] In another embodiment the Ti layer 16, Mo layer 1
7、Cu層18の代わりに金属薄膜としてCr層、Cu 7, Cr layer as the metal thin film instead of the Cu layer 18, Cu
層をこの順で形成してもよい。 It may form a layer in this order.

【0016】更に別の実施例では金属薄膜としてTi [0016] Ti as further metal thin film in an alternative embodiment
層、Ni層、Cu層をこの順で形成してもよい。 Layer, Ni layer may be formed of Cu layer in this order.

【0017】更に別の実施例では、無電解銅めっき層1 [0017] In yet another embodiment, the electroless copper plating layer 1
2の上に金属薄膜を形成することなく、次に電解銅めっき層19を形成しても良い。 Without forming a metal thin film on the 2, then it may be formed electroless copper plating layer 19.

【0018】表2は上記方法に従って作成した実施例に係る薄膜配線基板と、従来どおりに無電解めっきを施さないで作製した比較例に係る薄膜配線基板とを試料とし、ブリスタ発生の加速試験を行った結果を示したものである。 [0018] Table 2 and the thin film wiring board according to the embodiment was prepared according to the method described above, a thin film wiring board according to the comparative example was produced without subjected to electroless plating, a catalyst sample conventionally, an accelerated test of blister occurrence It shows the result of performing. 評価はスルーホール100個中に発生したブリスタの数を測定することにより行なった。 The evaluation was carried out by measuring the number of blisters that occurred 100 in the through-hole.

【0019】 [0019]

【表2】 [Table 2]

【0020】この表2から明らかなように、試料No. [0020] As can be seen from Table 2, sample No.
1〜10に示す実施例に係る基板では温度が上昇してもほとんどブリスタが発生していないが、他方、試料N Hardly blisters occur even when the temperature increases in the substrate according to the embodiment shown in 10, but on the other hand, the sample N
o. o. 11〜20に示す比較例に係る基板では、温度が上昇するに従ってブリスタが多数発生している。 In the substrate according to the comparative example shown in 11 to 20, the blister is generated number with increasing temperature.

【0021】上記したように、セミックス基板11の表面にあらかじめ無電解銅めっき層12を形成することにより、スルーホール導体13中の空洞の内部に無電解めっき液が浸透し、前記空洞が無電解めっきにより充てんされ、無電解めっき膜が形成される。 [0021] As described above, by forming in advance an electroless copper plating layer 12 on the surface of the Semikkusu substrate 11, an electroless plating solution penetrates into the interior of the cavity in through-hole conductor 13, the cavity electroless filled by plating, electroless plating film is formed. したがって、その後電解銅めっきを施しても該電解銅めっき液が前記多孔質導体13中に浸透することがなくなり、多層配線形成後におけるブリスタの発生を防止することができる。 Thus, then it is not possible to electrolytic copper plating solution be subjected to electrolytic copper plating penetrates into the porous conductor 13, it is possible to prevent the occurrence of blisters after forming multilayered wirings.

【0022】 [0022]

【発明の効果】以上詳述したように本発明に係る多層配線基板の製造工程においては、スルーホールを有するセミックス基板の表面に無電解めっきを施す工程で、スルーホーる導体中の空洞の内部に無電解めっき液が浸透し、前記空洞部が無電解めっきにより充てんされ、無電解めっき膜が形成される。 In the manufacturing process of the multilayer wiring substrate according to the present invention as described in detail above, according to the present invention, in the step of electroless plating on the surface of the Semikkusu substrate having through holes, the interior of the cavity in Suruhoru conductor electroless plating solution penetrates, the cavity is filled by electroless plating, the electroless plating film is formed. したがって、その後電解銅めっきを施しても該電解銅めっき液が前記多孔質導体中に浸透することがなくなり、多層配線形成後におけるブリスタの発生を防止することができる。 Thus, then it is not possible to electrolytic copper plating solution be subjected to electrolytic copper plating penetrates into the porous conductors, it is possible to prevent the occurrence of blisters after forming multilayered wirings.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】(a)〜(n)は本発明に係る薄膜配線基板の製造方法の実施例を説明するための各工程における模式的断面図である。 [1] (a) ~ (n) is a schematic cross-sectional view in each step for explaining an embodiment of a method for manufacturing a thin film wiring board according to the present invention.

【図2】従来の方法により作製された薄膜配線基板を示す断面図である。 2 is a sectional view showing a thin-film wiring substrate manufactured by a conventional method.

【図3】(a)(b)はスルーホールを有する基板に導体を形成する工程を工程順に示した模式的断面図である。 [3] (a) (b) is a schematic sectional view showing a step of forming a conductor on a substrate having a through-hole in the order of steps.

【符号の説明】 DESCRIPTION OF SYMBOLS

11 セラミックス基板 12 無電解銅めっき層 16 Ti層 17 Mo層 18 Cu層 19 電解銅めっき層 11 ceramic substrate 12 the electroless copper plating layer 16 Ti layer 17 Mo layer 18 Cu layer 19 electrolytic copper plating layer

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 スルーホールを有するセミックス基板の表面に無電解めっき法による薄膜を形成し、その後金属膜を形成することを特徴とする薄膜配線基板の製造方法。 1. A thin film was formed by electroless plating on the surface of the Semikkusu substrate having a through hole, the method of manufacturing a thin film wiring board, characterized in that subsequent to forming the metal film.
JP7101292A 1992-03-27 1992-03-27 Manufacture of thin film circuit board Granted JPH05275565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7101292A JPH05275565A (en) 1992-03-27 1992-03-27 Manufacture of thin film circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7101292A JPH05275565A (en) 1992-03-27 1992-03-27 Manufacture of thin film circuit board

Publications (1)

Publication Number Publication Date
JPH05275565A true true JPH05275565A (en) 1993-10-22

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Family Applications (1)

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JP7101292A Granted JPH05275565A (en) 1992-03-27 1992-03-27 Manufacture of thin film circuit board

Country Status (1)

Country Link
JP (1) JPH05275565A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465085B1 (en) 2000-04-04 2002-10-15 Fujitsu Limited Thin film wiring board and method for manufacturing the same, base substrate and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465085B1 (en) 2000-04-04 2002-10-15 Fujitsu Limited Thin film wiring board and method for manufacturing the same, base substrate and method for manufacturing the same

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