JPH05273588A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To suppress the degradation in the picture element holding potential of the active matrix type liquid crystal display device and to improve the opening rate thereof. CONSTITUTION:The liquid crystal display device has a panel structure constituted by holding a liquid crystal layer between a pair of substrates. TFTs, picture element electrodes 8 connected to the respective TFTs and storage capacitors for holding the charges of the picture element electrodes 8 are provided on one quartz substrate 1. A counter electrode is formed on the other substrate and forms liquid crystal capacitors with the individual picture element electrodes 8. The storage capacitors are set at the capacity values of >=4 times and <=10 times the liquid crystal capacitors. The degradation in the picture element holding potential is suppressed within <=10% in the range and the opening rate of >=20% is obtd.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device. More specifically, the present invention relates to the configuration of a storage capacitor used to hold a signal voltage written in a pixel.

[0002]

2. Description of the Related Art The structure of a conventional active matrix type liquid crystal display device will be briefly described with reference to FIG. FIG.
FIG. 3 is an equivalent circuit diagram corresponding to one pixel arranged in a matrix. The pixel has a pixel electrode 101 and a counter electrode 10.
2 has a liquid crystal capacitance CL composed of a liquid crystal layer sandwiched between A storage capacitor CS is connected in parallel to hold an image signal written in the liquid crystal capacitor CL. The storage capacitance CS occupies a part of the pixel area including the liquid crystal capacitance CL, and the pixel aperture ratio is sacrificed by this amount. A pixel switch 104 including a thin film transistor or a TFT is provided to drive the liquid crystal capacitance CL. The drain D of the TFT is connected to the pixel electrode 101, the source S is connected to the signal line, and the gate G is connected to the gate line. Pixel switch 1 in response to a gate signal
04 becomes conductive and writes an image signal in the liquid crystal capacitor CL. At this time, an extra charge is stored in the storage capacitor CS. When the gate signal is released, the pixel switch 104 is turned off and the written image signal is held. An active matrix type liquid crystal display device having a storage capacitor is disclosed in, for example, Japanese Patent Publication No. 1-33833.

[0003]

FIG. 14 shows the relationship between the pixel holding potential and the aperture ratio and the storage capacitor CS. Storage capacity C
The larger S is, the more the influence of leakage can be suppressed, so that the pixel potential can be held at a high level. On the contrary, the smaller the storage capacitance CS is, the lower the ratio occupied in the pixel area is, so that the aperture ratio is increased. Thus, in setting the storage capacity CS, two contradictory factors must be taken into consideration.
However, in reality, the mechanism of the image signal leakage is unknown, and since the image potential is prioritized from the viewpoint of taking a design margin, the storage capacitance CS tends to be large and the aperture ratio is sacrificed. There was an issue or problem. If the pixel aperture ratio is low, a display image having sufficient brightness cannot be obtained.

[0004]

SUMMARY OF THE INVENTION In view of the above-mentioned problems and problems of the conventional technique, an object of the present invention is to set an optimum range of the storage capacity CS. In order to achieve such an object, a plurality of thin film transistors formed on one main surface, a pixel electrode connected to each of the thin film transistors, and a storage capacitor for holding a signal charge of the pixel electrode are provided. An active matrix type liquid crystal display device comprising: a substrate, a substrate having a counter electrode, the other substrate facing the one substrate, and a liquid crystal layer held by the two substrates. A means of setting a capacitance value which is 4 times or more and 10 times or less of the liquid crystal capacity provided between the counter electrodes is provided.

[0005]

By setting the storage capacitance CS to be four times or more the liquid crystal capacitance CL, the decrease in the pixel holding potential can be suppressed to 10% or less. Therefore, practically sufficient display contrast can be obtained in this range. Also, the pixel aperture ratio can be set to 20% or more by setting the storage capacitance CS to be 10 times or less of the liquid crystal capacitance CL. This makes it possible to obtain a practically sufficient display brightness.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic sectional view showing an embodiment of an active matrix type liquid crystal display device according to the present invention, in which one pixel portion is cut out. Note that the counter substrate side is omitted for clarity. Each pixel is composed of a TFT part and a storage capacitor part and is formed on the same quartz substrate 1. The TFT portion has a patterned first polysilicon film 2 and constitutes a semiconductor active layer. A second polysilicon film 4 which is patterned through the gate insulating film 3 is formed on this, and constitutes a gate electrode. The TFT having such a structure is the first made of PSG or the like.
It is covered with an interlayer insulating film 5. TFT on this
The wiring electrode 6 electrically connected to the source region is formed. A second interlayer insulating film 7 made of PSG is further formed on this.
Is covered. A patterned pixel electrode 8 made of ITO or the like is formed on the second interlayer insulating film 7.
It is electrically connected to the drain region of the TFT through the contact hole. Although not shown, a liquid crystal layer is interposed between the pixel electrode 8 and the counter electrode to form a liquid crystal capacitor CL.
The value of the liquid crystal capacitance CL is determined by the area of the pixel electrode 8, the dielectric constant of the liquid crystal layer, and the distance between the facing electrodes.

The storage capacitor portion includes the first polysilicon film 2 and the second polysilicon film 2.
The gate insulating film 3 is sandwiched between the gate insulating film 3 and the polysilicon film 4. That is, the gate insulating film 3 functions as a dielectric film. In this embodiment, a three-layer structure of silicon oxide / silicon nitride / silicon oxide is adopted in order to improve the gate breakdown voltage of the TFT. The value of the storage capacitance CS is determined by the thickness and dielectric constant of the gate insulating film 3 and the area of the patterned polysilicon film. In the present invention, the storage capacitance CS is set to a capacitance value which is 4 times or more and 10 times or less the liquid crystal capacitance CL described above. By setting in this way, the decrease in the holding potential of the pixel electrode 8 can be suppressed to 10% or less, and the pixel aperture ratio can be secured to 20% or more.

The structure shown in FIG. 1 is an embodiment and the present invention is not limited to this. The TFT can be formed using not only a polysilicon film but also an amorphous silicon film. Further, it is not limited to the planar type shown in the drawing, but may be a staggered type. The structure of the storage capacitor is not limited to that shown in the figure. A structure in which a part of the gate line is used for one electrode of the storage capacitor may be used.

The above-mentioned setting of the optimum range of the storage capacitance is based on the analysis result of the mechanism of lowering the pixel holding potential. According to this mechanism analysis, the TFT connected to the pixel electrode
It was found that the parasitic capacitance of was greatly involved. In explaining the analysis results below, first referring to FIG.
The parasitic capacitance of is briefly described. FIG. 2 is a schematic diagram showing a TFT for driving a pixel, and usually has an LDD structure in order to suppress a leak current. That is, N-channel LD
In the DTFT, the drain region D has an N ⁻ low concentration impurity region and an N ⁺ high concentration impurity region. The same applies to the source region S. In the example shown, the TFT has a typical dimension with a channel width W of 3 μm and a channel length L of 5 μm. The low-concentration impurity region N ⁻ is diffused just below the gate G and an overlap occurs.
This lateral diffusion length is about 0.5 μm. Therefore, a parasitic capacitance having a gate insulating film as a dielectric is generated between the gate G and the drain D. This parasitic capacitance CGD is 3 μm ×
It is given by 0.5 μm × Ci. Ci is a capacitance value per unit area and is 5.2 × 10 when a gate insulating film having a three-layer structure of silicon oxide / silicon nitride / silicon oxide and a standard film thickness of about 78 nm is used. ^-8 F / cm
It will be about ² . When this value is substituted for Ci and CGD is calculated, it becomes about 1 fF. Similarly, the parasitic capacitance CGS generated between the gate G and the source S has a value of about 1fF. Also, a parasitic capacitance CSD is generated between the source S and the drain D.

Next, a circuit simulation is performed in consideration of the above-mentioned TFT parasitic capacitance, and the storage capacitance CS
The relationship between the decrease in pixel holding potential and FIG. 3 shows an equivalent circuit used in the simulation. For simplicity, only two pixels are shown. The gate G of the TFT is connected to the gate line, the source S is connected to the signal line, and the drain D is connected to one electrode of the liquid crystal capacitor CL, that is, the pixel electrode and one electrode of the storage capacitor CS. .. Note that the source S and the drain D shown here are provided for convenience and generally AC drive is performed, so that the functions of the two are switched alternately. In this equivalent circuit, the liquid crystal capacitance CL is set to 14fF. The liquid crystal capacity C
A predetermined voltage Vc is applied to the L and the storage capacitor CS from the counter electrode side.
om is applied. Further, gate signals Vg1, Vg2, Vg3 ... Are applied to the gate G of the TFT in a line sequential manner. Further, the image signal Vsig is applied to the source S. These signals were applied under preset conditions to change the storage capacitance CS to simulate the decrease in pixel holding potential. At this time, the parasitic capacitances CGD and CGS of the TFT
These values were set as parameters in order to see the effects of CSD and CSD. For example, the parasitic capacitance is 1fF as calculated earlier.
Is set to.

FIG. 4 is a waveform diagram of each signal used in the circuit simulation. The gate signals Vg1, Vg2, Vg3 ... Applied line-sequentially have a pulse height of 14 V and a pulse width of 63.5 μs. The image signal Vsig is 10.
Although it is an analog signal that fluctuates between 5V and 0.5V,
A constant value of 10.5 V was set in order to measure the amount of decrease in the pixel holding potential. The predetermined voltage Vc applied to the counter electrode
om was set to 6V.

FIG. 5 shows a typical pattern of the change over time of the pixel potential obtained when the above-mentioned line-sequential driving is performed. In response to the gate signal, the TFT becomes conductive and the image signal Vsig of 10.5V level is written in the liquid crystal capacitor. When a time corresponding to the pulse width of the gate signal elapses and the TFT becomes non-conductive, the written pixel potential is held. At this time, the pixel potential drops sharply at the moment when the TFT switches from the conductive state to the non-conductive state. This is due to the parasitic capacitive coupling in the TFT, and hereinafter, the decrease in the holding potential is represented by VC.

FIG. 6 shows the simulation result. This graph is a plot of the pixel potential drop VC when the storage capacitance CS is changed using the parasitic capacitance CGD between the gate and the drain as a parameter. As is clear from the graph, VC largely depends on CGD. For example, CGD
Has a small value of about 1 fF, the pixel potential decrease VC increases as the storage capacitance CS decreases.
This is because the pixel holding potential is drawn to the gate electrode potential by the parasitic capacitance coupling between the gate G and the drain D when the TFT switches from the conducting state to the non-conducting state. It is considered that the same parasitic effect due to the parasitic capacitance coupling also occurs between the gate line and the terminal of the pixel electrode. As is apparent from the graph of FIG. 6, the storage capacitance CS must be larger than about 56 fF in order to suppress the potential drop VC to 10% or less, that is, -0.5 V or less. Since the liquid crystal capacitance CL is set to 14 fF in this simulation, the storage capacitance CS needs to be set to 4 times or more of CL.

FIG. 7 is a graph showing the relationship between the storage capacitance CS and the potential drop VC when the parasitic capacitance CSD between the source and the drain is used as a parameter. Gate/
Unlike the storage capacitance CGD between the drains, the CSD does not have a great influence on the fluctuation of the pixel potential. In particular, C
When SD is a small value of about 1fF, the storage capacity CS
The fluctuation of the pixel potential is not recognized regardless of the value of.

FIG. 8 shows a storage capacitance CGS between the gate and the source.
6 is a graph showing the relationship between the storage capacitance CS and the pixel potential decrease VC when using as a parameter. If the storage capacitance CS decreases regardless of the value of CGS, the pixel potential decreases. Also in this case, the pixel potential drop VC can be suppressed to 10% or less by setting the value of CS to about 50 fF or more.

Next, with reference to FIG. 9, the basis for suppressing the decrease of the pixel holding potential to 10% or less will be briefly described. FIG. 9 is a graph showing the relationship between the liquid crystal drive voltage VLCD and the transmittance T. The central value of the liquid crystal drive voltage is 5 V, and the amplitude of the drive voltage is changed within the range indicated by arrow A to display an image. As is clear from the graph, the liquid crystal transmittance is 0
In order to get closer to, it is necessary to apply a drive voltage in the range indicated by arrow B, which corresponds to the pixel holding potential. When the holding potential decreases, the transmittance increases, light leakage occurs, and the display contrast deteriorates. In order to maintain the normal display image quality, a contrast ratio of 100: 1 is required, and the applied voltage must be kept at 9.5V or higher. In other words,
It is necessary to prevent a voltage drop exceeding 10% of the pixel holding potential of 5V.

In the above description, the lower limit value of the storage capacitance is set in relation to the pixel holding potential. Next, the case of setting the upper limit value of the storage capacitance in relation to the aperture ratio will be described. FIG. 10 shows a pixel model used for setting the upper limit value.
The pixel area is 30 μm × 49 μm, which corresponds to a liquid crystal viewfinder having 100,000 pixels, for example. The area of one pixel is typically divided into three, and a display region X formed of an ITO transparent pixel electrode, a storage capacitor region Y, a contact and a TFT.
And other areas Z including wiring. The pixel aperture ratio is represented by the ratio of the area of the display region X to the total area. The display area X according to the area size of the storage capacitance area Y
The area size of will also change. The following numerical formula 1 was used to express the aperture ratio using the area size of the storage capacitor region Y as a variable.

[0018]

[Equation 1]

In Formula 1, the total area X + Y + Z is 14
It is fixed at 70 μm ² . Since the other regions Z are also fixed, the sum of the area dimensions of the display region X and the storage capacitor region Y is also fixed and is 591 μm ² . When the aperture ratio is calculated based on these relationships, it is given as (591 μm ² −Y) / 1470 μm ² with the area of the storage capacitor region Y as a variable.
Area of the storage capacitor region Y is the proportionality multiplier correlates to the value of the storage capacitor CS is 134μm ² / 70fF. That is,
The 70 fF storage capacitance has an area size of 134 μm ² .

FIG. 11 is a graph showing the relationship shown in Expression 1. When the storage capacitance CS is increased, the aperture ratio decreases linearly. In order to secure an aperture ratio of 20% or more, the storage capacitance CS must be suppressed to 140fF or less. Considering the above-mentioned value of the liquid crystal capacitance CL of 14 fF as a reference, it is necessary to limit the value to 10 times or less.

Finally, the necessity of ensuring an aperture ratio of 20% or more will be described with reference to FIG. Usually, an active matrix type liquid crystal display device illuminates from behind by using a backlight composed of a fluorescent tube or the like. For example, when the liquid crystal display device is used as a viewfinder of a video camera, the backlight is at most 25 because power supply is restricted.
Only illuminance of about 00 NIT can be obtained. In order to obtain sufficient display brightness using such a backlight, the illuminance is 50N
It is necessary to fill the level of IT with light from the liquid crystal viewfinder. Therefore, the lower limit of the aperture ratio is 20%.

[0022]

As described above, according to the present invention, by setting the storage capacity to be 4 times or more and 10 times or less of the liquid crystal capacity, the decrease of the pixel holding potential can be suppressed to 10% or less. A pixel aperture ratio of 20% or more can be secured. This allows
There is an effect that an active matrix type liquid crystal display device having sufficient contrast and brightness at a practical level can be obtained. Since the storage capacitor enough to suppress the intrusion of the sudden signal through the TFT parasitic capacitance is provided, it is possible to effectively prevent the drop of the pixel holding potential. Since the pixel electrode area is not sacrificed by this amount, the aperture ratio can be improved. There is also an effect that the necessary storage capacity can be easily calculated as the definition of pixels becomes higher.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a schematic structural diagram of a TFT having an LDD structure.

FIG. 3 is an equivalent circuit diagram used in the simulation.

FIG. 4 is a waveform diagram of a signal used for simulation.

FIG. 5 is a graph showing changes in pixel potential with time.

FIG. 6 is a graph showing the relationship between the storage capacitance CS and the pixel potential decrease VC.

FIG. 7 is a graph showing the relationship between the storage capacitance CS and the pixel potential drop VC in the same manner.

FIG. 8 is a graph showing a relationship between the storage capacitance CS and the pixel potential decrease VC similarly.

FIG. 9 is a graph showing the relationship between the drive voltage of liquid crystal and the transmittance.

FIG. 10 is a schematic diagram showing an area distribution of one pixel.

FIG. 11 is a graph showing the relationship between the storage capacity CS and the aperture ratio.

FIG. 12 is a schematic diagram showing a backlight illumination structure of a liquid crystal viewfinder.

FIG. 13 is an equivalent circuit diagram of one pixel of a conventional active matrix type liquid crystal display device.

FIG. 14 is a graph showing a relationship between a pixel holding potential, an aperture ratio, and a storage capacitor CS.

[Explanation of symbols]

 1 Quartz Substrate 2 First Polysilicon Film 3 Gate Insulating Film 4 Second Polysilicon Film 8 Pixel Electrode CL Liquid Crystal Capacitance CS Storage Capacitance TFT Thin Film Transistor

Claims (1)

[Claims] 1. One substrate comprising a plurality of thin film transistors formed on one main surface, pixel electrodes connected to each of the thin film transistors, and a storage capacitor for holding an electric charge of the pixel electrodes. A liquid crystal display device comprising: a second substrate having a counter electrode and facing the one substrate, and a liquid crystal layer held by the two substrates, wherein the storage capacitance is the pixel electrode and the counter electrode. A liquid crystal display device, wherein a capacitance value is set to be 4 times or more and 10 times or less of a liquid crystal capacity provided between them.