JPH05267851A - Multilayer printed circuit board - Google Patents

Multilayer printed circuit board

Info

Publication number
JPH05267851A
JPH05267851A JP4064410A JP6441092A JPH05267851A JP H05267851 A JPH05267851 A JP H05267851A JP 4064410 A JP4064410 A JP 4064410A JP 6441092 A JP6441092 A JP 6441092A JP H05267851 A JPH05267851 A JP H05267851A
Authority
JP
Japan
Prior art keywords
pad
hole
lsi
electrically connected
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4064410A
Other languages
Japanese (ja)
Inventor
Makoto Kawamata
誠 河股
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4064410A priority Critical patent/JPH05267851A/en
Publication of JPH05267851A publication Critical patent/JPH05267851A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To eliminate formation of an excess penetrating through hole and to enhance mounting density of a component by providing a non-penetrating through hole in an inspection pad electrically connected to a pad of an LSI in a multilayer printed circuit board in which a surface mounting type LSI is placed. CONSTITUTION:A multilayer printed circuit board 1 has an inspection pad 4 electrically connected to a pad 2 of an LSI, and comprises a non-penetrating through hole 5 in the pad 4. The hole 5 is electrically connected to an inner pattern 6 of the board 1. Incidentally, the hole 5 is provided in the pad 4 electrically connected to the pad 1, and may be electrically connected to a component pad to be placed on an opposite side surface to the placing surface of an LSI. Thus, necessity of providing an excess penetrating through hole land on the board 1 is eliminated, mounting density of the component on the board 1 is improved, and a wiring efficiency is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は多層印刷配線板に関し、
特にLSIのパッドと電気的に接続された検査用パッド
を有する多層印刷配線板に関する。
The present invention relates to a multilayer printed wiring board,
In particular, the present invention relates to a multilayer printed wiring board having an inspection pad electrically connected to an LSI pad.

【0002】[0002]

【従来の技術】近年の電子機器の小型化,高密度化に伴
い、使用されるLSIのパッケージは、表面実装化,リ
ードピッチの狭小化が進んできている。それに伴って、
印刷配線板の接続検査も表面実装型LSIの部分につい
ては、LSIのパッドを検査のポイントにできないた
め、図3に示すように、LSIのパッド2と電気的に接
続された検査用パッド4、または、貫通スルーホールラ
ンド8を設け検査用のパッドとして使用していた。
2. Description of the Related Art With the recent miniaturization and high density of electronic equipment, LSI packages used have been surface-mounted and lead pitches have been narrowed. Along with that,
In the connection inspection of the printed wiring board, the LSI pad cannot be used as the inspection point for the surface-mounted LSI portion. Therefore, as shown in FIG. 3, the inspection pad 4, which is electrically connected to the LSI pad 2, Alternatively, the through-hole land 8 is provided and used as an inspection pad.

【0003】LSIの検査用パッド4を経由するパター
ンを検査用パッドの反対面、もしくは、内層へ接続させ
る場合、図4に示すように、検査用パッド4の反対面に
も貫通スルーホールランド8が形成されてしまうため、
このスルーホールランド8が検査用パッド4の反対面の
部品用パッド7の配置及び配線パターン3形成の妨げと
なっていた。
When the pattern passing through the inspection pad 4 of the LSI is connected to the opposite surface of the inspection pad or the inner layer, as shown in FIG. 4, the through-hole land 8 is also formed on the opposite surface of the inspection pad 4. Will be formed,
The through hole lands 8 hinder the arrangement of the component pads 7 on the opposite surface of the inspection pad 4 and the formation of the wiring pattern 3.

【0004】[0004]

【発明が解決しようとする課題】この従来の多層印刷配
線板では、部品の実装密度やパターン配線密度が高くな
った場合、検査用パッド、または、貫通スルーホールラ
ンドが検査用パッドの反対面の部品用パッド配置及び配
線パターン形成の妨げになり、実装密度と配線効率を劣
化させるという問題があった。
In this conventional multilayer printed wiring board, when the mounting density of the components or the pattern wiring density becomes high, the inspection pad or the through-hole land is on the opposite surface of the inspection pad. There is a problem that it hinders the arrangement of pads for components and the formation of wiring patterns, and deteriorates the mounting density and wiring efficiency.

【0005】本発明の目的は、実装密度と配線効率の高
い多層印刷配線板を提供することにある。
An object of the present invention is to provide a multi-layer printed wiring board having high packaging density and high wiring efficiency.

【0006】[0006]

【課題を解決するための手段】本発明は、表面実装型の
LSIが搭載される多層印刷配線板において、前記LS
Iのパッドと電気的に接続された検査用パッド内に非貫
通スルーホールを設ける。
The present invention provides a multilayer printed wiring board on which a surface mounting type LSI is mounted, wherein the LS
A non-through hole is provided in the inspection pad electrically connected to the I pad.

【0007】[0007]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0008】図1は本発明の第1の実施例の要部断面図
である。
FIG. 1 is a sectional view of the essential portions of the first embodiment of the present invention.

【0009】第1の実施例は、図1に示すように、LS
Iのパッド2と電気的に接続されている検査用パッド4
を有する多層印刷配線板1において、検査用パッド4内
に非貫通スルーホール5を設け、多層印刷配線板1の内
層パターン6との電気的接続をもたせたものである。
In the first embodiment, as shown in FIG.
Inspection pad 4 electrically connected to I pad 2
In the multilayer printed wiring board 1 having the above, non-through through holes 5 are provided in the inspection pad 4 so as to be electrically connected to the inner layer pattern 6 of the multilayer printed wiring board 1.

【0010】図2は本発明の第2の実施例の要部断面図
である。
FIG. 2 is a sectional view of the essential portions of the second embodiment of the present invention.

【0011】第2の実施例は、図2に示すように、検査
用パッド4内に非貫通スルーホール5を設け、LSIの
搭載面と反対側の面に搭載される部品用パッド7との電
気的接続をもたせたものである。
In the second embodiment, as shown in FIG. 2, a non-penetrating through hole 5 is provided in the inspection pad 4, and a component pad 7 mounted on the surface opposite to the mounting surface of the LSI. It has an electrical connection.

【0012】[0012]

【発明の効果】以上説明したように本発明はLSIパッ
ドと電気的に接続されている検査用パッド内に非貫通ス
ルーホールを設けることにより、多層印刷配線板上に余
分な貫通スルーホールランドを設ける必要をなくすこと
ができる。このため、多層印刷配線板上への部品の実装
密度の向上及び配線効率の向上に効果がある。
As described above, according to the present invention, by providing a non-penetrating through hole in the inspection pad electrically connected to the LSI pad, an extra penetrating through hole land is formed on the multilayer printed wiring board. It is possible to eliminate the need to provide. Therefore, it is effective in improving the mounting density of components on the multilayer printed wiring board and in improving the wiring efficiency.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の要部断面図である。FIG. 1 is a cross-sectional view of a main part of a first embodiment of the present invention.

【図2】本発明の第2の実施例の要部断面図である。FIG. 2 is a cross-sectional view of essential parts of a second embodiment of the present invention.

【図3】従来のLSIのパットに接続された検査用パッ
ドの平面図である。
FIG. 3 is a plan view of an inspection pad connected to a pad of a conventional LSI.

【図4】従来の多層印刷配線板の一例の要部断面図であ
る。
FIG. 4 is a cross-sectional view of essential parts of an example of a conventional multilayer printed wiring board.

【符号の説明】[Explanation of symbols]

1 多層印刷配線板 2 パッド 3 配線パターン 4 検査用パッド 5 非貫通スルーホール 6 内層パターン 7 部品用パッド 8 貫通スルーホールランド 1 Multilayer Printed Wiring Board 2 Pad 3 Wiring Pattern 4 Inspection Pad 5 Non-Through Through Hole 6 Inner Layer Pattern 7 Component Pad 8 Through Through Hole Land

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 表面実装型のLSIが搭載される多層印
刷配線板において、前記LSIのパッドと電気的に接続
された検査用パッド内に非貫通スルーホールを設けたこ
とを特徴とする多層印刷配線板。
1. A multilayer printed wiring board on which a surface-mounting type LSI is mounted, wherein a non-through hole is provided in an inspection pad electrically connected to a pad of the LSI. Wiring board.
JP4064410A 1992-03-23 1992-03-23 Multilayer printed circuit board Pending JPH05267851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4064410A JPH05267851A (en) 1992-03-23 1992-03-23 Multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4064410A JPH05267851A (en) 1992-03-23 1992-03-23 Multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPH05267851A true JPH05267851A (en) 1993-10-15

Family

ID=13257507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4064410A Pending JPH05267851A (en) 1992-03-23 1992-03-23 Multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPH05267851A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117135818A (en) * 2023-04-11 2023-11-28 荣耀终端有限公司 Single board, terminal and radio frequency test method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177752A (en) * 1985-01-31 1986-08-09 Mitsubishi Electric Corp Multilayer ceramic substrate
JPH0432297A (en) * 1990-05-29 1992-02-04 Kyocera Corp Multilayer interconnection board and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177752A (en) * 1985-01-31 1986-08-09 Mitsubishi Electric Corp Multilayer ceramic substrate
JPH0432297A (en) * 1990-05-29 1992-02-04 Kyocera Corp Multilayer interconnection board and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117135818A (en) * 2023-04-11 2023-11-28 荣耀终端有限公司 Single board, terminal and radio frequency test method

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Effective date: 19980224