JPH05267559A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enable the manufacture of an element having high function even with one chip and further, enable the multi-item small-quantity production of semiconductor devices by preventing the drop of the yield rate accompanying the increase of the area of a semiconductor chip. CONSTITUTION:After manufacture of a plurality of semiconductor chips 2 and 3, only the superior goods are selected, and the fellow side faces, where atoms are densest, of respective semiconductor substrates 9 are connected so that the element formation faces 4a and 4b may be on a level. Therefore, even if the area of a chip increases, the drop of yield rate can be prevented, so the manufacture of a one-chip element having high function with large area becomes possible. Moreover, multi-item small-quantity production becomes possible by preparing many kinds of semiconductor chips and connecting them, changing the combination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is particularly suitable for constructing a semiconductor device in which a semiconductor substrate has a large area and many functions are formed on one wafer, or a semiconductor device which is manufactured in a small number. The present invention relates to a structure and a manufacturing method of a semiconductor device and a wiring structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art Up to now, there has been a demand for a semiconductor device to have a plurality of functions such as an arithmetic function, a memory function and an input / output function on one chip. However, since the increase in the chip area brings about a significant decrease in yield, it has been dealt with by reducing each function and reducing the occupied area of each function.

For this reason, a method is adopted in which each function is dropped rather than the case of one chip one function.
An example of this is the HD described in Hitachi Microcomputer General User's Guide February 1991 page 121.
401220 An 8-bit single chip microcomputer can be given.

This microcomputer chip has 20
48 bytes ROM, 32 bytes RAM, 256 bytes E
It has various functions such as EPROM, timer, D / A converter, and I / O port. Each function is 8-bit microcomputer HD64180 and 4MDRA.
It is significantly inferior to the system composed of MHM514102 and the like.

A technique for combining a plurality of chips to make one semiconductor device is described in Japanese Patent Application Laid-Open No. 2-184063.

[0006]

In the former technique, in order to prevent an increase in the chip area, each function is configured to be lower than that in the case of one chip and one function, so that it is not suitable when a high function is required. Met.

In the latter technique, a gap is always formed between the chips, so that the gap is filled with resin, and therefore it cannot be applied to a high temperature process. The reason for forming this gap is that the chips obtained by etching each chip by isotropic etching are combined.

An object of the present invention is to provide a semiconductor device in which a plurality of functions are formed on one chip, and each function is not inferior to the case where one chip has one function.

It is another object of the present invention to provide a semiconductor device which can be manufactured at a low cost without lowering its function in response to a demand for manufacturing a semiconductor device at a low cost even when the production amount is small.

A further object of the present invention is to provide a semiconductor device which can be applied to a high temperature process even if it is composed of a plurality of chips.

[0011]

A semiconductor device according to the present invention comprises a plurality of semiconductor chips each having a semiconductor element forming portion on the surface of a semiconductor substrate and arranged so that each element forming portion is on the same surface side. With any of the features of.

(1) The semiconductor chips are combined into one so that the side surfaces thereof come into surface contact with each other.

(2) The side surfaces having the same inclination angle are surface-connected to form one sheet.

(3) The side faces of the same crystal plane are connected to each other to form one sheet.

(4) The semiconductor chips are combined so that the side surfaces thereof come into surface contact with each other to form one sheet, and the backing plate is arranged on the back side of the element forming portion.

(5) In (3), the crystal plane on the side surface is a {111} plane.

(6) (4) The back side of the element forming portion and the backing plate are bonded with an adhesive.

(7) Side surfaces of a plurality of types of semiconductor chips are brought into surface contact with each other, and the semiconductor chips have a central arithmetic processing function, a memory function, and an arithmetic function.
These semiconductor chips are selected from the group consisting of those having a light-receiving element, those having a light-emitting element, those having a sensor function, those that merely serve as electric signal transmission means between chips, and those that have a movable part. Combine and make one.

(8) A plurality of semiconductor chips are combined so that their side surfaces are in surface contact with each other, and the atoms of the semiconductor material on the contact surfaces are directly bonded or bonded via oxygen atoms.

The method for manufacturing a semiconductor device of the present invention is characterized by any of the following.

(9) A plurality of semiconductor chips having the semiconductor substrate surface as a semiconductor element forming portion are arranged such that the element forming portions are on the same surface side and the opposing joint surfaces are parallel to each other, Combine to make one sheet.

(10) The side surface of the semiconductor chip having the semiconductor substrate surface as a semiconductor element forming portion is anisotropically etched, and the plurality of semiconductor chips are connected to each other by aligning the etching-processed surfaces of the semiconductor chip.

(11) In (10), the etching liquid for the etching treatment is KOH, NaOH, CsOH,
It contains an alkaline solution such as NH ₄ OH or the like, an organic solution such as ethylenediamine, hydrazine or choline, or a quaternary ammonium aqueous solution such as tetramethylammonium hydroxide or tetraethylammonium hydroxide.

(12) A plurality of semiconductor chips having the semiconductor substrate surface as the semiconductor element forming portion are assembled so that the element forming portions are on the same surface side, and the bonding of the connecting surfaces is 400
Pressure bonding at a temperature of ℃ or more.

(13) In any one of (9) to (12), a conductive film is formed so as to straddle the edge of the semiconductor chip and the edge of another semiconductor chip in contact with the edge. The film is divided and cut by any one of a laser, an ion beam, a plasma, and an electron beam depending on a connection mode of wiring.

(14) In any one of (9) to (12), the position of the wiring in each semiconductor chip to be connected is recognized, and the laser light of the laser CVD apparatus is recognized so as not to interfere with other wiring. Determine the irradiation path of.

(15) In any one of (9) to (12), the arrangement or the order of the wirings for connecting the plurality of semiconductor chips to each other is unified (standardized) over all the plurality of semiconductor chips. To do.

[0028]

In the present invention, element chips are manufactured with a size smaller than the conventional chip size, good products are selected, and then the semiconductor substrates of the element chips are connected so that the element formation surfaces are in the same plane. .. As a result, a semiconductor device can be manufactured within the conventional yield range.

Further, by manufacturing several kinds of element chips and changing the combination according to the customer's request, it is possible to carry out a small quantity production of a wide variety of products.

Here, the element chip is a semiconductor chip that is a constituent element of the semiconductor device according to the present invention, and is composed of a combination of a semiconductor substrate and an element formation surface. This is a concept including both the case where the surface layer itself of the semiconductor substrate is formed so as to share the semiconductor element function, the case where a semiconductor element functional portion is separately formed on the surface of the semiconductor substrate, and the case where both of these are included. ..

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and manufacturing method of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, 4, and 5. FIG. 2 is a flow chart of the manufacturing process.

First, as shown in FIG. 1, a CPU (central processing unit; hereinafter the same) chip 2 and a memory circuit having 5, 5a, 6 and 6a which are wirings to be connected to other chips at the ends thereof. The memory chip 3 having parts is formed on each wafer 18 by a known semiconductor manufacturing process configured by photolithography technology, film formation technology, etching technology, etc. (steps F1 and F4 in FIG. 2).

Thereafter, as shown in FIG. 3, the CPU chip 2
Element chip 17 such as memory chip 3 or wafer 18
By anisotropic etching (step F in FIG. 2)
2, F5).

During this etching, the element formation surface 4 (4
a, 4b) is not attacked, only S is formed on the element formation surface 4.
An etching mask of iO ₂ , Si ₃ N _4, etc. is formed.

The etching has a strong anisotropy, and at the time of etching, the closest packed surface of atoms of the semiconductor substrate 9, that is, {111}.
((111), (11-1), (1-11) (-11
1) (1-1-1) (-11-1) (-1-11) (-
1-1-1). same as below. ) A surface appears, for example, an alkaline solution containing KOH, NaOH, CsOH, NH ₄ OH, etc., or ethylenediamine, hydrazine, choline, etc., or a quaternary ammonium hydroxide aqueous solution such as tetramethylammonium hydroxide, tetraethylammonium hydroxide, etc. It is desirable to use an organic solution containing the above.

At this time, for example, if the element formation surface is {10
0}, and assuming that the long side of each element chip 17 is <110>, the {100} face of the side surface is also etched, so that the obtained element chip 17 has a corner as shown in FIG. It becomes a shape like.

However, this shape can be controlled to some extent by preparing an etching mask in consideration of the amount of corners that can be taken.

In order to contact the outer surfaces of the CPU chip 2 and the memory chip 3 later to form the semiconductor device 1, one chip is formed such that the element forming surface 4 is larger in area than the back surface thereof. The other chip is the element formation surface 4
Must be formed so that the area is smaller than the back surface.

For this purpose, one chip is formed on the element forming surface 4
It is desirable that the etching be performed from the side of the other side and that of the other chip be performed from the back surface of the element forming surface.

By using highly anisotropic etching for the formation of the outer surface of the element chip 17, the densest surface of atoms appears neatly. Therefore, when these are brought into contact with each other to form the semiconductor device 1. Also, it is possible to minimize gaps due to unevenness on the connection surface and to minimize the positional deviation between the element chips.

In the semiconductor device thus obtained, a plurality of semiconductor chips are arranged such that the element forming portions are on the same surface side, and the side surfaces of the facing semiconductor chips are arranged in parallel to each other and joined. Thus, the side surfaces having the same inclination angle are combined so as to be in surface contact with each other.

The inclination angle (angle of the acute angle portion) of each chip obtained by anisotropic etching is constant depending on the semiconductor material, and is 54.74 ° in the case of Si, for example. Anisotropic etching has the highest atomic density of Si crystals {111}
The etching rate for a surface is other surface (eg (100)
It utilizes that it is much slower than the (surface). The semiconductor material is required to be a material capable of this anisotropic etching, and in addition to Si, Ge and GaAs also correspond to this.

The anisotropic etching can be accurately performed by controlling the concentration of the etching solution and the etching temperature. For example, in the case of Si, an etch rate of 0.2 μm / min is obtained with a 50 ° C. etching solution of a 44 wt% potassium hydroxide aqueous solution.

Next, the function of each chip is checked, and the defective one of the CPU chip 2 and the memory chip 3 is removed.

Then, only non-defective products are selected (step F in FIG. 2).
3, F6), as shown in FIG. 4, the CPU chip 2 and the memory chip 3 having a memory circuit portion are arranged so that the respective element formation surfaces 4a and 4b are in the vicinity of the same plane.
At this time, the atom closest surfaces ({111} planes) of the semiconductor substrate of the CPU chip 2 and the memory chip 3 having the memory circuit portion are brought into contact with each other (step F7 in FIG. 2).

By arranging the element forming surfaces 4a and 4b so as to be on the same plane as described above, 5 and 6 and 5a are respectively formed.
The distance of the connection wiring 8 connecting between and 6a becomes the shortest. Also, 1
It can be handled as one chip, and handling becomes easier. In this way, the wiring between the CPU chip 2 and the memory chip 3 is performed (step F8 in FIG. 2).

At this time, 400 in an oxidizing atmosphere.
By crimping the contact surfaces at a temperature above ℃,
The contact surfaces can also be glued. By this bonding process, the atoms on the bonding surface of the CPU chip 2 and the atoms on the bonding surface of the memory chip 3 are bonded to each other through oxygen atoms. Or 80
In a high temperature range such as 0 ° C. or higher, the atoms on the bonding surface of the CPU chip 2 and the bonding surface of the memory chip 3 are directly bonded to each other.

Next, as shown in FIG. 5, conductivity is provided so as to cover both the wiring 5 of the CPU chip 2 and the wiring 6 of the memory chip 3 at the ends of the CPU chip 2 and the memory chip 3 having the memory circuit portion. The film 7 is formed.

Further, as shown in FIG. 1, the laser 5 is provided so that the wiring 5 of the CPU chip 2 and the wiring 6 of the memory chip 3 to be connected to this wiring can be connected and can be insulated and separated from the other wirings 5a and 6a. The film 7 can be partially burned off by using the method to form the connection wiring 8. At this time, the laser output is optimized so that the semiconductor substrate 9 is not left with damage such as crystal defects due to the heat of the laser.

When selecting the laser irradiation path, CP
It is necessary to recognize the positional relationship between the wirings 5 and 5a of the U chip 2 and the wirings 6 and 6a of the memory chip 3.
For this, recognition by human eyes may be used, or automatic image recognition technology may be used. For example, when connecting the wiring 5 of the CPU chip 2 and the wiring 6 of the memory chip 3 as shown in FIG. 1, after confirming the respective positions, the other wiring 5
The laser irradiation path is determined so as to be insulated from a and 6a.

In addition to the laser, a focused ion beam, plasma,
It is also possible to use an electron beam or the like.

In the first embodiment of the present invention, CP
U chip 2 and memory chip 3 are manufactured separately,
Since it is possible to perform wiring and connection after removing defective products, the semiconductor device 1 having a large chip area can be obtained without lowering the yield.

Therefore, even if a plurality of functions are configured on one chip, it is possible to configure each function without degrading the functions as compared with the case of one chip one function.

Further, by manufacturing chips respectively having different functions of the CPU chip 2 and memory capacities of the memory chips 3, semiconductor devices having various functions and memory capacities can be produced by combining these chips. In other words, high-mix low-volume production becomes possible.

A second embodiment of the present invention is shown in FIG. In this embodiment, the laser CVD method is used to form the connection wiring 8.

After recognizing the positional relationship between the wiring 5 of the CPU chip 2 and the wiring 6 of the memory chip 3, the irradiation path of the laser is selected, and the laser beam is irradiated in the source gas of the laser CVD according to this irradiation path. Then, the gaseous molecules of the source gas are decomposed by the energy of the laser light, and the released atoms (molecules) can be deposited according to the laser irradiation region, that is, the laser irradiation path. As the excitation energy source, an ion beam or an electron beam may be used instead of the laser.

As an example, FIG. 7 shows a schematic view of a film forming apparatus using the laser CVD method. In the case of forming fine wiring, the structure shown in FIG. 7 is desirable, but the structure shown in FIG. 8 may be used. This laser CVD apparatus includes a raw material gas cylinder 20, a mirror 21, and a laser oscillator 2.
2, chamber 23, objective lens 24, movable stage 2
5 and the stage controller 26.

The laser light emitted from the laser oscillator 22 is reflected by the mirror 21 and condensed by the objective lens 24, then introduced into the chamber 23 and irradiated onto the semiconductor device 1 on the movable stage 25. The movable stage 25 is controlled by a stage controller 26 and can irradiate a laser on any place of the semiconductor device. A raw material gas is introduced from the raw material gas cylinder 20 into the chamber 23.

Materials that can be used to form the connection wiring 8 using this laser CVD method are copper, gold, zinc, cadmium, aluminum, gallium, indium, titanium, chromium, molybdenum, tungsten, nickel, platinum, and carbon. , Silicon, germanium, tin, etc. have been confirmed.

In this embodiment using the laser CVD method, as in the first embodiment, the CPU chip 2 and the memory chip 3 can be separately manufactured, and defective products can be removed before wiring and bonding. Therefore, the semiconductor device 1 having a large chip area can be obtained without lowering the yield.

Therefore, even if a plurality of functions are configured on one chip, it is possible to configure each function without degrading the function as compared with the case of one function for one chip. Further, even when a step is formed between the CPU chip 2 and the memory chip 3, the connection wiring 8 can be surely formed in the step by scanning the laser along the step. That is, the wiring can be reliably formed on the silicon substrate other than the element formation surface.

The structure of the third embodiment of the present invention is shown in FIG.
In this embodiment, the CPU chip 2 and the memory chip 3 are placed on and bonded to a backing plate, that is, a base 10 made of the same material as the semiconductor substrate 9. This manufacturing method is shown below.

First, as shown in FIG. 3, the CPU chip 2 having the wirings 5, 5a, 6, 6a to be connected to the ends thereof.
And the memory chip 3 are separated from the wafer.

Next, after arranging the non-defective products on the base 10, the CPU chip 2, the memory chip 3 and the base 1 are arranged.
While keeping 0 in close contact with each other, heating is performed to 400 ° C. or higher, and the CPU chip 2, the memory chip 3 and the base 10 are pressure bonded.
In this case, the base 10 is preferably made of the same material as each of the element chips so that an excessive thermal stress does not act between the base 10 and each of the element chips, and it is more preferable that the respective crystal axes are substantially the same.

After that, wiring as shown in the first and second embodiments is performed.

An adhesive may be used to bond the chips 2 and 3 to the base 10.

In the third embodiment of the present invention, each chip is adhered on the base 10, so that the mechanical strength is excellent and the handling is easy.

A fourth embodiment of the present invention is shown in FIGS. In this embodiment, the arrangement of wirings such as 5, 6, 5a, 6a connected to the connection wiring 8 arranged at the beginning of each element chip is standardized. Further, FIG. 11 shows an example of wiring arrangement in this embodiment.

In the present embodiment, the data bus 27, the address bus 28, and the control signal 29 are standardized in this order, but a larger number of wirings may be standardized according to the application.

In each element chip, (1) one in which the element forming surface 4 is formed to have a larger area than its back surface, and (2) one in which the element forming surface 4 is formed to have a smaller area than its back surface However, the wiring of both should be reversed. In this way, by connecting according to the shape of the outer surface of each element chip, it is possible to correspond each wiring without error. The data bus 27, the address bus 28, and the control signal 29 are formed separately for the sake of standardization. Therefore, there are lines that contribute to the connection and lines that do not.

In the present embodiment, the data bus 27, the address bus 28, and the control signal 29 such as the clock are arranged according to the standard, so that the connection wirings 8 may cross each other even when wiring between the element chips. Therefore, information can be transmitted between each element chip without error.

Further, according to the present embodiment, any element chips can be connected to each other without paying attention to the wiring order, so that an efficient wiring work can be performed.

FIG. 12 shows the fifth embodiment of the present invention. This embodiment is an example in which, in addition to the CPU chip 2 and the memory chip 3, element chips such as the input / output control chip 11, the laser oscillation chip 13, and the light receiving chip 14 are connected.

Conventionally, wiring is performed for each packaged element, so that a large number of portions are required for wiring, resulting in a large structure as a whole. Also,
The delay due to this wiring and the delay due to the amplifier that drives the bus cannot be avoided.

According to the present invention, the element chips can be connected to each other so that the element forming surfaces 4a and 4b are in the same plane to form one chip, so that the size and the speed can be reduced. Further, by changing the combination of the element chips in various ways, it is possible to inexpensively produce a semiconductor device that meets the customer's request.

The laser oscillator chip 13 is a laser diode.
It forms a terminal, a serial output port, and a decoder. The light receiving chip 14 forms a photodiode, a serial input port, and a decoder. Light receiving chip 14
The light is input to the photo diode and the light is output from the laser diode of one of the laser oscillation chips 13.

FIG. 14 shows a sixth embodiment of the present invention in which a highly functional intelligent sensor is constructed by combining the CPU chip 2, the memory chip 3, the input / output control chip 11 and the sensor chip 12.

The CPU chip 2 and the memory chip 3 are as described in the above embodiments, and the memory chip 3 includes a memory and a decoder. The input / output control chip 11 includes an external connection terminal, an input / output port, and a decoder.
The sensor chip 12 includes an A / D converter, a decoder, and a sensor. Reference numerals 8 and 16 are wirings for connecting the chips.

After converting the signal detected in the sensor chip 12 into a digital signal, the CPU is connected via the data bus.
Send to chip 2. The CPU chip 2 processes this according to the program previously input to the memory chip 3,
External information can be input / output through the input / output control chip 11.

Conventionally, since the manufacturing method of a sensor chip such as a pressure sensor is different from that of a highly integrated semiconductor chip, it is difficult to manufacture the sensor chip and the highly integrated semiconductor chip on the same chip. However, in this embodiment, the sensor chip and the highly integrated semiconductor are separately manufactured, and the element forming surfaces 4a and 4b, which are not shown in FIG. 14, are arranged and wired so as to be on the same surface to form one chip. It becomes possible to handle.

Further, FIG. 15 shows a seventh embodiment of the present invention. Although this embodiment comprises a CPU chip 2 and a memory chip 3, an address signal decoder is incorporated in the CPU chip 2 to eliminate the bus buffer between the CPU and the memory.

In the present invention, unlike the case where the wiring is pulled out to the outside of the chip, the current required for driving can be reduced because it is the wiring within one chip, so the buffer can be omitted, and between the CPU and the memory. The information transmission speed can be increased.

The eighth embodiment of the present invention is shown in FIG. In this embodiment, each element chip is connected via a wiring dedicated chip 15. Therefore, like the CPU chip 2 and the memory chip 3, even when a number of element chips are connected in parallel to one element chip, wiring can be efficiently performed.

The wiring dedicated chip 15 is used for the data bus 2
7, the address bus 28, and the function of branching the wiring of the control signal 29 such as the clock, for example, the CPU chip 2
It is particularly effective when connecting the wiring such as the data bus 27 to the many memory chips 3.

FIGS. 17 and 18 show one unit therein as an example of a computer having a conventional multi-CPU system. In this system, since a long wire is provided between the CPU chip and the memory chip or between the CPU chip and another chip by using a lead wire, a buffer is required between the chips.

However, if a part or all of this unit is made into one chip according to the present invention, the wiring for connecting each unit is made on one chip, so that the wiring can be shortened and the buffer can be omitted. Therefore, it is possible to prevent a decrease in information transmission speed due to the length of wiring and the presence of the buffer.

In particular, in FIGS. 17 and 18, the portion surrounded by the broken line, that is, the portion of the CPU and the main memory has a large number of signal exchanges. Therefore, if this is made into one chip, it is particularly effective for speeding up.

In the example of FIG. 17, the CPU chip and the chip of the main memory system are joined to form one semiconductor device. In the example of FIG. 18, in addition to these, NDP (numerical operation processing device) and DCP ( The data control processing device) is joined to form one semiconductor device. These elements are particularly effective for speeding up because they frequently exchange signals.

A ninth embodiment of the present invention is shown in FIGS. In this embodiment, the actuator chip 30, the CPU chip 2, the memory chip 3, and the input / output chip 11 manufactured by using the micromachining technology are integrated into one chip by using the present invention. The actuator chip 30 includes a decoder, an actuator, an actuator drive unit, and a D / A converter. Figure 20 is an actuator
It is a perspective view of a tip.

Since a device having an actuator function, that is, a device having a movable part, is not compatible with other semiconductor manufacturing processes and a process which deteriorates the performance of a highly integrated semiconductor device may be used, the actuator may be used. It is difficult to form a device having a function and a highly integrated semiconductor device on one chip.

However, by using the present invention, it is possible to manufacture the actuator chip 19 and other highly integrated semiconductor elements by a different process, and then form them into one chip.

Although FIGS. 19 and 20 show an embodiment in which the actuator chip 30 is provided with a decoder, an actuator, an actuator drive section and a D / A converter, a larger actuator is shown. It is also possible to connect the element chip only for the CPU to the CPU chip 2 through the element chip on which the decoder, the actuator driver and the D / A converter are formed.

[0093]

According to the present invention, the following effects can be obtained.

(1) A semiconductor device having a large area can be manufactured without lowering the yield of the semiconductor device.

(2) A plurality of functions can be formed on one chip, and each function can be as good as one chip and one function.

(3) High-mix low-volume production of semiconductor devices can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor device according to a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing a manufacturing process of the semiconductor device according to the first exemplary embodiment of the present invention.

FIG. 3 is a perspective view illustrating one manufacturing process of the semiconductor device according to the first exemplary embodiment of the present invention.

FIG. 4 is a perspective view illustrating one manufacturing process of the semiconductor device according to the first exemplary embodiment of the present invention.

FIG. 5 is a perspective view illustrating one manufacturing process of the semiconductor device according to the first exemplary embodiment of the present invention.

FIG. 6 is a perspective view illustrating one manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 7 is a schematic diagram illustrating a device used for wiring a semiconductor device according to a second exemplary embodiment of the present invention.

FIG. 8 is a schematic view illustrating another device used for wiring of the semiconductor device according to the second exemplary embodiment of the present invention.

FIG. 9 is a perspective view of a semiconductor device according to a third exemplary embodiment of the present invention.

FIG. 10 is a perspective view illustrating a structure of an end portion of a semiconductor device according to a fourth exemplary embodiment of the present invention.

FIG. 11 is a schematic diagram illustrating a connection structure of a semiconductor device according to a fourth exemplary embodiment of the present invention.

FIG. 12 is a perspective view of a semiconductor device according to a fifth exemplary embodiment of the present invention.

FIG. 13 is a layout configuration diagram of a semiconductor device according to a fifth exemplary embodiment of the present invention.

FIG. 14 is a layout configuration diagram of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 15 is a layout configuration diagram of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 16 is a layout configuration diagram of a semiconductor device according to an eighth exemplary embodiment of the present invention.

FIG. 17 is a layout configuration diagram of a semiconductor device according to an application of the eighth embodiment of the present invention.

FIG. 18 is a layout configuration diagram of a semiconductor device showing another mode of application of the eighth embodiment of the present invention.

FIG. 19 is a layout configuration diagram of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 20 is an explanatory diagram of an actuator chip of a semiconductor device according to a ninth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... CPU chip, 3 ... Memory chip, 4a, 4b ... Element formation surface, 5, 5a, 6, 6a ... Wiring, 7 ... Film, 8 ... Connection wiring, 9 ... Semiconductor substrate, 10 ... Base , 11 ... I / O control chip, 12 ... Sensor chip,
13 ... Laser oscillation chip, 14 ... Light receiving chip, 15 ... Wiring chip, 16 ... Wiring frame, 17 ... Element chip, 1
8 ... Wafer, 20 ... Raw material gas cylinder, 21 ... Mirror,
22 ... Laser oscillator, 23 ... Chamber, 24 ... Objective lens, 25 ... Movable stage, 26 ... Stage controller, 27
... data bus, 28 ... address bus, 29 ... control signal,
30 ... Actuator chip.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatsugu Kamiya 502, Kazunachi-cho, Tsuchiura-shi, Ibaraki Hiritsu Seisakusho Co., Ltd.

Claims (15)

[Claims] 1. A plurality of semiconductor chips each having a semiconductor element forming portion on the surface of a semiconductor substrate are arranged so that each element forming portion is on the same surface side, and are combined so that side surfaces of the semiconductor chips are in surface contact with each other. A semiconductor device characterized in that it is formed as one sheet. 2. A plurality of semiconductor chips each having a semiconductor element surface as a semiconductor element forming portion are arranged such that the element forming portions are on the same surface side, and the side surfaces having the same inclination angle are surface-connected to form one sheet. A semiconductor device characterized by comprising. 3. A plurality of semiconductor chips each having a semiconductor element surface as a semiconductor element forming portion are arranged such that the element forming portions are on the same plane side, and the side surfaces having the same crystal plane are surface-connected to each other to form one semiconductor chip. A semiconductor device characterized by comprising. 4. A plurality of semiconductor chips having a semiconductor element surface as a semiconductor element forming portion are arranged so that the element forming portions are on the same surface side, and are combined so that side surfaces of the semiconductor chips are in surface contact with each other. A semiconductor device, characterized in that a backing plate is arranged on the back side of the element forming portion, which is one. 5. The crystal plane of the side surface according to claim 3,
A semiconductor device having a {111} plane. 6. The semiconductor device according to claim 4, wherein the back side of the element forming portion and the backing plate are bonded with an adhesive. 7. A plurality of types of semiconductor chips are brought into surface contact with each other, and the semiconductor chips have a central arithmetic processing function, a memory function, an arithmetic function, a light receiving element mounted, and a light emitting device. The semiconductor chip is selected from the group consisting of a device mounted with an element, a device having a sensor function, a device simply serving as an electric signal transmitting means between chips, and a device having a movable part, and these semiconductor chips are combined into one. Semiconductor device. 8. A semiconductor characterized in that a plurality of semiconductor chips are combined so that their side surfaces are in surface contact with each other, and the atoms of the semiconductor material on the contact surface are directly bonded or bonded via oxygen atoms. apparatus. 9. A plurality of semiconductor chips having a semiconductor substrate surface as a semiconductor element forming portion are arranged such that each element forming portion is on the same surface side and opposing bonding surfaces are parallel to each other and combined. A method of manufacturing a semiconductor device, wherein the number of the semiconductor devices is one. 10. A semiconductor characterized in that a side surface of a semiconductor chip having a semiconductor substrate surface as a semiconductor element forming portion is anisotropically etched, and a plurality of semiconductor chips are connected to each other by aligning the etched surfaces of the semiconductor chip. Device manufacturing method. 11. The etching solution for etching according to claim 10, wherein KOH, NaOH, CsOH,
An alkali solution selected from the group of NH ₄ OH, an organic solution selected from the group of ethylenediamine, hydrazine and choline, or a solution containing quaternary ammonium hydroxide. 12. A plurality of semiconductor chips each having a semiconductor element forming portion on the surface of a semiconductor substrate are assembled so that the respective element forming portions are on the same surface side, and the connection surfaces are bonded by pressure at a temperature of 400 ° C. or higher. A method for manufacturing a semiconductor device, comprising: 13. The conductive film according to claim 9, wherein a conductive film is formed so as to extend over an edge of the semiconductor chip and an edge of another semiconductor chip in contact with the edge. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is divided and cut by any one of a laser, an ion beam, a plasma, and an electron beam according to a connection form of wiring. 14. A laser CVD apparatus according to any one of claims 9 to 12, wherein a position to be connected to a wiring in each semiconductor chip is recognized, and the position is prevented from interfering with other wiring, so that A method for manufacturing a semiconductor device, which comprises determining an irradiation path. 15. The arrangement according to claim 9, wherein the arrangement or the order of wirings for connecting the plurality of semiconductor chips to each other is unified over all the plurality of semiconductor chips. Method of manufacturing semiconductor device.