JPH05267480A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

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JPH05267480A
JPH05267480A JP9479692A JP9479692A JPH05267480A JP H05267480 A JPH05267480 A JP H05267480A JP 9479692 A JP9479692 A JP 9479692A JP 9479692 A JP9479692 A JP 9479692A JP H05267480 A JPH05267480 A JP H05267480A
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film
interlayer insulating
teos
semiconductor device
insulating film
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Japanese (ja)
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Kimihiko Yamashita
公彦 山下
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Ricoh Co Ltd
株式会社リコー
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Abstract

PURPOSE:To prevent detrimental affect on device properties by reducing an amount of carbon atom taken into a silicon oxide film when a silicon oxide film is formed by plasma CVD method using organic oxysilane such as TEOS as a main material. CONSTITUTION:A silicon substrate 26 is arranged on a lower electrode 23 and heated by a lamp 22. Reaction gas is supplied through a gas supply port 29 and a high frequency voltage is applied between both electrodes 23, 24 from a high frequency power supply 28. Thereby, reaction gas reacts and a BPSG film or a PSG film is deposited on the silicon substrate 26. Conditions of plasma CVD are; a pressure inside a CVD reaction chamber 21 of 6.5Torr, a substrate temperature of 300 to 450 deg.C, a power of the high frequency power supply 28 of 100 to 500W. The BPSG film is deposited supplying TEOS kept at 40 deg.C together with oxygen, TMP and TMB as a reaction gas from a gas supply port 29 to the reaction chamber 21 while making helium gas flow. Ratio of O2 flow rate/TEOS flow rate is 2.0 or above.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は層間絶縁膜としてシリコン酸化膜を有する半導体装置と、そのシリコン酸化膜層間絶縁膜をプラズマCVD法により堆積する製造方法に関するものである。 The present invention relates are those of the semiconductor device having a silicon oxide film as an interlayer insulating film, a manufacturing method of depositing the silicon oxide film interlayer insulating film by a plasma CVD method.

【0002】 [0002]

【従来の技術】半導体装置の層間絶縁膜としてプラズマCVD法によりTEOS(テトラエチルオルソシリケート)を主成分とする方法が用いられている。 How the main component TEOS (tetraethyl orthosilicate) is used by a plasma CVD method as an interlayer insulating film of a semiconductor device. この方法により形成したシリコン酸化膜は、シランを主原料として常圧CVD法により形成したシリコン酸化膜よりもステップカバレッジが優れており、またTEOSを主原料として常圧CVD法により形成したシリコン酸化膜よりも膜質が安定しているという利点を備えている。 Silicon oxide film formed by this method, silane has excellent step coverage than the silicon oxide film formed by normal pressure CVD method as a main material, also a silicon oxide film formed by atmospheric pressure CVD using TEOS as a main material film quality than is provided with the advantage of being stable.

【0003】MOS型半導体装置のゲート配線(ポリシリコン又はポリサイドなど)と第1層目メタル配線との間の層間絶縁膜としてBPSG膜やPSG膜などのシリコン酸化膜が広く用いられており、その層間絶縁膜としてステップカバレッジがよくリフロー後の平坦度を向上させる目的でTEOSを主原料としたプラズマCVD法が採用されている。 [0003] The gate wiring of a MOS type semiconductor device (polysilicon or polycide, etc.) and silicon oxide film such as BPSG film or a PSG film is widely used as an interlayer insulating film between the first layer metal interconnection, the plasma CVD method using TEOS as a main material for the purpose of improving the flatness after step coverage is good reflow as an interlayer insulating film is employed. しかし、TEOSを主原料としてプラズマCVD法で形成されたシリコン酸化膜は、シリコン酸化膜形成の過程で発生する有機成分がシリコン酸化膜中に取り込まれる傾向が強い。 However, the silicon oxide film formed by plasma CVD using TEOS as a main material has a strong tendency to organic components generated in the course of the silicon oxide film formation is incorporated into the silicon oxide film. 現在主流となっている絶縁膜形成材料であるシラン(SiH 4 )は、その分子構造に有機成分を含んでおらず、したがってシランを主原料として形成したシリコン酸化膜には炭素は含有されない。 Silane which is an insulating film-forming material that is currently the mainstream (SiH 4), the does not contain organic components in the molecular structure, therefore the silicon oxide film formed with silane as the main raw material carbon is not contained.

【0004】TEOSを主原料としてプラズマCVD法により形成したシリコン酸化膜をメタル配線とメタル配線の間の層間絶縁膜として利用する場合はシリコン酸化膜中に取り込まれた炭素原子は安定であり、半導体装置の特性に悪影響を与えることはない。 [0004] carbon atoms incorporated into the silicon oxide film when used as an interlayer insulating film between the silicon oxide film formed by plasma CVD using TEOS as a main material a metal wire and the metal wire is stable, semiconductor It does not adversely affect the characteristics of the device. しかし、そのシリコン酸化膜をゲート配線とメタル配線間の層間絶縁膜に用いた場合、通常、CVD膜形成後に平坦化と注入不純物の活性化を目的とした熱処理(リフロー工程)が行なわれるので、TEOSを原料として形成されたシリコン酸化膜中に取り込まれた炭素原子がその熱処理により半導体基板中に拡散し、デバイス特性に悪影響を与える。 However, in the case of using the silicon oxide film on the interlayer insulating film between the gate wiring and the metal wiring, typically, the heat treatment for the purpose of activation of flattening and implanted impurities after CVD film formation (reflow process) is performed, TEOS was diffused into the semiconductor substrate by a carbon atom incorporated into a silicon oxide film formed as a raw material thereof a heat treatment, adversely affect the device characteristics.

【0005】そこで、プラズマCVD法によりTEOS [0005] Therefore, TEOS by a plasma CVD method
を主原料として形成されるシリコン酸化膜中に炭素などの不純物が取り込まれるのを防ぐためにいくつかの方法が提案されている。 The are several ways to prevent impurities from being taken such as carbon in the silicon oxide film formed as a main raw material have been proposed. 例えば、TEOSを窒素で通気してCVD装置に導くことにより膜中に取り込まれる炭素量を減らす方法(特開平1−238024号公報参照)、 For example, a method of reducing the amount of carbon incorporated into the film by directing a TEOS to CVD apparatus by bubbling with nitrogen (see Japanese Patent Laid-Open No. 1-238024),
TEOSを主原料として生成したシリコン酸化膜をオゾン雰囲気中又は酸素プラズマ中でアニール処理することにより膜中の不純物を減少させる方法(特開平3−41 Method for reducing the impurities in the film by annealing the silicon oxide film formed using TEOS as a main material in an ozone atmosphere or oxygen plasma (JP-A-3-41
731号公報参照)、シリコン酸化膜を酸素プラズマ又は酸素ラジカルで処理することにより不純物を減少させてリーク電流を低減する方法(特開平2−219232 See JP 731), a method of decreasing the impurities to reduce the leakage current by processing the silicon oxide film by oxygen plasma or oxygen radicals (JP-A-2-219232
号公報参照)、TEOSに水素又は水蒸気を混合することにより酸化膜に取り込まれる炭素量を減らす方法(特開平2−285636号公報参照)などである。 No. see Japanese), see Japanese method (JP-A-2-285636 to reduce the amount of carbon incorporated into the oxide film by mixing hydrogen or water vapor TEOS) and the like.

【0006】 [0006]

【発明が解決しようとする課題】本発明はTEOSなどの有機オキシシランを主原料としてプラズマCVD法によりシリコン酸化膜を形成する際に、上記の提案された方法とは別の方法によりシリコン酸化膜に取り込まれる炭素原子の量を少なくしてデバイス特性に悪影響を与えないようにする方法と、そのように形成された層間絶縁膜をもつ半導体装置を提供することを目的とするものである。 When forming the silicon oxide film by plasma CVD organic oxysilane such as the present invention is TEOS [0006] As a main raw material, the silicon oxide film by a different method from the method proposed in the a way to not adversely affect the least to the device properties the amount of carbon atoms incorporated, it is an object to provide a semiconductor device having the so-formed interlayer insulating film.

【0007】 [0007]

【課題を解決するための手段】本発明の半導体装置では、メタル配線の下に形成される層間絶縁膜として有機オキシシランを主成分としプラズマCVD法により堆積された炭素含有量の少ないシリコン酸化膜が用いられている。 In the semiconductor device of the present invention SUMMARY OF THE INVENTION may, carbon content less silicon oxide film deposited by the plasma CVD method as a main component an organic oxysilane as an interlayer insulating film formed under the metal wiring It has been used. 好ましい態様では、その層間絶縁膜はゲート配線とメタル配線との間の層間絶縁膜である。 In a preferred embodiment, the interlayer insulating film is an interlayer insulating film between the gate wiring and the metal wiring. 本発明の製造方法では、プラズマCVD法により半導体装置の層間絶縁膜を堆積する際に、主原料として有機オキシシランを用い、酸素流量と有機オキシシラン流量との比を、有機オキシシランを通気ガス流量で表わしたときの流量比としてO 2 /(有機オキシシラン)を2.0以上とする。 In the production method of the present invention, in depositing an interlayer insulating film of a semiconductor device by the plasma CVD method, an organic oxysilane used as a main raw material, the ratio of oxygen flow and the organic oxysilane flow, represents an organic oxysilane breathable gas flow O 2 / (organic oxysilane) and 2.0 or more as a flow ratio when the.

【0008】プラズマCVD法によるシリコン酸化膜形成の主原料としての有機オキシシランは、TEOSの他にC 25 Si(OC 253やSi(OC 374 、Si [0008] Organic oxysilane as a main raw material of the silicon oxide film formed by the plasma CVD method, C 2 H 5 Si (OC 2 H 5) 3 and Si (OC 3 H 7) in addition to TEOS 4, Si
(OCH 34などを用いることができる。 (OCH 3) 4 or the like can be used. 有機オキシシランを反応室へ導くには、適度に加熱した有機オキシシランにヘリウムなどの不活性ガスや酸素を通気してその通気ガスとともに導いたり、有機オキシシランを加熱してその蒸気を導くようにすればよい。 To guide the organic oxysilane into the reaction chamber, or lead together with the vent gas is vented with an inert gas and oxygen, such as helium moderately heated organic oxysilane, if to direct the vapor to heat the organic oxysilane good. TEOSの場合に通気するときは、TEOSの温度を30〜50℃に設定するのが適当である。 When venting in the case of TEOS, it is appropriate to set the temperature of the TEOS in 30 to 50 ° C..

【0009】 [0009]

【実施例】図1は本発明の半導体装置の一実施例を表わしたものである。 DETAILED DESCRIPTION FIG. 1 is a representation of one embodiment of a semiconductor device of the present invention. シリコン基板2にフィールド酸化膜4 Field oxide film on a silicon substrate 2 4
により活性領域が形成され、その活性領域にはソース領域6とドレイン領域8が不純物拡散により形成され、ソース領域6とドレイン領域8の間のチャネル領域上にはゲート酸化膜10を介してポリシリコンのゲート電極1 The active region is formed, the source region 6 and the drain region 8 in the active region is formed by impurity diffusion, polysilicon through the gate oxide film 10 on a channel region between the source region 6 and the drain region 8 the gate electrode 1
2が形成されている。 2 is formed. ゲート電極12とメタル配線1 Gate electrode 12 and the metal wiring 1
6,18との間の層間絶縁膜14としてTEOSを主成分としプラズマCVD法により堆積された炭素含有量の少ないシリコン酸化膜であるBPSG膜又はPSG膜が形成されている。 BPSG film or a PSG film as the interlayer insulating film 14 is a silicon oxide film with less carbon content deposited by the TEOS as a main component plasma CVD method between the 6, 18 are formed. 層間絶縁膜14にはコンタクトホールが形成され、メタル配線16,18がそれぞれソース領域16、ドレイン領域8と接続されている。 A contact hole is formed in the interlayer insulating film 14, metal wiring 16 and 18 are connected the source region 16, a drain region 8.

【0010】図2は本発明の製造方法で用いるプラズマCVD装置を概略的に示したものである。 [0010] FIG. 2 is a view of the plasma CVD apparatus used in the manufacturing method of the present invention shown schematically. 図2で、反応室21内にはランプ22により温度制御される接地された下部電極23と、反応ガスを放出するシャワーヘッドを有し高周波印加電極を兼ねる上部電極24が配置されている。 In Figure 2, the reaction chamber 21 and the lower electrode 23 which is grounded is temperature controlled by the lamp 22, the upper electrode 24 serving as a high frequency application electrode has a showerhead to release the reactive gas is arranged. 反応室21は排気口25から真空排気される。 The reaction chamber 21 is evacuated through the exhaust port 25.
下部電極23上にはシリコン酸化膜を堆積しようとするシリコン基板26が上部電極24と対向するように配置される。 On the lower electrode 23 is arranged so that the silicon substrate 26 to be a silicon oxide film is deposited is opposed to the upper electrode 24. TEOSはヘリウムなどの不活性ガス又は酸素によって通気され、その通気ガスのヘリウムや酸素とともにガス供給口29から反応室21へ供給される。 TEOS is vented with an inert gas or oxygen, such as helium, it is supplied from the gas supply port 29 with helium and oxygen for the aeration gas into the reaction chamber 21. ガス供給口29からはTEOSを含む通気ガスの他に、酸素と、TMP(トリメチルホスフェート;PO(OC Other vent gas containing TEOS from the gas supply port 29, and oxygen, TMP (trimethyl phosphate; PO (OC
33 )やTMB(トリメチルボレート;B(OC H 3) 3) and TMB (trimethyl borate; B (OC
33 )などの不純物原料ガスも反応室21へ供給される。 H 3) 3) impurity source gas such also supplied to the reaction chamber 21. これらの反応ガスは上部電極24のシャワーヘッドからシリコン基板26上に均一に供給され、排気口25 These reaction gas is uniformly supplied onto the silicon substrate 26 from the showerhead of the upper electrode 24, the exhaust port 25
から排気される。 It is exhausted from. 上部電極24と下部電極23の間には高周波電源28によって13.56MHzの高周波電圧が印加される。 13.56MHz high-frequency voltage is applied by the high frequency power source 28 to between the upper electrode 24 and the lower electrode 23.

【0011】図2のCVD装置で、シリコン基板26を下部電極23上に配置し、石英ガラス27を経てランプ22から反応室21内に入射される光により基板26が下地電極23を介して加熱される。 [0011] In the CVD apparatus of FIG. 2, to place the silicon substrate 26 on the lower electrode 23, the substrate 26 by the light incident on the reaction chamber 21 from the lamp 22 through the quartz glass 27 is heated through the base electrode 23 It is. ガス供給口29を経て反応ガスが供給され、高周波電源28から両電極2 The reaction gas is supplied through the gas supply port 29, the electrodes 2 from the high frequency power supply 28
3,24間に高周波電圧が印加されることにより、反応ガスが反応してシリコン基板6上にBPSG膜又はPS By the high-frequency voltage is applied between the 3, 24, BPSG film on the silicon substrate 6 reactive gas reacts or PS
G膜が堆積する。 G film is deposited.

【0012】プラズマCVDの条件として、CVD反応室21内の圧力を2〜12Torr、例えば約6.5Torrとし、基板温度を300〜450℃とし、高周波電源28 [0012] As conditions of the plasma CVD, the pressure in the CVD reaction chamber 21 2~12Torr, for example, about 6.5Torr, a substrate temperature of 300 to 450 ° C., a high frequency power source 28
の電力を100〜500Wに設定する。 Setting the power to the 100~500W. TEOSとして純度99.9999%のものを用い、約40℃に保温し、ヘリウムガスで通気しながら酸素及びTMP、TM With a purity of 99.9999% as TEOS, it was kept at about 40 ° C., oxygen and TMP with aeration with helium gas, TM
Bとともにガス供給口29から反応室21へ供給しながらBPSG膜を堆積させた場合の、BPSG膜の成膜速度とO 2流量/TEOS流量比の関係を図3(A)に示す。 When the BPSG film was deposited while supplied from the gas supply port 29 into the reaction chamber 21 together with B, shown in FIG. 3 (A) the relationship between the deposition rate and O 2 flow rate / TEOS flow ratio of BPSG film. ここで、O 2とTEOSの流量比は、TEOS流量としては40℃に保温されたTEOSにヘリウムガスを通気して気化させ、ヘリウムガスとともに反応室21へ導くときのヘリウムガス流量として表わされている。 Here, the flow ratio of O 2 and TEOS as the TEOS flow is vaporized by bubbling helium gas TEOS which is kept at 40 ° C., expressed as a helium gas flow rate when the leading with helium gas to the reaction chamber 21 ing. 図3(A)によれば、O 2流量/TEOS流量比が小さいほどBPSG膜の成膜速度が大きくなり、一般的には生産性を考慮してその比が0.5〜2.0の範囲に設定されて使用されている。 According to FIG. 3 (A), O 2 flow rate / TEOS deposition rate as the flow rate ratio is smaller BPSG film increases, typically the ratio is 0.5 to 2.0 in consideration of productivity It is set in the range being used. しかし、そのような範囲で形成されたBPSG膜には多量の炭素が取り込まれ、それがデバイス特性に悪影響を与えることがわかった。 However, a large amount of carbon incorporated in the BPSG film formed in such a range, it was found that adversely affect the device characteristics. 図3(B) Figure 3 (B)
はBPSG膜形成時のO 2流量/TEOS流量比とBP O 2 flow rate during BPSG film / TEOS flow ratio and BP
SG膜中の炭素含有量との関係を表わしたものである。 Flowchart showing a relation between the carbon content in SG film.
炭素含有量はSIMS(二次イオン質量分析法)により測定したものであり、BPSG膜成膜後リフロー工程(920℃、窒素雰囲気、30分)を行なった試料をS The carbon content is one measured by SIMS (secondary ion mass spectrometry), BPSG film formation after the reflow step (920 ° C., nitrogen atmosphere, 30 minutes) the sample was subjected to S
IMS分析し、BPSG膜とシリコン基板との界面に偏析した炭素のピーク濃度を示している。 And IMS analysis shows a peak concentration of carbon segregated to the interface between the BPSG film and the silicon substrate. また、シランを主原料としたBPSG膜の膜中炭素濃度は約5.0×1 Further, the film in the carbon concentration in the BPSG film using silane as the main raw material of about 5.0 × 1
18原子/ccであり、これはSIMS分析のバックグラウンド値とほぼ同じである。 0 18 is an atomic / cc, which is about the same as a background value of the SIMS analysis.

【0013】BPSG膜中に取り込まれた炭素のデバイス特性に与える影響が最も顕著に現われるのは、CMO [0013] The effect on device characteristics of carbon incorporated into the BPSG film appears most notably, CMO
SデバイスのP型拡散層の抵抗であり、取り込まれた炭素量が多いほどP型拡散層の抵抗が高くなる傾向が見られる。 The resistance of the P-type diffusion layer of the S devices, tends to resistance increases of incorporated higher the carbon content P-type diffusion layer is observed. 図3(C)はO 2流量/TEOS流量比とP型拡散層のシート抵抗値の関係を示したものである。 FIG. 3 (C) is shows the relationship between the sheet resistance value of the O 2 flow rate / TEOS flow ratio and P-type diffusion layer. シート抵抗値はO 2流量/TEOS流量比の増加にともない減少していくのがわかる。 Sheet resistance seen that decreases with an increase of the O 2 flow rate / TEOS flow ratio.

【0014】図3の結果から、TEOSを主原料とするプラズマCVDによるBPSG膜中の炭素量はO 2流量/TEOS流量比に依存し、デバイス特性に与える影響も同様にその比に依存する。 [0014] From the results of FIG. 3, the carbon content in the BPSG film by plasma CVD using TEOS as a main material depends on the O 2 flow rate / TEOS flow ratio, also impact on the device characteristics similarly depends on the ratio. したがって、BPSG膜中の炭素の影響を極力少なくするためには、その比をできるだけ高く設定する必要があり、その値は2.0以上とするのが適当である。 Therefore, in order to minimize the influence of the carbon in the BPSG film, it is necessary to set high as possible the ratio, it is appropriate to that value 2.0 or more.

【0015】実施例は主原料としてTEOSを取り上げているが、有機オキシシランとしてはそれ以外にC 25 [0015] Examples, but is taken up TEOS as a main material, C 2 H 5 otherwise as organic Oxysilane
Si(OC 253 、Si(OC 374 、Si(OCH Si (OC 2 H 5) 3 , Si (OC 3 H 7) 4, Si (OCH
34などを用いることもでき、それらの有機オキシシランを主原料とした場合にも同様に炭素が取り込まれる傾向があるので、それらの場合も本発明によO 2流量/ 3) can also be used as 4, there is a tendency that the carbon is incorporated in the same manner when those organic oxysilane as a main raw material, by the present invention even if their O 2 flow /
(有機オキシシラン)流量比を2.0以上とすることにより取り込まれる炭素量を少なくすることができる。 It is possible to reduce the amount of carbon taken up by the (organic oxysilane) flow rate ratio of 2.0 or more.

【0016】 [0016]

【発明の効果】本発明ではBPSG膜やPSG膜をTE TE a BPSG film or a PSG film in the present invention
OSなどの有機オキシシランを主成分としてプラズマC Plasma C organic oxysilane such as an operating system (OS) as the main component
VD法により形成する際、O 2流量/(有機オキシシラン)流量比を2.0以上に設定したことにより、BPS When forming the VD method, by setting the O 2 flow rate / (organic oxysilane) flow rate ratio to 2.0 or more, BPS
G膜やPSG膜などのシリコン酸化膜に取り込まれる炭素量が減少してデバイス特性に悪影響を与えることなく、良質の層間絶縁膜を形成することができる。 Without adversely affecting the device characteristics amount of carbon incorporated in the silicon oxide film such as G film or PSG film is reduced, good quality can be formed the interlayer insulating film. この層間絶縁膜はデバイス特性に悪影響を与えないことからゲート配線とメタル配線の間の層間絶縁膜として利用することができる。 The interlayer insulating film can be used as an interlayer insulating film between the gate wiring and the metal wiring since it does not adversely affect the device characteristics.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】一実施例の半導体装置を示す断面図である。 1 is a sectional view showing a semiconductor device of an embodiment.

【図2】本発明が適用されるプラズマCVD装置の一例を概略的に示す断面図である。 An example of FIG. 2 plasma CVD apparatus to which the present invention is applied is a sectional view schematically showing.

【図3】一実施例におけるO 2流量/TEOS流量比と成膜速度、炭素濃度、シート抵抗値の関係をそれぞれ示す図である。 3 is a diagram illustrating O 2 flow / TEOS flow ratio in an embodiment and the deposition rate, the carbon concentration, the relationship between the sheet resistance, respectively.

【符号の説明】 DESCRIPTION OF SYMBOLS

2 シリコン基板 6 ソース 8 ドレイン 10 ゲート酸化膜 12 ゲート電極 14 層間絶縁膜 16,18 メタル配線 21 CVD装置の反応室 22 温度制御用ランプ 23 下部電極 24 上部電極 26 シリコン基板 28 高周波電源 2 silicon substrate 6 source 8 drain 10 gate oxide film 12 gate electrode 14 interlayer insulating films 16 and 18 the reaction chamber 22 for temperature control lamp 23 lower electrode 24 upper electrode 26 silicon substrate 28 of the metal wiring 21 CVD apparatus high-frequency power supply

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体装置のメタル配線の下に形成される層間絶縁膜として有機オキシシランを主成分としプラズマCVD法により堆積された炭素含有量の少ないシリコン酸化膜が用いられていることを特徴とする半導体装置。 1. A and characterized in that the carbon content less silicon oxide film deposited by the plasma CVD method as a main component an organic oxysilane as an interlayer insulating film formed under the metal wiring of a semiconductor device has been used semiconductor device.
  2. 【請求項2】 前記層間絶縁膜がゲート配線とメタル配線との間の層間絶縁膜である請求項1に記載の半導体装置。 2. A semiconductor device according to claim 1 which is an interlayer insulating film between the interlayer insulating film is a gate wiring and the metal wiring.
  3. 【請求項3】 プラズマCVD法により半導体装置の層間絶縁膜を堆積する方法において、主原料として有機オキシシランを用い、酸素流量と有機オキシシラン流量との比を、有機オキシシランを通気ガス流量で表わしたときの流量比としてO 2 /(有機オキシシラン)を2.0以上とすることを特徴とする半導体装置の製造方法。 By 3. A plasma CVD method in a method of depositing an interlayer insulating film of a semiconductor device, an organic oxysilane used as a main raw material, the ratio of oxygen flow and the organic oxysilane flow, when expressed organic oxysilane breathable gas flow the method of manufacturing a semiconductor device characterized by the of O 2 / (organic oxysilane) 2.0 or higher as a flow ratio.
  4. 【請求項4】 前記層間絶縁膜がゲート配線とメタル配線との間の層間絶縁膜である請求項3に記載の半導体装置の製造方法。 4. A method of manufacturing a semiconductor device according to claim 3 which is an interlayer insulating film between the interlayer insulating film is a gate wiring and the metal wiring.
JP9479692A 1992-03-21 1992-03-21 Semiconductor device and its manufacture Pending JPH05267480A (en)

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US6054379A (en) * 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6287990B1 (en) 1998-02-11 2001-09-11 Applied Materials, Inc. CVD plasma assisted low dielectric constant films
US6399489B1 (en) 1999-11-01 2002-06-04 Applied Materials, Inc. Barrier layer deposition using HDP-CVD
US6586346B1 (en) 1990-02-06 2003-07-01 Semiconductor Energy Lab Method of forming an oxide film
US6593655B1 (en) 1998-05-29 2003-07-15 Dow Corning Corporation Method for producing hydrogenated silicon oxycarbide films having low dielectric constant
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US6667553B2 (en) 1998-05-29 2003-12-23 Dow Corning Corporation H:SiOC coated substrates
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US7227244B2 (en) 1998-02-11 2007-06-05 Applied Materials, Inc. Integrated low k dielectrics and etch stops
US6072227A (en) * 1998-02-11 2000-06-06 Applied Materials, Inc. Low power method of depositing a low k dielectric with organo silane
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US7023092B2 (en) 1998-02-11 2006-04-04 Applied Materials Inc. Low dielectric constant film produced from silicon compounds comprising silicon-carbon bonds
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