JPH052555A - ワークステーシヨンインターフエース装置用の内部バス - Google Patents

ワークステーシヨンインターフエース装置用の内部バス

Info

Publication number
JPH052555A
JPH052555A JP3242426A JP24242691A JPH052555A JP H052555 A JPH052555 A JP H052555A JP 3242426 A JP3242426 A JP 3242426A JP 24242691 A JP24242691 A JP 24242691A JP H052555 A JPH052555 A JP H052555A
Authority
JP
Japan
Prior art keywords
bus
central processing
unit
processing unit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP3242426A
Other languages
English (en)
Japanese (ja)
Inventor
Edward C King
シー． キング エドワード
Anton Goeppel
ゴーペル アントン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of JPH052555A publication Critical patent/JPH052555A/ja
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
JP3242426A 1990-08-31 1991-08-29 ワークステーシヨンインターフエース装置用の内部バス Ceased JPH052555A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9018992.9 1990-08-31
GB909018992A GB9018992D0 (en) 1990-08-31 1990-08-31 Internal bus for work station interfacing means

Publications (1)

Publication Number Publication Date
JPH052555A true JPH052555A (ja) 1993-01-08

Family

ID=10681419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3242426A Ceased JPH052555A (ja) 1990-08-31 1991-08-29 ワークステーシヨンインターフエース装置用の内部バス

Country Status (5)

Country Link
US (1) US5363492A (https=)
EP (1) EP0474442B1 (https=)
JP (1) JPH052555A (https=)
DE (1) DE69128823T2 (https=)
GB (1) GB9018992D0 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600839A (en) * 1993-10-01 1997-02-04 Advanced Micro Devices, Inc. System and method for controlling assertion of a peripheral bus clock signal through a slave device
WO1995020193A1 (en) * 1994-01-25 1995-07-27 Apple Computer, Inc. Improved bus protocol using separate clocks for arbitration and data transfer
EP0665501A1 (en) * 1994-01-28 1995-08-02 Compaq Computer Corporation Bus master arbitration circuitry with retry mechanism
US5511203A (en) * 1994-02-02 1996-04-23 Advanced Micro Devices Power management system distinguishing between primary and secondary system activity
US5758107A (en) * 1994-02-14 1998-05-26 Motorola Inc. System for offloading external bus by coupling peripheral device to data processor through interface logic that emulate the characteristics of the external bus
US5729705A (en) * 1995-07-24 1998-03-17 Symbios Logic Inc. Method and apparatus for enhancing throughput of disk array data transfers in a controller
US5734848A (en) * 1995-07-24 1998-03-31 Symbios Logic Inc. Method and appartus for transferring data in a controller having centralized memory

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4807109A (en) * 1983-11-25 1989-02-21 Intel Corporation High speed synchronous/asynchronous local bus and data transfer method
US4777591A (en) * 1984-01-03 1988-10-11 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
JPS61156338A (ja) * 1984-12-27 1986-07-16 Toshiba Corp マルチプロセツサシステム
JPS6226561A (ja) * 1985-07-26 1987-02-04 Toshiba Corp パ−ソナルコンピユ−タ
US4805137A (en) * 1987-01-08 1989-02-14 United Technologies Corporation Bus controller command block processing system
US4782439A (en) * 1987-02-17 1988-11-01 Intel Corporation Direct memory access system for microcontroller
US5151986A (en) * 1987-08-27 1992-09-29 Motorola, Inc. Microcomputer with on-board chip selects and programmable bus stretching
US4933845A (en) * 1987-09-04 1990-06-12 Digital Equipment Corporation Reconfigurable bus
US4979097A (en) * 1987-09-04 1990-12-18 Digital Equipment Corporation Method and apparatus for interconnecting busses in a multibus computer system
JP2749819B2 (ja) * 1987-10-26 1998-05-13 松下電工株式会社 共有メモリ制御方式
US5089953A (en) * 1987-12-28 1992-02-18 Sundstrand Corporation Control and arbitration unit
US5125084A (en) * 1988-05-26 1992-06-23 Ibm Corporation Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller
US5073969A (en) * 1988-08-01 1991-12-17 Intel Corporation Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
DE68919032T2 (de) * 1988-08-29 1995-06-08 Mitsubishi Rayon Co Polymerzusammensetzung und optische Faser, umhüllt mit diese Zusammensetzung.
DE3853071D1 (de) * 1988-09-30 1995-03-23 Siemens Nixdorf Inf Syst Verfahren zur Steuerung der Datenübertragung einer Zentraleinheiten-Anschlusssteuerungsschaltung und Schaltungsanordnung zur Durchführung desVerfahrens.
US5123092A (en) * 1988-10-21 1992-06-16 Zenith Data Systems Corporation External expansion bus interface
US5083259A (en) * 1988-12-07 1992-01-21 Xycom, Inc. Computer bus interconnection device
US5070449A (en) * 1988-12-19 1991-12-03 Honeywell Inc. Bus interface controller for computer graphics
EP0390978A1 (en) * 1989-04-03 1990-10-10 Koninklijke Philips Electronics N.V. Communication system with a two-wire serial backbone bus for connecting bridges to secondary three-wire buses
US5088028A (en) * 1989-04-07 1992-02-11 Tektronix, Inc. Lock converting bus-to-bus interface system
US5060139A (en) * 1989-04-07 1991-10-22 Tektronix, Inc. Futurebus interrupt subsystem apparatus
EP0400174B1 (de) * 1989-05-31 1995-08-30 Siemens Aktiengesellschaft Adaptereinrichtung zum störungsfreien Anschluss von peripheren Rechnereinrichtungen an eine von Rechnersystemen gesteuerte Peripherieschnittstelle
US5101479A (en) * 1989-07-21 1992-03-31 Clearpoint Research Corporation Bus device for generating and responding to slave response codes
US5165022A (en) * 1989-10-23 1992-11-17 International Business Machines Corporation Channel and control unit having a first I/O program protocol for communication with a main processor and a second universal I/O program protocol for communication with a plurality of I/O adapters
US5125080A (en) * 1989-11-13 1992-06-23 Chips And Technologies, Incorporated Logic support chip for AT-type computer with improved bus architecture
US5072365A (en) * 1989-12-27 1991-12-10 Motorola, Inc. Direct memory access controller using prioritized interrupts for varying bus mastership
US5155844A (en) * 1990-02-14 1992-10-13 International Business Machines Corporation Background memory test during system start up
US5233692A (en) * 1990-04-06 1993-08-03 Micro Technology, Inc. Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface
US5218681A (en) * 1990-08-31 1993-06-08 Advanced Micro Devices, Inc. Apparatus for controlling access to a data bus
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus

Also Published As

Publication number Publication date
EP0474442B1 (en) 1998-01-28
EP0474442A2 (en) 1992-03-11
GB9018992D0 (en) 1990-10-17
DE69128823T2 (de) 1998-09-03
EP0474442A3 (https=) 1994-08-03
US5363492A (en) 1994-11-08
DE69128823D1 (de) 1998-03-05

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