JPH05251258A - Thin film capacitor and manufacture thereof - Google Patents
Thin film capacitor and manufacture thereofInfo
- Publication number
- JPH05251258A JPH05251258A JP4083172A JP8317292A JPH05251258A JP H05251258 A JPH05251258 A JP H05251258A JP 4083172 A JP4083172 A JP 4083172A JP 8317292 A JP8317292 A JP 8317292A JP H05251258 A JPH05251258 A JP H05251258A
- Authority
- JP
- Japan
- Prior art keywords
- lower electrode
- thin film
- film capacitor
- dielectric
- upper electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄膜コンデンサおよびそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、半導体集積回路用の薄膜コンデン
サは、ポリシリコンを電極とするシリコン酸化膜および
シリコン窒化膜の積層構造からなり、ダイナミックラン
ダムアクセスメモリにおいて、トランジスタおよびビッ
ト線を形成後に容量部を形成する技術としては、例えば
１９８８年インターナショナル・エレクトロン・デバイ
セズ・ミーティング・ダイジェスト・オブ・テクニカル
・ペイパーズ（International Electron Devices Meeti
ng Digest of Technical Papers,1988）の 592〜595頁
に記載されている。2. Description of the Related Art Conventionally, a thin film capacitor for a semiconductor integrated circuit has a laminated structure of a silicon oxide film and a silicon nitride film using polysilicon as an electrode, and in a dynamic random access memory, a capacitor portion is formed after forming a transistor and a bit line. For example, the technology for forming the ‘International Electron Devices Meeti 1988 International Electron Devices Meeting Digest of Technical Papers’
ng Digest of Technical Papers, 1988), pages 592-595.
【０００３】[0003]
【発明が解決しようとする課題】上述の従来の薄膜キャ
パシタでは、近年の集積回路のより一層の高集積化に対
応した容量部の面積の縮小に限界がある。したがって、
薄膜キャパシタの誘電体部の薄膜化と高誘電率化、およ
び立体構造化によって容量部の面積を実効的に縮小しな
ければならない。従来の容量を形成する誘電体はシリコ
ン酸化膜やシリコン窒化膜であり、これらの誘電率はた
かだか７程度であるため、要求される容量を達成するた
めにはシリコン酸化膜換算で１０ｎｍ以下という極めて
薄い膜厚が求められる。一方、このような薄い膜厚では
許容されるリーク電流以下の電流−電圧特性を有する誘
電体薄膜を実現するのは非常に困難である。また、立体
構造を用いて実効的に電極面積を増加させる方法を用い
ても、下部電極の表面形状が平坦ではない場合、誘電体
膜の部分的に薄くなるところで電界が集中することによ
り、リーク電流の増大が生じる。In the above-mentioned conventional thin film capacitor, there is a limit to the reduction of the area of the capacitance portion corresponding to the higher integration of integrated circuits in recent years. Therefore,
It is necessary to effectively reduce the area of the capacitor part by thinning the dielectric part of the thin film capacitor, increasing the dielectric constant, and forming a three-dimensional structure. The conventional dielectric material forming the capacitance is a silicon oxide film or a silicon nitride film, and the dielectric constant of these is at most about 7. Therefore, in order to achieve the required capacitance, it is extremely less than 10 nm in terms of silicon oxide film. Thin film thickness is required. On the other hand, with such a thin film thickness, it is very difficult to realize a dielectric thin film having a current-voltage characteristic equal to or less than an allowable leak current. Even if a method of effectively increasing the electrode area by using a three-dimensional structure is used, if the surface shape of the lower electrode is not flat, the electric field concentrates at the part where the dielectric film becomes thin, which causes leakage. An increase in current occurs.
【０００４】したがって、例えば室温で３００近い誘電
率を有するＳｒＴｉＯ3や、さらに大きな誘電率を有す
る（Ｂａ，Ｓｒ）ＴｉＯ3やＰｂ（Ｚｒ，Ｔｉ）Ｏ3やＰ
ｂ（Ｍｇ，Ｎｂ）Ｏ3やＰｂ（Ｍｇ，Ｗ）Ｏ3に代表され
る高誘電率の誘電体を容量形成部に用いることで、要求
される容量をシリコン酸化膜などの場合と比べてより厚
い膜厚で実現する方法が考えられるが、この場合も所定
の形状に加工された下部電極表面の凹凸のため高誘電率
膜の局部的な膜厚の減少や電界集中によるリーク電流の
増加は避けられなかった。本発明の目的はこのような従
来の欠点を解決した薄膜コンデンサを提供することにあ
る。Therefore, for example, SrTiO 3 having a dielectric constant close to 300 at room temperature, (Ba, Sr) TiO 3 or Pb (Zr, Ti) O 3 or P having a larger dielectric constant is used.
By using a high-dielectric-constant dielectric material typified by b (Mg, Nb) O 3 or Pb (Mg, W) O 3 for the capacitance forming portion, the required capacitance is higher than that in the case of a silicon oxide film. A method of achieving a thicker film thickness is conceivable, but in this case as well, the unevenness of the lower electrode surface processed into a prescribed shape causes a local decrease in the film thickness of the high dielectric constant film and an increase in leakage current due to electric field concentration. Was inevitable. An object of the present invention is to provide a thin film capacitor that solves the above-mentioned conventional drawbacks.
【０００５】[0005]
【課題を解決するための手段】本発明の第１は、基板上
に下部電極、誘電体膜および上部電極を順次積層した薄
膜コンデンサであって、下部電極の少なくとも最表面層
が窒素を含有するＰｔ、Ｐｄ、Ｒｈ、Ｒｕ、Ｒｅ、Ｏ
ｓ、Ｉｒのうち少なくとも１種以上の材料からなり、誘
電体が誘電率の大きな高誘電率膜からなることを特徴と
する薄膜コンデンサ、および、基板上に下部電極、誘電
体膜および上部電極を順次積層した薄膜コンデンサの製
造方法であって、下部電極の最表面層がＰｔ、Ｐｄ、Ｒ
ｈ、Ｒｕ、Ｒｅ、Ｏｓ、Ｉｒのうち少なくとも１種以上
の材料からなり、該下部電極をスパッタリング法により
作製する際、スパッタガスにＮ2を混合し、表面形状を
平坦化する工程を備え、しかる後に誘電体膜を形成し、
上部電極を形成することを特徴とする薄膜コンデンサの
製造方法である。ここで、下部電極の窒素含有量は特に
限定されないが、良好な導電性を保持するには、１０原
子％以下が好ましく、この窒素含有の層は、下部電極が
多層構造をとる場合は、少なくとも最上層が窒素含有層
であればよい。A first aspect of the present invention is a thin film capacitor in which a lower electrode, a dielectric film and an upper electrode are sequentially laminated on a substrate, and at least the outermost surface layer of the lower electrode contains nitrogen. Pt, Pd, Rh, Ru, Re, O
of at least one of s and Ir, and the dielectric material is a high dielectric constant film having a large dielectric constant, and a lower electrode, a dielectric film and an upper electrode on a substrate. A method of manufacturing a sequentially laminated thin film capacitor, wherein the outermost surface layer of the lower electrode is Pt, Pd, R.
h, Ru, Re, Os, Ir, which is made of at least one or more kinds of materials, and when the lower electrode is produced by a sputtering method, a step of mixing N 2 with a sputtering gas to flatten the surface shape is provided, After that, a dielectric film is formed,
A method of manufacturing a thin film capacitor, which comprises forming an upper electrode. Here, the nitrogen content of the lower electrode is not particularly limited, but in order to maintain good conductivity, it is preferably 10 atomic% or less, and this nitrogen-containing layer is at least when the lower electrode has a multilayer structure. The uppermost layer may be the nitrogen-containing layer.
【０００６】本発明の第２は、基板上に下部電極、誘電
体膜および上部電極を順次積層する薄膜コンデンサの製
造方法であって、下部電極を形成した後、低圧雰囲気中
でＡｒ、Ｎｅ、Ｋｒ、Ｘｅのうち少なくとも１種以上、
あるいはそれにＨ、Ｎ、Ｏ、Ｆの中から１種以上を添加
した混合ガスをイオン化して照射し、下部電極の表面を
平坦化する工程を備え、しかる後に誘電体膜を形成し、
上部電極を形成することを特徴とする薄膜コンデンサの
製造方法である。A second aspect of the present invention is a method of manufacturing a thin film capacitor in which a lower electrode, a dielectric film and an upper electrode are sequentially laminated on a substrate. After forming the lower electrode, Ar, Ne, At least one or more of Kr and Xe,
Alternatively, a step of ionizing and irradiating a mixed gas containing one or more kinds selected from H, N, O, and F to flatten the surface of the lower electrode, and then forming a dielectric film,
A method of manufacturing a thin film capacitor, which comprises forming an upper electrode.
【０００７】本発明の第３は、基板上に層間絶縁膜を形
成した後、該層間絶縁膜にコンタクトを穿ち、コンタク
トホールの埋め込み、下部電極、誘電体膜および上部電
極の堆積を順次行う薄膜コンデンサの製造方法であっ
て、コンタクトホール部を超高真空化学気相成長法（Ｕ
ＨＶ−ＣＶＤ法）によりエピタキシャル成長したシリコ
ンで埋め込むことにより、埋め込みの後のコンタクトホ
ール部表面を平坦化する工程を備え、しかる後に下部電
極、誘電体膜および上部電極を順次形成することを特徴
とする薄膜コンデンサの製造方法である。A third aspect of the present invention is a thin film in which an interlayer insulating film is formed on a substrate, a contact is formed in the interlayer insulating film, a contact hole is filled, and a lower electrode, a dielectric film and an upper electrode are sequentially deposited. A method of manufacturing a capacitor, wherein a contact hole portion is formed by ultra high vacuum chemical vapor deposition (U
The method is characterized by including a step of flattening the surface of the contact hole portion after the burying by burying with silicon epitaxially grown by the HV-CVD method, and thereafter, the lower electrode, the dielectric film and the upper electrode are sequentially formed. It is a method of manufacturing a thin film capacitor.
【０００８】[0008]
【作用】第１の発明では、下部電極に貴金属を用いる場
合、スパッタリングによる作製時にＮを混入させること
により配向性が抑制され、下部電極表面が平坦化され
る。その結果、薄膜コンデンサのリーク電流の低減を実
現できる。また、第２の発明では、高誘電率膜の作製の
前にイオンビームを照射させることで下部電極表面が平
坦化され、薄膜コンデンサのリーク電流の低減が実現さ
れる。また、第３の発明では、層間絶縁膜上に薄膜コン
デンサを作製する際、コンタクトホール部をＵＨＶ−Ｃ
ＶＤ法によるエピタキシャル成長したシリコンで埋める
ことによって、コンタクトホール部表面が平坦化され、
薄膜コンデンサのリーク電流の低減が実現される。In the first aspect of the invention, when a noble metal is used for the lower electrode, the orientation is suppressed by mixing N during the production by sputtering, and the surface of the lower electrode is flattened. As a result, it is possible to reduce the leak current of the thin film capacitor. Further, in the second aspect of the invention, the surface of the lower electrode is flattened by irradiating with an ion beam before the production of the high dielectric constant film, so that the leakage current of the thin film capacitor is reduced. Further, in the third invention, when the thin film capacitor is formed on the interlayer insulating film, the contact hole portion is formed by the UHV-C.
By filling with silicon epitaxially grown by the VD method, the surface of the contact hole is flattened,
Reduction of the leak current of the thin film capacitor is realized.
【０００９】[0009]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。 実施例１ 図１は本発明の請求項１に示した薄膜コンデンサの一例
の断面図である。図中、１０１はシリコン基板、１０２
はＮを含む下部電極のＰｔ、１０３は誘電体のＳｒＴｉ
Ｏ3、１０４は上部電極のＡｌである。ＰｔはＡｒ分圧
が４×１０-3Ｔｏｒｒ、Ｎ2分圧が１×１０-4Ｔｏｒｒ
の混合ガスによるＤＣスパッタリング法により基板温度
は室温で作製した。従来のＡｒガスのみによるスパッタ
と比べて、ＡｒとＮ2の混合ガスでスパッタした場合、
Ｐｔの初期核生成が抑制され、またＮ原子がＰｔの結晶
の格子間に混入するため（１１１）軸方向への配向性も
抑制される。したがって、従来の方法で作製したＰｔ膜
は（１１１）軸配向した、２００オングストローム程度
の柱状構造となり、表面も５０オングストローム以上の
凹凸があるが、本発明の薄膜コンデンサに用いているＰ
ｔ膜は柱状構造を取らず、表面も凹凸が１０オングスト
ローム以下の非常に平坦な膜である。誘電体のＳｒＴｉ
Ｏ3はイオンビームスパッタ法によりビーム電圧１００
０Ｖ、ビーム電流４０ｍＡで作製した。Ａｌは４×１０
-3ＴｏｒｒのＡｒガスのみによるＤＣスパッタリング法
により作製した。Embodiments of the present invention will be described below with reference to the drawings. Example 1 FIG. 1 is a sectional view of an example of the thin film capacitor shown in claim 1 of the present invention. In the figure, 101 is a silicon substrate, and 102 is
Is Pt for the lower electrode containing N, 103 is SrTi for the dielectric
O 3 and 104 are Al of the upper electrode. Pt has an Ar partial pressure of 4 × 10 −3 Torr and an N 2 partial pressure of 1 × 10 −4 Torr.
The substrate temperature was room temperature by the DC sputtering method using the mixed gas of. Compared with the conventional sputtering using only Ar gas, when sputtering using a mixed gas of Ar and N 2 ,
The initial nucleation of Pt is suppressed, and since N atoms are mixed in the lattice of the Pt crystal, the orientation in the (111) axis direction is also suppressed. Therefore, the Pt film produced by the conventional method has a (111) -axis-oriented columnar structure of about 200 angstroms and the surface has irregularities of 50 angstroms or more.
The t film does not have a columnar structure, and the surface is also a very flat film with unevenness of 10 angstroms or less. Dielectric SrTi
The beam voltage of O 3 is 100 by the ion beam sputtering method.
It was manufactured at 0 V and a beam current of 40 mA. Al is 4 × 10
It was prepared by a DC sputtering method using only Ar gas of -3 Torr.
【００１０】図２の（ｂ）は、この構造の薄膜コンデン
サの電圧と電流密度との関係を示したものである。比較
のため、図２（ａ）に、下部電極にＮを含まないＰｔを
用いたほかは、上記実施例と同様の構造のものについて
の関係を示す。下部電極にＮを含むＰｔを用いることに
より、リーク電流が低減されていることがわかる。FIG. 2 (b) shows the relationship between the voltage and the current density of the thin film capacitor having this structure. For comparison, FIG. 2A shows the relationship for the structure similar to that of the above-described example except that Pt containing no N was used for the lower electrode. It can be seen that the leak current is reduced by using Pt containing N for the lower electrode.
【００１１】図３は上記の方法により作製した薄膜コン
デンサの下部電極の断面形状を従来の薄膜コンデンサと
比較して模式的に示した図であり、（ａ）は従来の構
造、（ｂ）は本発明の構造を示したものである。図中、
３０１はシリコン（１００）基板、３０２は下部電極の
Ｐｔ、３０３は下部電極の窒素（Ｎ）含有のＰｔであ
る。Ｎを含むことで従来のＰｔ膜と抵抗率には大きな違
いはなく電極材料として使用できることもわかった。本
実施例では下部電極としてＮ含有のＰｔを用いたが、こ
の他、Ｎ含有のＰｄ、Ｒｈ、Ｒｕ、Ｒｅ、Ｏｓ、Ｉｒで
あってもよい。また下部電極を単層としたが、多層構造
であってもよい。この場合は少なくとも最上層をＮ含有
層とする。FIG. 3 is a diagram schematically showing the cross-sectional shape of the lower electrode of the thin-film capacitor manufactured by the above method in comparison with a conventional thin-film capacitor. (A) is a conventional structure, (b) is 1 shows a structure of the present invention. In the figure,
Reference numeral 301 is a silicon (100) substrate, 302 is a lower electrode Pt, and 303 is a lower electrode Pt containing nitrogen (N). It was also found that by including N, the resistivity was not significantly different from that of the conventional Pt film, and it could be used as an electrode material. In this embodiment, N-containing Pt is used as the lower electrode, but N-containing Pd, Rh, Ru, Re, Os, or Ir may be used. Although the lower electrode has a single layer, it may have a multi-layer structure. In this case, at least the uppermost layer is the N-containing layer.
【００１２】実施例２ 図４は本発明の請求項３による薄膜コンデンサの製造方
法に使用されるイオンビームスパッタ装置の一例の構成
図である。図中、４０１はスパッタ用イオン源、４０２
は基板へのイオン照射用イオン源、４０３はターゲット
のＳｒＴｉＯ3、４０４はＤＣスパッタ法により下部電
極としてＰｔ（５０ｎｍ）／Ｔａ（５０ｎｍ）をコート
したシリコン基板である。ＳｒＴｉＯ3をスパッタする
前に、イオン源４０２を用いてＡｒイオンビームを加速
電圧５０ｅＶ、ビーム電流１００ｍＡで基板に向けて１
時間照射し、表面粗さ約５〜１０オングストローム程度
まで下部電極表面の平坦化を行った。しかる後に、イオ
ン源４０１を用いてＡｒイオンビームで加速電圧１００
０Ｖ、ビーム電流４０ｍＡでＳｒＴｉＯ3４０３のスパ
ッタを２時間行い、誘電体薄膜を形成した。本装置から
取り出した後、上部電極としてＡｌ（５００ｎｍ）を形
成し、薄膜コンデンサの電流−電圧特性を測定したとこ
ろ、図５（ｂ）に示すように、Ａｒイオンビームの照射
を行ったほうが何も平坦化しない場合（図５（ａ））に
比べて、リーク電流を低減することができた。本実施例
ではイオン化ガスとしてＡｒを用いたが、この他、Ｎ
ｅ、Ｋｒ、Ｘｅであってもよく、またこれにＨ、Ｎ、
Ｏ、Ｆの１種以上が添加されていてもよい。Embodiment 2 FIG. 4 is a block diagram of an example of an ion beam sputtering apparatus used in a method of manufacturing a thin film capacitor according to claim 3 of the present invention. In the figure, 401 is an ion source for sputtering, and 402
Is an ion source for irradiating the substrate, 403 is SrTiO 3 as a target, and 404 is a silicon substrate coated with Pt (50 nm) / Ta (50 nm) as a lower electrode by a DC sputtering method. Before sputtering SrTiO 3 , an Ar ion beam was used to direct an Ar ion beam toward the substrate at an acceleration voltage of 50 eV and a beam current of 100 mA using an ion source 402.
Irradiation was performed for a period of time to flatten the lower electrode surface to a surface roughness of about 5 to 10 Å. After that, the ion source 401 is used to accelerate the Ar ion beam to 100
SrTiO 3 403 was sputtered for 2 hours at 0 V and a beam current of 40 mA to form a dielectric thin film. After taking out from this device, Al (500 nm) was formed as the upper electrode, and the current-voltage characteristics of the thin film capacitor were measured. As shown in FIG. 5 (b), what was irradiated with Ar ion beam was The leakage current could be reduced as compared with the case where no flattening was performed (FIG. 5A). In this embodiment, Ar is used as the ionized gas, but in addition to this, N
e, Kr, Xe, and H, N,
One or more of O and F may be added.
【００１３】実施例３ 図６は本発明の請求項４による方法で得られる薄膜コン
デンサの断面構造（図６（ｂ））を従来の方法による場
合図６（ａ）と比較した図である。図中、６０１はシリ
コン基板、６０２はコンタクトホール部のポリシリコ
ン、６０３はコンタクトホール部のエピタキシャル成長
させたシリコン、６０４は下部電極のＰｔ／Ｔａ、６０
５は誘電体のＳｒＴｉＯ3、６０６は上部電極のＡｌ／
ＴｉＮ、６０７は層間絶縁膜である。従来はＬＰ−ＣＶ
Ｄ法により形成したポリシリコンをコンタクトホール部
の埋め込みに用いていたが、図６（ａ）に示すようにコ
ンタクトホール中央部に凹型の窪みが生じたり、ポリシ
リコンのグレインのため表面に２００オングストローム
以上の凹凸が生じていた。本発明では、超高真空ＣＶＤ
法を用い、コンタクトホールの埋め込み前に１０-10Ｔ
ｏｒｒ程度の超高真空まで排気した真空装置内に、Ｓｉ
2Ｈ6ガスを１０-6Ｔｏｒｒ程度導入してコンタクトホー
ル部にシリコンを選択的にエピタキシャル成長させ、不
純物としてＰのドーピングを行った。その結果、表面粗
さが５〜１０オングストローム程度まで平坦化された。
その上に下部電極としてＰｔ／Ｔａを、誘電体としてＳ
ｒＴｉＯ3を、上部電極としてＡｌ／ＴｉＮを形成し、
薄膜コンデンサの電流−電圧特性を従来のポリシリコン
を用いた場合と比較した。その結果が図７である。図
中、（ａ）は従来の方法によって得られた薄膜コンデン
サの特性、（ｂ）は本実施例によって得られた薄膜コン
デンサの特性である。コンタクトホール部にエピタキシ
ャル成長したシリコンを用いることにより、リーク電流
が低減された。Embodiment 3 FIG. 6 is a diagram comparing the cross-sectional structure (FIG. 6B) of a thin film capacitor obtained by the method according to claim 4 of the present invention with FIG. 6A in the case of the conventional method. In the figure, 601 is a silicon substrate, 602 is polysilicon in the contact hole portion, 603 is epitaxially grown silicon in the contact hole portion, 604 is Pt / Ta of the lower electrode, 60
5 is dielectric SrTiO 3 , and 606 is Al / of the upper electrode.
TiN and 607 are interlayer insulating films. Conventionally LP-CV
Although the polysilicon formed by the D method was used for filling the contact hole portion, as shown in FIG. 6A, a concave recess is formed in the central portion of the contact hole, or the grain of the polysilicon causes 200 angstroms on the surface. The above unevenness was generated. In the present invention, ultra high vacuum CVD
Method, 10 -10 T before filling the contact hole
Si in a vacuum system evacuated to an ultra high vacuum of about orr
2 H 6 gas was introduced at about 10 −6 Torr to selectively epitaxially grow silicon in the contact hole portion, and P was doped as an impurity. As a result, the surface roughness was flattened to about 5 to 10 Å.
On top of that, Pt / Ta is used as a lower electrode, and S is used as a dielectric.
Forming Al / TiN using rTiO 3 as the upper electrode,
The current-voltage characteristics of the thin film capacitor were compared with the case of using conventional polysilicon. The result is shown in FIG. In the figure, (a) shows the characteristics of the thin film capacitor obtained by the conventional method, and (b) shows the characteristics of the thin film capacitor obtained by this embodiment. The leak current was reduced by using the epitaxially grown silicon in the contact hole portion.
【００１４】なお、上記３つの実施例では高誘電率膜と
してＳｒＴｉＯ3の例を述べたが、本発明は、高誘電率
膜として化学式がＡＢＯ3で表され、それぞれＡとして
Ｂａ、Ｓｒ、Ｐｂ、Ｌａ、Ｌｉ、Ｋのうち少なくとも１
種以上、ＢとしてＺｒ、Ｔｉ、Ｔａ、Ｎｂ、Ｍｇ、Ｍ
ｎ、Ｆｅ、Ｚｎ、Ｗのうち少なくとも１種以上からなる
もの、例えば、（Ｂａ，Ｓｒ）ＴｉＯ3、ＰｂＴｉＯ3、
Ｐｂ（Ｚｒ，Ｔｉ）Ｏ3、（Ｐｂ，Ｌａ）（Ｚｒ，Ｔ
ｉ）Ｏ3、Ｐｂ（Ｍｇ，Ｎｂ）Ｏ3、Ｐｂ（Ｍｇ，Ｗ）Ｏ
3、Ｐｂ（Ｚｎ，Ｎｂ）Ｏ3、ＬｉＴａＯ3、ＬｉＮｂ
Ｏ3、ＫＴａＯ3、ＫＮｂＯ3など、あるいはそれ以外の
化学式の、Ｔａ2Ｏ5、Ｂｉ4Ｔｉ3Ｏ12、ＢａＭｇＦ4な
どを用いても有効である。In the above three embodiments, the example of SrTiO 3 was described as the high dielectric constant film, but in the present invention, the chemical formula is represented by ABO 3 as the high dielectric constant film, and A, Ba, Sr and Pb, respectively. , La, Li, K at least 1
Seed or more, B as Zr, Ti, Ta, Nb, Mg, M
At least one of n, Fe, Zn, and W, such as (Ba, Sr) TiO 3 , PbTiO 3 ,
Pb (Zr, Ti) O 3 , (Pb, La) (Zr, T
i) O 3 , Pb (Mg, Nb) O 3 , Pb (Mg, W) O
3 , Pb (Zn, Nb) O 3 , LiTaO 3 , LiNb
It is also effective to use O 3 , KTaO 3 , KNbO 3 or the like, or other chemical formulas such as Ta 2 O 5 , Bi 4 Ti 3 O 12 or BaMgF 4 .
【００１５】[0015]
【発明の効果】以上説明したように、本発明によれば下
部電極表面が平坦化され、高誘電率膜を用いた薄膜コン
デンサのリーク電流の増加を抑えることができる。As described above, according to the present invention, the surface of the lower electrode is flattened and the increase of the leak current of the thin film capacitor using the high dielectric constant film can be suppressed.
【図１】本発明による薄膜コンデンサの一例の断面図で
ある。FIG. 1 is a cross-sectional view of an example of a thin film capacitor according to the present invention.
【図２】本発明による薄膜コンデンサの一例の電流−電
圧特性図である。FIG. 2 is a current-voltage characteristic diagram of an example of a thin film capacitor according to the present invention.
【図３】下部電極の断面形状の説明図である。FIG. 3 is an explanatory diagram of a cross-sectional shape of a lower electrode.
【図４】本発明の方法に用いられるイオンビームスパッ
タ装置の一例の構成図である。FIG. 4 is a configuration diagram of an example of an ion beam sputtering apparatus used in the method of the present invention.
【図５】本発明による薄膜コンデンサの一例の電流−電
圧特性図である。FIG. 5 is a current-voltage characteristic diagram of an example of a thin film capacitor according to the present invention.
【図６】本発明による層間絶縁膜上の薄膜コンデンサの
断面図を従来例と比較して示した図である。FIG. 6 is a diagram showing a cross-sectional view of a thin film capacitor on an interlayer insulating film according to the present invention in comparison with a conventional example.
【図７】本発明による薄膜コンデンサの一例の電流−電
圧特性図である。FIG. 7 is a current-voltage characteristic diagram of an example of a thin film capacitor according to the present invention.
１０１ シリコン基板 １０２ Ｎ含有Ｐｔ １０３ ＳｒＴｉＯ3 １０４ Ａｌ ３０１ シリコン（１００）基板 ３０２ Ｐｔ ３０３ Ｎ含有Ｐｔ ４０１ スパッタ用イオン源 ４０２ イオン照射用イオン源 ４０３ ＳｒＴｉＯ3 ４０４ シリコン基板 ６０１ シリコン基板 ６０２ ポリシリコン ６０３ エピタキシャル成長シリコン ６０４ Ｐｔ／Ｔａ ６０５ ＳｒＴｉＯ3 ６０６ Ａｌ／ＴｉＮ ６０７ 層間絶縁膜101 Silicon substrate 102 N-containing Pt 103 SrTiO 3 104 Al 301 Silicon (100) substrate 302 Pt 303 N-containing Pt 401 Sputtering ion source 402 Ion irradiation ion source 403 SrTiO 3 404 Silicon substrate 601 Silicon substrate 602 Polysilicon 603 Epitaxial growth silicon 604 Pt / Ta 605 SrTiO 3 606 Al / TiN 607 Interlayer insulating film
Claims (4)
電極を順次積層した薄膜コンデンサであって、下部電極
の少なくとも最表面層が窒素を含有するＰｔ、Ｐｄ、Ｒ
ｈ、Ｒｕ、Ｒｅ、Ｏｓ、Ｉｒのうち少なくとも１種以上
の材料からなり、誘電体が誘電率の大きな高誘電率膜か
らなることを特徴とする薄膜コンデンサ。1. A thin film capacitor in which a lower electrode, a dielectric film and an upper electrode are sequentially laminated on a substrate, wherein at least the outermost surface layer of the lower electrode contains Pt, Pd, R.
A thin film capacitor comprising at least one material selected from the group consisting of h, Ru, Re, Os and Ir, and having a high dielectric constant film as a dielectric.
電極を順次積層した薄膜コンデンサの製造方法であっ
て、下部電極の最表面層がＰｔ、Ｐｄ、Ｒｈ、Ｒｕ、Ｒ
ｅ、Ｏｓ、Ｉｒのうち少なくとも１種以上の材料からな
り、該下部電極をスパッタリング法により作製する際、
スパッタガスにＮ2を混合し、表面形状を平坦化する工
程を備え、しかる後に誘電体膜を形成し、上部電極を形
成することを特徴とする薄膜コンデンサの製造方法。2. A method of manufacturing a thin film capacitor in which a lower electrode, a dielectric film and an upper electrode are sequentially laminated on a substrate, wherein the outermost surface layer of the lower electrode is Pt, Pd, Rh, Ru, R.
e, Os, or Ir, which is made of at least one kind of material, and when the lower electrode is formed by a sputtering method,
A method of manufacturing a thin film capacitor, comprising a step of mixing a sputtering gas with N 2 to flatten a surface shape, and thereafter forming a dielectric film and forming an upper electrode.
電極を順次積層する薄膜コンデンサの製造方法であっ
て、下部電極を形成した後、低圧雰囲気中でＡｒ、Ｎ
ｅ、Ｋｒ、Ｘｅのうち少なくとも１種以上、あるいはそ
れにＨ、Ｎ、Ｏ、Ｆの中から１種以上を添加した混合ガ
スをイオン化して照射し、下部電極の表面を平坦化する
工程を備え、しかる後に誘電体膜を形成し、上部電極を
形成することを特徴とする薄膜コンデンサの製造方法。3. A method of manufacturing a thin film capacitor, in which a lower electrode, a dielectric film and an upper electrode are sequentially laminated on a substrate, wherein after the lower electrode is formed, Ar, N in a low pressure atmosphere.
a step of ionizing and irradiating a mixed gas containing at least one of e, Kr, and Xe or one or more of H, N, O, and F to flatten the surface of the lower electrode. A method of manufacturing a thin film capacitor, characterized by forming a dielectric film and then forming an upper electrode.
間絶縁膜にコンタクトを穿ち、コンタクトホールの埋め
込み、下部電極、誘電体膜および上部電極の堆積を順次
行う薄膜コンデンサの製造方法であって、コンタクトホ
ール部を超高真空化学気相成長法（ＵＨＶ−ＣＶＤ法）
によりエピタキシャル成長したシリコンで埋め込むこと
により、埋め込みの後のコンタクトホール部表面を平坦
化する工程を備え、しかる後に下部電極、誘電体膜およ
び上部電極を順次形成することを特徴とする薄膜コンデ
ンサの製造方法。4. A method for manufacturing a thin film capacitor, which comprises forming an interlayer insulating film on a substrate, forming a contact in the interlayer insulating film, filling a contact hole, and depositing a lower electrode, a dielectric film and an upper electrode in order. Therefore, the contact hole part is formed by ultra-high vacuum chemical vapor deposition (UHV-CVD method).
A method for manufacturing a thin film capacitor, characterized by comprising a step of flattening the surface of the contact hole portion after filling by epitaxially growing silicon by filling the lower electrode, the dielectric film and the upper electrode in this order. ..
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04083172A JP3125425B2 (en) | 1992-03-05 | 1992-03-05 | Thin film capacitor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04083172A JP3125425B2 (en) | 1992-03-05 | 1992-03-05 | Thin film capacitor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05251258A true JPH05251258A (en) | 1993-09-28 |
| JP3125425B2 JP3125425B2 (en) | 2001-01-15 |
Family
ID=13794867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04083172A Expired - Fee Related JP3125425B2 (en) | 1992-03-05 | 1992-03-05 | Thin film capacitor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3125425B2 (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202296A (en) * | 1992-02-25 | 1993-04-13 | Osborne Don M | Chemically treated air filter for enriching the oxygen present in an airstream |
| WO1998039801A1 (en) * | 1997-03-03 | 1998-09-11 | Symetrix Corporation | Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures |
| US5852307A (en) * | 1995-07-28 | 1998-12-22 | Kabushiki Kaisha Toshiba | Semiconductor device with capacitor |
| JPH11163271A (en) * | 1997-11-28 | 1999-06-18 | Rohm Co Ltd | Manufacture of capacitor |
| JPH11214853A (en) * | 1997-11-21 | 1999-08-06 | Sony Corp | Manufacture of wiring board |
| WO2000001000A1 (en) * | 1998-06-30 | 2000-01-06 | Matsushita Electronics Corporation | Dc sputtering process for making smooth electrodes and thin film ferroelectric capacitors having improved memory retention |
| JP2002134710A (en) * | 1994-01-13 | 2002-05-10 | Rohm Co Ltd | Dielectric capacitor |
| JP2002261252A (en) * | 1994-01-13 | 2002-09-13 | Rohm Co Ltd | Ferroelectric capacitor |
| USRE38565E1 (en) * | 1997-03-03 | 2004-08-17 | Matsushita Electric Industrial Co., Ltd. | Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures |
| JP2006319357A (en) * | 1994-01-13 | 2006-11-24 | Rohm Co Ltd | Process for fabricating dielectric capacitor |
| JP2006319358A (en) * | 1994-01-13 | 2006-11-24 | Rohm Co Ltd | Ferroelectric capacitor and its fabrication process |
| JP2007134711A (en) * | 2005-11-07 | 2007-05-31 | Samsung Electro Mech Co Ltd | Printed circuit board incorporating thin film capacitor and manufacturing method of the same |
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1992
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Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202296A (en) * | 1992-02-25 | 1993-04-13 | Osborne Don M | Chemically treated air filter for enriching the oxygen present in an airstream |
| JP2006319358A (en) * | 1994-01-13 | 2006-11-24 | Rohm Co Ltd | Ferroelectric capacitor and its fabrication process |
| JP2002134710A (en) * | 1994-01-13 | 2002-05-10 | Rohm Co Ltd | Dielectric capacitor |
| JP2002261252A (en) * | 1994-01-13 | 2002-09-13 | Rohm Co Ltd | Ferroelectric capacitor |
| JP2006319357A (en) * | 1994-01-13 | 2006-11-24 | Rohm Co Ltd | Process for fabricating dielectric capacitor |
| US6156599A (en) * | 1995-07-28 | 2000-12-05 | Kabushiki Kaisha Toshiba | Method of making a semiconductor device with capacitor |
| US5852307A (en) * | 1995-07-28 | 1998-12-22 | Kabushiki Kaisha Toshiba | Semiconductor device with capacitor |
| US6265738B1 (en) | 1997-03-03 | 2001-07-24 | Matsushita Electronics Corporation | Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures |
| US6440754B2 (en) | 1997-03-03 | 2002-08-27 | Matsushita Electric Industrial Co., Ltd. | Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures |
| WO1998039801A1 (en) * | 1997-03-03 | 1998-09-11 | Symetrix Corporation | Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures |
| USRE38565E1 (en) * | 1997-03-03 | 2004-08-17 | Matsushita Electric Industrial Co., Ltd. | Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures |
| JPH11214853A (en) * | 1997-11-21 | 1999-08-06 | Sony Corp | Manufacture of wiring board |
| JPH11163271A (en) * | 1997-11-28 | 1999-06-18 | Rohm Co Ltd | Manufacture of capacitor |
| JP2005311385A (en) * | 1998-06-30 | 2005-11-04 | Matsushita Electric Ind Co Ltd | Dc-sputtering process for manufacturing thin-film ferroelectric capacitor having smoothing electrode and improved memory retentivity |
| US6541375B1 (en) | 1998-06-30 | 2003-04-01 | Matsushita Electric Industrial Co., Ltd. | DC sputtering process for making smooth electrodes and thin film ferroelectric capacitors having improved memory retention |
| WO2000001000A1 (en) * | 1998-06-30 | 2000-01-06 | Matsushita Electronics Corporation | Dc sputtering process for making smooth electrodes and thin film ferroelectric capacitors having improved memory retention |
| JP2007134711A (en) * | 2005-11-07 | 2007-05-31 | Samsung Electro Mech Co Ltd | Printed circuit board incorporating thin film capacitor and manufacturing method of the same |
| US7675756B2 (en) | 2005-11-07 | 2010-03-09 | Samsung Electro-Mechanics Co., Ltd. | Thin film-capacitor-embedded printed circuit board and method of manufacturing the same |
| US7886436B2 (en) | 2005-11-07 | 2011-02-15 | Samsung Electro-Mechanics Co., Ltd. | Thin film capacitor-embedded printed circuit board and method of manufacturing the same |
| US7929272B2 (en) | 2006-06-06 | 2011-04-19 | Tdk Corporation | Thin film capacitor |
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