JPH05236502A - Video display device - Google Patents

Abstract

PURPOSE:To reduce the number of parts for automatic cut-off adjustment and the number of required pins of an IC to realize the efficiency with respect to cost and production process and to make the speed of cut-off adjustment high. CONSTITUTION:A reference pulse (RPR, RPG, or RPS) is added to a prescribed position in each field of a video signal, and the cathode current obtained by this addition is converted to a pulse voltage and the pulse voltage is compared with a comparison reference voltage by a comparator 17, and the comparison output is counted by an up/down counting means (18R, 18G, or 18B) and is subjected to D/A conversion, and the DC component of the video signal is controlled in a level shift circuit (12R, 12G, or 12B) by this D/A conversion output voltage to control the cut-off characteristic, and the counting operation of the up/down-counting means (18R, 18G, or 18B) is executed based on count pulses supplied in plural units in one field in the case of a set prescribed period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a television receiver,
The present invention relates to a video display device such as a monitor device, and more particularly to a video display device capable of automatically controlling the cutoff characteristic of a CRT.

[0002]

2. Description of the Related Art As is well known, in an image display device such as a television receiver, R, G and B phosphors are arranged in a CRT (cathode ray tube) according to a predetermined rule. The body displays an image by emitting light from the beam from each electron gun based on the R, G, and B image signals.

By the way, the CRT including the electron gun has a large manufacturing variation, and the characteristics of the R, G, and B phosphors are not all uniform and are different from each other, so that the cutoff point at which the phosphor emits light. Are R, G, and B, and are mixed. The cut-off characteristic (light emission characteristic) is represented by the cathode current with respect to the cathode voltage, which is shown in FIG.
5 shows. As can be seen from this figure, the cutoff characteristics do not match in the R, G, and B channels. Note that FIG.
Is just an example, and the cutoff points are not always in the order of R, G, B in the order of increasing cathode voltage.
The cutoff characteristics are quite irregular for each CRT.

In order to match the cutoff points that do not match as described above, adjustment in the production process is necessary.
That is, a level shift circuit, a gain control circuit, etc. are provided in the signal processing / amplification circuit system for each of the R, G, and B video signal channels, and these are adjusted so that the cutoff characteristics of each channel match. I was doing

Further, in order to reduce such a cutoff adjustment process and a gain control circuit, an automatic cutoff adjustment system for automatically performing the cutoff adjustment has been proposed. FIG. 16 shows a circuit block of a main part of a television receiver adopting the conventional automatic cutoff adjustment method.

When the supplied video signal is demodulated into an R signal, a G signal and a B signal by a demodulation circuit system (not shown), R,
The G and B signals are switched circuits 1R, 1G and 1B, respectively.
Is supplied to. In the switch circuits 1R, 1G, 1B,
R, G, reference pulses RP _R in different predetermined positions in the vertical blanking interval of each signal as the B signals shown in FIG. 17, RP _G, is RP _B is added.

[0007] In this way the reference pulse RP _{R, R}
The signal to which P _G and RP _B are added is the level shift circuit 2
Drive circuit 3R, 3G, 3B via R, 2G, 2B
And the electron gun is driven. Of course, it goes without saying that the video display is performed by the signals in the video signal section supplied to the drive circuits 3R, 3G, 3B.
The internal structure of the drive circuits 3G and 3B is the same as that of the drive circuit 3R, so that the illustration thereof is omitted. 4 indicates a CRT.

Here, pay attention to the reference pulses RP _R , RP _G , and RP _B added within the vertical blanking period. Reference pulses like the video signal portion RP _R, RP
_G and RP _B are also amplified by the transistor Q ₁ , and cathode currents R _IK , G _IK and B _{IK of} the CRT are obtained.
The cathode currents R _IK , G _IK and B _IK are applied to the transistor P ₁
Will be detected by the switch circuit 5R, 5G, 5B and will flow to the resistor R ₁ . Here, the switch circuits 5R, 5G and 5B are respectively provided with the reference pulse RP.
_R, RP _G, are controlled so that the contacts are closed only during a period corresponding to the RP _B, hence the resistance R _1,
As shown in FIG. 18, a voltage having three pulses corresponding to the cathode current by the reference pulses RPR, RPG, and RPB of _R , _G , and _B is obtained.

This pulse voltage is input to the clamp circuit 6 via the clamp capacitor C _{1 so} that the voltage of the clamp pulse section obtained from the clamp pulse generator 6a becomes V ₁ (see FIG. 18). It is clamped by pulling current in and out of C ₁ . The clamped pulse voltage is time-sequentially changed by the switch circuit 7 by the comparators 8R, 8G, corresponding to R, G, B, respectively.
8B is distributed and supplied.

[0010] Comparator 8R, 8G, 8B in is [Delta] V ₁ higher voltage to voltages V ₁ to the other terminal (V ₁ + _{ΔV 1)} is supplied as a comparison reference voltage, DC level is clamped to V ₁ Each pulse voltage present is compared to this.

Each of the comparators 8R, 8G, and 8B is controlled so as to perform a comparison operation only during a period when the pulse voltage is supplied, and the comparison output includes a differential value containing an error value between the pulse voltage and the reference voltage. It is configured so that an amplifier-like output can be obtained. This comparator 8
R, 8G, the comparison output of the 8B (i.e. [Delta] V ₁ = current such that [Delta] V ₁ ') each sample hold capacitor C _2R, C _2G, is supplied to the C _2B, the sample hold capacitor C _2R, C _2G, C _2B The voltage held at is supplied as a control voltage to each of the level shift circuits 2R, 2G, 2B.

That is, on the basis of the voltages held in the sample and hold capacitors C _2R , C _2G and C _2B , the level shift circuits 2R, 2G and 2B respectively output R and
G, the black level of the B signal is the reference pulse RP _R, R
The automatic cutoff adjustment is realized by controlling the heights of P _G and RP _B to be equal to each other.

[0013]

The conventional automatic cutoff adjusting circuit as described above has the following problems.

The portion 10 surrounded by the alternate long and short dash line in FIG. 16 is usually constructed in one IC,
The sample and hold capacitors C _2R , C _2G and C _2B must be connected as external parts to the IC. For this reason, the number of parts increases and three extra IC connecting pins are used, which is inefficient in terms of cost and manufacturing process.

Further, the pin to which the sample and hold capacitors C _2R , C _2G and C _2B are connected has a very high impedance because a current flows only in the reference pulse section (1H) in one field. However, when the impedance of the substrate is lowered due to a change with time, a leak current is generated, which causes the sample-hold operation of the sample-hold capacitors C _2R , C _2G , and C _2B to not be normally maintained.

[0016]

The present invention has been made in view of the above problems, and a reference pulse is added to a predetermined position for each field of a video signal, and a cathode current obtained by the reference pulse is added. In a video display device adapted to convert the pulse voltage into a pulse voltage and compare the pulse voltage with a predetermined reference voltage to obtain the control information of the cutoff characteristic of the CRT. By having the counting means, the D / A converting means for converting the output of the up / down counting means into an analog signal, and the level shifting means for controlling the DC component of the video signal by the output voltage of the D / A converting means. The cut-off characteristics can be controlled and up / down The und means provides the video display device configured to execute the count operation for the output of the comparison means based on the count pulse supplied in a plurality of units during one field during the set predetermined period. .

Further, for the up / down count means, from the power-on state to the time when the video display operation in the CRT becomes stable, the output of the comparison means is based on the count pulse supplied in plural units during one field. The count operation is executed and the CRT
The stable time point of the video display operation is determined by detecting the cathode currents of all R, G, and B and counting operation up to a predetermined count value starting from the cathode current detection time point.

[0018]

Operation: Up / down counting of comparison information between a pulse voltage converted from a cathode current based on a reference pulse once in one field and a predetermined comparison reference voltage,
By converting this count output into an analog signal, the output value is held for one field. That is, the control information for the level shift means can be obtained without using the sample / hold consensus sensor.

Further, when the CRT operation is unstable, there is often a considerable voltage difference between the pulse voltage and the comparison reference voltage, which causes the convergence time of the cutoff loop to be prolonged. In such a case, By performing the up / down count operation a plurality of times for one field, the convergence time of the cutoff loop can be shortened.

[0020]

EXAMPLES Hereinafter, referring to FIGS. 1 to 14, (A) automatic cutoff adjustment operation, (B) comparison reference hysteresis voltage supply operation, (C) operation of superimposing a reverse polarity signal on a D / A conversion output, ( An embodiment of the image display device of the present invention will be described in the order of D) a color temperature adjustment operation outside the automatic cutoff loop, and (E) a high speed stabilization operation of cutoff adjustment by counter pulse control. In addition, in the description of this embodiment, as shown in FIG.
FIG. 18 is incorporated.

(A) Automatic cut-off adjustment operation FIG. 1 is a block diagram showing a main part of a television receiver as an embodiment.
B is a switch circuit, and the demodulated R signal, G signal,
As shown in FIG. 17, the reference pulse RP is applied to a predetermined portion of the vertical blanking period different from that of the B signal.
_R , RP _G , and RP _B are added. 12R, 12G, 12
B is a level shift circuit, which controls the black level of the video signal and adjusts the cutoff characteristics of the R, G, and B channels, as will be described later.

Level shift circuits 12R, 12G, 12B
Outputs are drive circuits 13R, 13G, 13B, respectively.
Is supplied to the CRT 14 and amplified by the transistor Q _1.
R, G, B electron guns are driven, and cathode currents R _IK , G _IK , B _IK are applied to the transistor P ₁
It is designed to be detected by.

The cathode currents R _IK , G _IK and B _IK flow into the resistor R ₁ via the switch circuits 15R, 15G and 15B. Switch circuits 15R, 15G, 15B is the reference pulse RP each _R, RP _G, are controlled so that the contacts are closed only during a period corresponding to the RP _B, therefore the resistor R _1, as shown in FIG. 18 R , G, the reference pulse RP _R of B, RP _G, R
A voltage with three pulses is obtained, which corresponds to the cathode current due to P _B.

This pulse voltage is input to the clamp circuit 16 via the clamp capacitor C _{1 so} that the voltage of the clamp pulse section obtained from the clamp pulse generator 6a becomes V ₁ (see FIG. 18). It is clamped by pulling current in and out of C ₁ . Figure 2
The pulse voltage clamped as shown in (a) is supplied to the comparator 17.

A voltage (V ₁ +) higher than the voltage V ₁ by ΔV ₁ is applied to the other terminal of the comparator 17 as a comparison reference voltage.
ΔV ₁ ) is supplied and each pulse voltage whose DC level is clamped to V ₁ is compared with this, and “H (5
V) ”or“ L (0V) ”(Fig. 2
(See (b)).

The comparison output of the comparator 17 is supplied to the up / down counter units 18R, 18G and 18B. Then, the up / down counter units 18R, 18
In G and 18B, the count clocks R _CK , G _CK , and B _CK are given as shown in FIGS. 2C to 2E in the period corresponding to the reference pulse of each channel, and based on this, the comparator 17 If the output is "H", up-counting is performed, and if it is "L", down-counting is performed. It should be noted that FIGS. 2F to 2H show only the LSB of the count output. Reference numerals 19R, 19G, and 19B denote D / A converters that convert the outputs of the up / down counter units 18R, 18G, and 18B into analog signals.

Up / down counter units and D / A converters (18R, 19R) (18G, 19G) (18B, 1)
9B) is specifically configured as shown in FIG. 3, for example. That is, the output from the comparator 17 is first input to the data terminal of the D flip-flop 30, the count clocks (R _CK , G _CK , B _CK ) are used as the latch clocks, and the supplied comparison output is latched. Is output. Then, the latch output is supplied to the up / down counter 31. In this way, by counting the latch output, the influence of the waveform rounding of the output of the comparator 17 can be removed.

In this case, the count clocks (R _CK , G _CK ,
B _CK ) is supplied through the inverter 32, and counts at the rising edge of the output of the inverter 32. In the up / down counter 31, for example, 8-bit counting operation is performed, and the count output is the resistance r ₀ to
It is output as an analog voltage value by the D / A converter composed of r ₁₅ . The inverter 33 and the switch circuit 34 will be described later.

In this way, the voltage which is up / down-counted based on the comparison operation of the comparator 17 is converted into an analog voltage, that is, D / for each of the R, G and B channels.
The outputs of the A converters 19R, 19G and 19B are supplied as control voltages to the level shift circuits 12R, 12G and 12B, respectively. That is, in each of the level shift circuits 12R, 12G, and 12B, R, G, and
The black level of the B signal is the reference pulse RP _R, RP
_{By controlling} the heights of _G and RP _B to be equal to each other (that is, the voltage ΔV ₁ 'in FIG. 18 is equal to ΔV ₁ ), the automatic cutoff adjustment is realized.

Therefore, the up / down counter 31 initially continues to count up or down in each field, but converges to repeat upcounting and downcounting for each field after a predetermined time point. That is, the automatic cutoff adjustment operation is stable at this point.

In this embodiment, since the circuit within 10 surrounded by the one-dot chain line can be constructed in one IC,
In order to realize the automatic cutoff adjustment operation, an external sample hold capacitor as in the conventional example shown in FIG. 16 is unnecessary. Therefore, in the present embodiment, reduction of the number of pins required for the IC, reduction of elements, etc. are realized, and efficiency is improved in terms of cost, manufacturing process and the like. In addition, the operation of the external sample-hold capacitor cannot be normally maintained due to the influence of the change over time, and the automatic cutoff adjustment operation does not become unstable.

(B) Comparison Reference Hysteresis Voltage Supply Operation When the automatic cutoff adjustment operation is stable, conversely, such an up / down counter 31 is used.
The up-counting and down-counting must be accurately repeated. For this purpose, the output of the comparator 17 is the reference pulse RP _R , RP _G , RP _B (reference pulse for each field) of each field. The condition is that the output of "L" and "H" is repeated for the pulse voltage corresponding to the cathode current detected by.

However, in the stable state, the pulse voltage for each field is a value very close to the comparison reference voltage,
The difference is not large enough. Therefore, for example, there is a possibility that an error is likely to occur in the comparison operation in the comparator 17 due to the influence of noise or the like. Since the probability of occurrence of this malfunction is random, the white balance is momentarily collapsed by the malfunction and color flicker appears on the screen.

Therefore, in this embodiment, the comparator 17
A hysteresis voltage circuit 20R, 20G, 20B for controlling the comparison reference voltage (V ₁ + ΔV ₁ ) supplied to the switch circuit 21 and a switch circuit 21 are provided. Actually, the hysteresis voltage circuits 20R, 20G, 20B and the switch circuit 21 are 40 in FIG. 4, that is, an OR gate 41 and a resistor R.
₂ and the power supply unit (V ₁ + ΔV for the above-mentioned comparison reference voltage)
₁ ) and a resistor R ₃ .

The D flip-flop in the preceding stage of the OR gate 41 corresponds to the D flip-flop 30 in FIG. That is, each of the up / down counter units 18
The D flip-flop 30 in R, 18G, 18B is shown.

The comparator 17 includes transistors P ₁₁ and P
_{The 12} differential pairs compare the comparison reference voltage (V ₁ + ΔV ₁ ) supplied to the base side of the transistor P ₁₁ with the pulse voltage supplied to the base side of the transistor P ₁₂ , and the comparison output is the transistor Q ₁₃ However, as described above, the comparison output is supplied to the D flip-flop 30 in each of the up / down counter units 18R, 18G, 18B, and the latch is supplied only in the reference pulse section. Clock R _CK , G
It is latched based on _CK and _BCK . The latch output (that is, 5V output or 0V output) of the D flip-flop 30 is supplied to the up / down counter 31 as shown in FIG. 3 and is also supplied to the OR gate 41 as shown in FIG. Then, the resistors R ₂ and R ₃ add the original comparison reference voltage (V ₁ + ΔV ₁ ) by resistance division.

As a result, as shown by the dotted line in FIG. 5A, the comparison reference voltage is the first voltage V which is relatively high after the latch output of the D flip-flop 30 becomes "H".
_R1 is reached, and after the latch output of the D flip-flop 30 becomes "L", the second voltage V _R2 becomes relatively low. 5B, 5C, and 5D, the pulse voltage supplied to the comparator 17, the latch clock,
The D flip-flop output is represented by R,
Only one channel of G and B is shown.
Therefore, actually, the comparison reference voltage of FIG. 5A also has a waveform in which three channels are combined.

The comparison reference voltage is such, that is, the time t _L comparator 17 to be output to "L", the comparison reference voltage V _R1, and the time comparator 17 to be output to "H" t _H The comparison reference voltage _rises and falls based on the output of the comparator 17 so that the comparison reference voltage becomes VR2. In the state in which the comparison result of "L" should be output, the comparison operation is stable and hardly affected by noise or the like.

(C) Superimposing Operation of Reverse Polarity Signal on D / A Converted Output Now, in this embodiment, each channel corresponding to each of R, G, and B channels in a state where the auto cutoff loop is stable. The least significant bit of the up / down counter 31 repeats "L" and "H" for each field, but this is the variation of the least significant bit (that is, the D / A converter 19R, 19G,
The level shift circuit 12R, 12G, 12B is level-shifted by the amount of change in the voltage value of the minimum bit of 19B). Therefore, the black level of the video signal fluctuates up and down for each field, and this state is the same for each of the R, G, and B channels, so that a luminance flicker appears on the screen and the influence appears.

Therefore, in the present embodiment, only in the video signal section, the change amount of the voltage value of the minimum bit of the D / A converters 19R, 19G, 19B is added to the output of the D / A converters 19R, 19G, 19B. By overlapping with opposite polarities, the occurrence of luminance flicker is prevented. This will be described with reference to FIG. 3 again and with reference to FIG.

As described above, the output of the comparator 17 is the latch clock (and the count clock via the inverter 32) R _CK , G in each of the R, G, B channels.
_It is latched by the D flip-flop 30 on the basis of _CK and _BCK , and is counted by the up / down counter 31, the state of which is as shown in FIGS. Here, the polarity of the up / down counter 31 is "H" for up, and "L" for down. The output of the up / down counter 31 is a D / A composed of resistors r _{0 to} r _15.
Although it is sent to the converters (19R, 19G, 19B), the resistor r ₀ is normally grounded by connecting the switch circuit 34 to the ground terminal, and in that state, the D / A converters (19R, 19G, 19B, The output (corresponding to the least significant bit) of 19B) is as shown in FIG. And this D / A
Level shift circuit (12R, 12
The amount of level shift in G, 12B) is controlled.

Here, the switch circuit 34 is connected to the inverter 3
3 is connected to the terminal and the signal of FIG.
When the inverted signal of FIG. 6 (e) is supplied to the resistor r ₀ through 3, the output of the D / A converter (19R, 19G, 19B) becomes as shown in FIG. 6 (f). In 6 (d), the correction waveform is such that the portion that is at the L level (hatched portion) in the video signal section is filled up. That is,
The change in the least significant bit in the output of the D / A converter (19R, 19G, 19B) is canceled. As a result, the black level is kept constant in the video signal section, and the occurrence of luminance flicker on the screen is prevented.

However, if such a correction is made in the reference pulse section (= vertical retrace section) shown in FIG. 6 (g), the automatic cutoff operation itself will not be carried out, so this reference pulse No correction is applied only to the section. That is, the switch circuit 34
The reference pulse section is grounded, and the video signal section section is controlled to connect the inverter 33. By this, the actual D / A converter (19R, 1
The output of 9G, 19B) is as shown in FIG.

Of course, even if the output of the inverter 33 is added to the grounded resistor r ₀ to perform the above correction, the precision of 1 bit as the level shift control voltage is not affected. FIG. 7 shows D / when no correction operation is performed.
The output of the A converter (corresponding to LSB) is shown by a dotted line, and the output of the D / A converter (corresponding to LSB) when the correction operation is executed is shown by a solid line.

(D) Color temperature adjusting operation outside the automatic cut-off loop By the way, reference numeral 22 shown in FIG. 1 indicates a switch circuit provided for adjusting the color temperature, and the color temperature adjustment is carried out at each level shift. The circuits 12R, 12G, and 12B control the color temperature adjustment voltage V ₃ to change the DC shift amount of the video signal. However, when controlling the color temperature adjustment voltage V ₃ at the reference pulse section to control the loop of the automatic cutoff that has been described above, the reference pulse RP _R, RP _G, R
The height of P _B also changes, and the automatic cutoff adjustment operation does not work properly. Therefore, in the reference pulse section, the switch circuit 22 is controlled so as to select the fixed voltage V ₄ .

Hereinafter, each level shift circuit 12R, 1 will be described.
The color temperature adjustment executed in 2G and 12B will be described. Even if the R, G, and B emission points are matched to some extent by the automatic cutoff adjustment operation, color temperature adjustment is necessary to make the delicate appearance of white uniform on this CRT.

For this reason, in the conventional automatic cutoff adjustment method shown in FIG. 16, the color temperature is adjusted by finely setting the comparison reference voltages of the comparators 8R, 8G, 8B of each channel. That is, in the case of the circuit of FIG. 16, when the value of ΔV ₁ is controlled and the comparison reference voltage is changed, the height of the pulse voltage at which the cathode current (R _IK , G _IK , B _IK ) is detected is increased by the cutoff adjustment loop. changes, As a result, R, G, reference pulses RP _R and B each channel, RP _G, the height of the RP _B changes.
The black level of the video signal is the reference pulse RP.
_R, since they are to be adjusted in RP _G, based on the RP _B, it is possible to adjust the color temperature by setting the comparison reference voltage. The control of the comparison reference voltage for adjusting the color temperature is executed by a control signal supplied from a system control unit (not shown) via a bus.

However, in the case of the present embodiment, it is not preferable to execute the color temperature adjustment in the cutoff adjustment loop in this way. This is because the D / A converter (19R,
19G, 19B) output the reference pulse RP
_R, RP _G, but by controlling the height of the RP _B, necessarily a D / A converter (19R, 19G, 19B) the resolution of the bus control signals for bit resolution and color temperature adjustment, consistent Because there is no.

For example, in the relationship between the cathode current of the CRT and the RGB output (= input of the drive amplifier of the CRT) shown in FIG. 8, the dynamic range of the cathode current required for the automatic cutoff adjustment operation is defined as section A. Where D
Assuming that the bit resolution of the A / A converters (19R, 19G, 19B) is ΔV _1B by the solid line and the resolution of the bus control signal for adjusting the color temperature is ΔV _2B by the dotted line, even if the color temperature adjustment is instructed by the bus control signal. Actually, the black level of the video signal is adjusted by the D / A converter (19R,
Since it depends on the bit resolution of (19G, 19B), there is a dead zone for the color temperature adjustment, and the accuracy becomes rough.

Therefore, in the present embodiment, the color temperature adjustment is performed outside the automatic cutoff adjustment loop by the level shift circuit 1.
Using the color temperature adjustment voltage V ₃ for 2R, 12G and 12B,
I try to control it. Each level shift circuit 12R, 12G, 12B in this embodiment is, for example, as shown in FIG.
It is configured like.

In this circuit, video signals (R signal, G signal, B signal) are input to the base of the transistor Q ₂₁ . The video signal output is obtained from the emitter of the transistor Q ₂₁ through R _20, R _21. Here, the control voltage for the automatic cutoff adjustment, that is, the D / A converter (19
The outputs of R, 19G and 19B) are input to the base of the transistor Q ₂₅ and converted into a current I ₂ . Transistor Q
_{Since 23} and Q _{24 form} a current mirror circuit, the current I ₂ flows through the resistors R ₂₀ and R ₂₁ .

On the other hand, the color temperature adjusting voltage V ₃ or the fixed voltage V
_The current I ₁ due to ₄ flows through the resistor R ₂₀ . This resistance R ₂₀ ,
R ₂₁ has a function of shifting the DC level of the video signal, and the DC shift amount is determined by the current flowing through the resistors R ₂₀ and R ₂₁ .

Here, the transistor Q ₂₂ is an amplifier with a grounded base, and the potential of the emitter is about 0.4 V. Therefore, the value of the current I ₁ is determined by the values of the color temperature adjustment voltage V ₃ and the resistors R ₂₂ , R ₂₃ . In this case, the resistance R ₂₂ ,
Since the value of R ₂₃ is fixed, the value of the current I ₁ is controlled by the value of the color temperature adjustment voltage V ₃ . Current I ₁ when the color temperature adjustment voltage V ₃ is changed from 1.5 to 3.5 V when the resistance R ₂₂ is 30 kΩ and the resistance R ₂₃ is 2 kΩ.
The change of is shown in FIG. In this way, the color temperature can be adjusted by changing the value of the current I ₁ flowing through the resistor R ₂₀ . The adjustment of the current I ₁ , that is, the adjustment of the color temperature adjustment voltage V ₃ is performed by the D / A converter (19R, 19G, 19).
Since it does not depend on the bit resolution of B), the color temperature adjustment accuracy is not limited by using the D / A converter, and the adjustment accuracy can be set as desired by the accuracy of the bus control. ..

The actual DC level shift amount, that is, the level shift amount of the level shift circuit (12R, 12G, 12B) is the current I flowing through the resistors R ₂₀ and R _21.
It will also depend on the value of ₂ . That is, the video signal input from the transistor Q ₂₁ is level-shifted and output by the voltage effect of {(I ₁ + I ₂ ) × R ₂₀ + I ₂ × R ₂₁ }.

As described above, in the level shift circuit (12R, 12G, 12B) in this embodiment, the current I ₂ determined by the automatic cutoff adjustment loop and the current I ₁ determined by the color temperature adjustment voltage V ₃ are used. Although the level shift control systems independent of each other are configured, as described above, the reference pulse section is used in the switch circuit 2
Since 2 selects the fixed voltage V ₄ , the color temperature adjusting operation does not interfere with the automatic cutoff adjusting operation.

(E) High-speed stabilization operation of cutoff adjustment by counter pulse control In the case of the above embodiment, the reference pulse RP
_R, RP _G, RP _B are added once per field, the pulse voltages corresponding to cathode current detected by the reference pulse is also obtained once per field are input to the comparator 17. The comparison output is the up / down count units 18R, 18G, 18B.
In this case, one field count operation is performed. Therefore, the level shift operation for the cutoff adjustment is controlled with a width corresponding to the minimum bit of the D / A converter output per field.

On the other hand, in an actual CRT, it takes some time for the heater to warm up and the beam emission from the electron gun to stabilize after the power is turned on. During this period, in particular, based on the reference pulses RP _R , RP _G , and RP _B. The pulse voltage corresponding to the detected cathode current is also detected by the comparator 1
In many cases, there is a considerable voltage difference from the comparison reference voltage (V ₁ + ΔV ₁ ) that is supplied to 7.

Here, if the level shift amount of the reference pulses RP _R , RP _G , and RP _B per field is controlled so as to correspond to the minimum bit, the stable state (that is, the up / down counter 31 is incremented every field). It will take a considerable amount of time to reach the state where the count / down count is repeated).

In a normal television receiver, blanking is performed so that the image is not displayed for some time (about several seconds) after the power is turned on, but before the automatic cutoff adjustment operation reaches a stable state. Since abnormal video is displayed when the video blanking is canceled, the video blanking is continued at least until the stable state is reached. That is, since the cathode current does not flow immediately after the power is turned on, the control signal by the D / A output is shifted so that the DC component of the video signal output rises in the level shift circuit and functions to increase the current amount. It

When the CRT warms up after a while and the cathode current can be obtained, the DC components of the reference pulse and the video signal output become low and become stable at a certain point. This is because the normal image display is performed only when the stable state is reached. For this reason, it is very unfavorable that the image does not appear for a long time until the stable state is reached in the automatic cutoff adjustment operation.

Therefore, when the above embodiment is adopted, CR
It is desirable that the up / down counter 31 performs a plurality of counting operations for one field until T reaches the stable state so that the automatic cutoff adjusting operation can quickly reach the stable state.

Therefore, the up / down counting section 18R,
Count clocks R _CK and G supplied to 18G and 18B
The generation unit of _CK and _BCK is configured as shown in FIG. Further, FIG. 12 shows input / output waveforms of the respective parts in FIG. 11
51, 52, 53 are D flip-flops, 5
4, 55 are NAND gates, 56 is a switch circuit,
The pulse signal H is input to the input terminal 57 once in one horizontal cycle.
_BL (for example, a horizontal synchronizing signal or a signal of the same frequency generated from the horizontal synchronizing signal) is input, and a signal FH ₄ having a frequency four times that of the signal H _BL is input to the input terminal 58 (FIG. 12). (See (a) and (b)).

The signal H _BL is supplied to the reset input terminal of the D flip-flop via the inverter 59 (see FIG. 11).
(C)), and the signal FH ₄ is the D flip-flop 51,
It serves as a latch clock for 52 and 53, and is simultaneously input to the NAND gate 54. Further, the Q output of the D flip-flop 51 (FIG. 11 (d)) is the D flip-flop 5
2 and the NAND gate 54, and the Q output of the D flip-flop 52 (FIG. 11E) is input to the D flip-flop 53 and the NAND gate 55. Furthermore D
The xQ output of the flip-flop 53 (FIG. 11 (g)) is input to the NAND gate 55.

Therefore, from the NAND gate 54, FIG.
As shown in FIG. 11H, a clock having three pulses in one horizontal period is output, while the NAND gate 55 outputs the clock shown in FIG.
As in (i), a clock having one pulse in one horizontal period is output. The outputs of the NAND gates 54 and 55 are selected by the switch circuit 56, and the timing processing corresponding to the reference pulse of each channel is further performed, so that the up / down count units 18R, 18G, 1
It is supplied to 8B as a count clock (R _CK , G _CK , B _CK ).

Therefore, in each channel, when the output of the NAND gate 55 is selected with respect to the comparison output of the comparator 17 as shown in FIG. 13A input to the up / down count units (18R, 18G, 18B). 13B, when the count clock as shown in FIG. 13B is supplied to perform the count operation once per field and the output of the NAND gate 54 is selected,
The count clock as shown in (c) is supplied and the count operation is executed three times per field. That is,
At the time when the CRT has not reached a stable state,
By using the count clock of 3 (c), it is possible to speed up the time until the stable state of the automatic cutoff adjustment operation is reached.

In FIGS. 14A to 14C, the up / down counter 31 counts three times in one field during the unstable period immediately after the power is turned on, and once every one field after reaching the stable period. The reference pulse, the count clock, and the outputs of the D / A converters (19R, 19G, and 19B) when the counting operation is performed are shown for only one channel. By controlling the count clock in this way, quick stabilization is realized, and the video blanking time immediately after power-on can be shortened. Although the count pulse is obtained three times during the horizontal period when unstable, the count pulse may be generated second time or four times or more.

By the way, in this case, in order to obtain the switching timing of the switch circuit 56, means for identifying whether or not the operation of the CRT has reached a stable state is required. For this reason,
In FIG. 11, the counter unit 60 counts a predetermined number of vertical blanking pulses supplied to the input terminal 61 after the power is turned on, and outputs count-up information to the AND gate 62. Further, detection units 63R, 63G, 63B for detecting the presence / absence of the cathode currents (R _IK , G _IK , B _IK ) are provided, and the information that the cathode currents have been detected for all the R, G, B channels is provided. It is output via the gate 64.

The detection of the cathode current is carried out, for example, with reference to FIGS.
Up-down counting section (18R, 18G, 1
8B), the count value of the up / down counter 31 is reset from "0" at a predetermined time immediately after the power is turned on, and the count operation is performed by supplying the pulse voltage by the cathode current based on the reference pulse. It can be detected by counting up.

The AND gate 62 outputs at least a predetermined time after the power is turned on and the information indicating the state in which the cathode current is detected is output, and the output starts the counting of the counter 65. And the counter 65
When the CRT counts a predetermined time (for example, 0.8 to 1 second), it is determined that the CRT has entered a stable operation, and the count-up signal switches the switch circuit 56 originally connected to the NAND gate 54 side to the NAND gate 55 side. ..

In this case, the identification of stabilization of the CRT operation is
Detection of cathode current (that is, the CRT has warmed up)
Therefore, the CRT is already warmed up, for example, when the power is turned off and then immediately turned on. (When the cathode current detection signal is obtained relatively early), eliminate unnecessary waiting time
It is possible to quickly determine that T has reached the stable state.
On the contrary, even when the temperature is low and the CRT does not warm easily, a sufficient waiting time can be obtained by including the detection of the cathode current as a condition.

The present invention is not limited to the above-described embodiments, but various modifications can be made within the scope of the invention.

[0072]

As described above, the video display device of the present invention adds a reference pulse to a predetermined location for each field of a video signal, converts a cathode current obtained by this reference pulse into a pulse voltage, and outputs the pulse voltage. When the control information of the cut-off characteristic of the CRT is obtained by the output of the comparing means for comparing the voltage with the predetermined reference voltage, the output of the comparing means is counted by the up / down counting means and then D / A converted, and this D / A is obtained. Since the cutoff characteristic is controlled by having the level shift means for controlling the DC component of the video signal by the converted output voltage, the automatic cutoff adjustment loop can be configured in the IC and the sample hold as an external component. The capacitor can be eliminated. As a result, it is possible to reduce the number of parts and the number of connection pins required for the IC.
There is an effect that efficiency is realized in terms of cost and manufacturing process. Further, there is an advantage that the automatic cutoff adjustment operation does not become unstable due to the influence of the change over time.

Further, the up / down counting means controls the count clock so that the counting operation is performed a plurality of times in one field during a predetermined period, for example, an unstable period immediately after the power is turned on, so that the cutoff adjustment loop is quickly converged. This has the effect of being realized, and this also has the advantage of shortening the video blanking time immediately after the power is turned on.

The determination of the stable operation of the CRT is most appropriate according to the condition of the CRT and the ambient temperature because the determination is made in two steps, that is, the detection of the cathode current and the waiting time after the detection. There is also an effect that it is possible to make a distinction.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a video display device of the present invention.

FIG. 2 is an explanatory diagram of a count operation based on a reference pulse according to the embodiment.

FIG. 3 is a configuration diagram of an up / down count unit and a D / A converter according to an embodiment.

FIG. 4 is a circuit diagram for explaining a comparison reference hysteresis voltage generation unit of the embodiment.

FIG. 5 is a waveform diagram for explaining a comparison reference hysteresis voltage of the example.

FIG. 6 is a waveform diagram for explaining a correction operation for the output of the D / A converter of the embodiment.

FIG. 7 is an explanatory diagram of an output of the D / A converter of the embodiment.

FIG. 8 is an explanatory diagram of bit precision of a control signal for color temperature adjustment according to the embodiment.

FIG. 9 is a circuit diagram of a level shift circuit according to an embodiment.

FIG. 10 is an explanatory diagram of an adjusting operation by the color temperature adjusting voltage according to the embodiment.

FIG. 11 is a block diagram of a count clock generation unit according to the embodiment.

FIG. 12 is a waveform diagram for explaining the count clock generation operation of the embodiment.

FIG. 13 is an explanatory diagram of the count operation by the count clock of the embodiment.

FIG. 14 is an explanatory diagram of a D / A converter output based on a count clock according to the embodiment.

FIG. 15 is an explanatory diagram of cutoff characteristics of R, G, and B channels.

FIG. 16 is a block diagram of an automatic cutoff adjustment unit of a conventional image display device.

FIG. 17 is an explanatory diagram of a reference pulse.

FIG. 18 is an explanatory diagram of a pulse voltage obtained by a cathode current based on a reference pulse.

[Explanation of symbols]

 10 IC 11R, 11G, 11B switch circuit 12R, 12G, 12B level shift circuit 13R, 13G, 13B drive circuit 14 CRT 17 comparator 18R, 18G, 18B up / down count unit 19R, 19G, 19B D / A converter 20R, 20G , 20B Hysteresis voltage generator 22 Switch circuit 30 D flip-flop 31 Up-down counter 51, 52, 53 D flip-flop 60, 62 Counter 62R, 62G, 62B Detector

Claims (2)

[Claims] 1. A reference pulse is added to a predetermined location for each field of a video signal, and a cathode current obtained by the reference pulse is converted into a pulse voltage,
In a video display device adapted to obtain control information of a CRT cutoff characteristic by the output of a comparing means for comparing the pulse voltage with a predetermined reference voltage, an up / down counting means for counting the output of the comparing means, Control of cut-off characteristics by having D / A conversion means for converting the output of the up / down count means into an analog signal and level shift means for controlling the DC component of the video signal by the output voltage of the D / A conversion means And the up-down count means performs a count operation for the output of the comparison means based on the count pulse supplied in a plurality of units during one field during the set predetermined period. And a video display device. 2. The output of the comparison means to the up / down count means based on a count pulse supplied in a plurality of units during one field from the power-on state to the time when the video display operation in the CRT becomes stable. And the stable point of the video display operation on the CRT is R,
2. The image display device according to claim 1, wherein the cathode currents of all G and B are detected and the counting operation is started from the time when the cathode currents are detected up to a predetermined count value.