JPH05232900A - Driving method for plasma display panel - Google Patents

Abstract

PURPOSE:To maintain the normal operation of a logic circuit by setting the phase of the clock pulse of the same period as a holding pulse to be used in a driving circuit at the phase different from the holding pulse. CONSTITUTION:The phase of the clock pulse 1b of the same period as the period of the holding pulse 1a to be used in the driving circuit of the driving method for the dot matrix display type AC plasma display panel having a memory function is set at the phase different from the holding pulse 1a. The generation timing of a noise and the timing of the clock pulse 1b are shifted in such a manner, by which the change of the voltage of the clock pulse 1b, the intrusion of the noise in the region sensitive to the noise and the consequent indication of abnormality in the equiv. input of the circuit using the clock pulse 1b are eliminated. As a result, the voltage waveform driving the plasma display does not exhibit the abnormality any more and the driving in the normal state is assured. In addition, the malfunction by the intrusion of the noise is eliminated in other circuits using the clock pulse 1b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel used in personal computers, office workstations, or wall-mounted televisions, which are expected to develop in the future.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional dot matrix display type AC plasma display panel having a memory function. FIG. 4A is a plan view,
FIG. 4B is a sectional view taken along the line AA ′ of FIG.

This display panel includes a first insulating substrate 1, a second insulating substrate 2, a row electrode 3, a column electrode 4, an insulating layer 5, and so on.
6, a protective layer 7, a phosphor 8 and a partition wall 9.
In addition, 10 is a discharge space and 11 is a pixel.

FIG. 5 is a plan view showing the electrode arrangement of the plasma display panel shown in FIG. In FIG. 5, the row electrode 3 shown in FIG. 4 is divided into two groups, that is, scan electrodes S ₁ to S _m and common row electrodes C ₁ to C _{m + 1} . Note that reference numeral 12 denotes a seal portion that hermetically adheres the first insulating substrate 1 and the second insulating substrate 2. D ₁
D _n are column electrodes.

FIG. 2 is a voltage waveform diagram according to a conventional driving method of the plasma display panel shown in FIGS.
In FIG. 2, the waveform (2a) is the common row electrodes C _{1 to} C _{m + 1.}
The voltage waveform applied to the scanning electrode S ₁ is the waveform (2b).
The voltage waveform applied to the scanning electrode S ₂ is the waveform (2c).
The voltage waveform applied to the scanning electrode S ₃ is the waveform (2d).
Waveform (2e) shows the voltage waveform applied to the column electrode D ₁ , and waveform (2f) shows the discharge light emission waveform of the pixel at the intersection of the scan electrode S ₁ and the column electrode D _1. ing.

As shown in the waveform (2a), the common row electrode C
A sustain pulse A having a negative polarity is commonly applied to _{1 to} C _{m + 1} . Further, as shown in waveforms (2b), (2c), and (2d), the scan electrodes S _{1 to} S _m are scanned independently of each other in addition to the negative sustain pulse B common to all electrodes. The pulse SP and the erase pulse EP are line-sequentially applied. As shown in the waveform (2e), a positive data pulse is applied to the column electrode according to the light emission data. For example, in order to cause the pixel at the intersection of the scan electrode S ₁ and the column electrode D ₁ to emit light, a positive data pulse is applied to the column electrode D ₁ in synchronization with the scan pulse applied to the scan electrode S ₁ . Then, discharge is generated in this pixel, and light is emitted, for example, as shown by the waveform (2f). The discharge light emission is maintained by continuing to apply the sustain pulses A and B, but when the narrow low voltage erase pulse EP is applied to the scan electrode S ₁ , the discharge light emission is stopped. By such means, the light emission of each pixel can be controlled over the entire screen.

As can be seen from FIG. 2, the scanning pulse SP and the erasing pulse EP need to be sequentially generated. Therefore, the circuit configuration shown in FIG. 6 is used. That is, the scan pulse data and the erase pulse data are transferred to the shift registers 21 and 24 by the clock pulse synchronized with the sustain pulse.
Is shifted to the forward feed by the high voltage pulse circuits 23 and 26 through the latch circuits 22 and 25, and the sustain pulse, scan pulse, and erase pulse are further fed to the high voltage pulse mixing circuit 2.
In FIG. 7, they are mixed and sent to each scanning electrode of the plasma display panel 28.

[0008]

As described above, in the logic circuit in the drive circuit, the clock pulse having the same cycle as the sustain pulse is always used, but the high voltage for maintaining the discharge light emission on the entire screen. Circuits using clock pulses often malfunction due to noise generated from high-current sustain pulses. Taking FIG. 6 as an example, noise from the sustain pulse is mixed in the clock pulse of the scan shift register 21 and the erase shift register 24. This situation is shown in FIG. In FIG. 7, (7a) is the voltage waveform of the sustain pulse of high voltage and large current, (7b) is the voltage waveform of the clock pulse, and (7c) is the equivalent voltage waveform of the clock pulse seen from the circuit using the clock pulse. Is. The harmonic components generated at the rising and falling edges of the high-voltage / large-current sustain pulse (7a) are mixed into the clock pulse (7b), and this noise causes a false clock pulse ( It looks like 7d) has entered. That is, noise is mixed in the most noise-sensitive region where the voltage of the clock pulse changes, and a false clock pulse (7d) is generated. As a result, the voltage waveform as shown in FIG. 2 should be obtained, but the voltage waveform as shown in FIG. In FIG. 8, a waveform (8a) is a voltage waveform applied to the common row electrodes C _{1 to} C _{m + 1} , a waveform (8b) is a voltage waveform applied to the scan electrode S ₁ , and a waveform (8c) is a scan. The waveform of the voltage applied to the electrode S ₂ is shown, and the waveform (8d) shows the waveform of the voltage applied to the scan electrode S ₃ . When FIG. 2 and FIG. 8 are compared, in FIG. 8, since the clock pulse of the scan shift register 21 shown in FIG. 6 has two false clock pulses shown in FIG. 7 per period, it is shown in (8c). It can be seen that the scanning pulse has been excessively shifted by two cycles. The same applies to the erase pulse. As described above, the conventional circuit has a problem that the circuit using the clock pulse malfunctions due to the noise mixed from the sustain pulse.

An object of the present invention is to provide a method for driving a plasma display panel, which is configured so that noise from a sustain pulse mixed in a clock pulse does not affect a circuit using the clock pulse, and thus no circuit malfunction occurs. To provide.

[0010]

According to the present invention, in a method of driving a dot matrix display type AC plasma display panel having a memory function, the phase of a clock pulse used in a driving circuit and having the same period as a sustain pulse is A method of driving a plasma display panel is obtained which has a phase different from that of a sustain pulse.

[0011]

The present invention, by using the above means,
The problems of the prior art were solved. Hereinafter, detailed description will be given with reference to examples.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the relationship between clock pulses and sustain pulses according to the present invention. In FIG. 1, (1a) shows a sustain pulse, (1b) shows a clock pulse, and (1c) shows an equivalent clock pulse waveform seen from a circuit using the clock pulse. What is essential here is that the phase of the clock pulse (1b), which has the same cycle as the sustain pulse (1a), is different from the phase of the sustain pulse (1a). As a result, by shifting the timing of generating the noise and the timing of the clock pulse, as shown in FIG. 7, the noise is mixed in the most noise-sensitive area where the voltage of the clock pulse changes. The equivalent input of the circuit using the clock pulse no longer shows the abnormality as shown in FIG. As a result, the voltage waveform for driving the plasma display does not show an abnormality as shown in FIG. 8, and the plasma display can be driven in a normal state as shown in FIG. Also, in other circuits using the clock pulse, the malfunction due to the noise mixing from the sustain pulse is eliminated. To make the phases of the sustain pulse and the clock pulse different, the phase of the sustain pulse may be changed, or the phase of the clock pulse may be changed. In short, it is sufficient to make a relative phase shift and adjust the mutual phase so that noise from the sustain pulse is not mixed in the change region of the clock pulse that is most sensitive to noise. Also, to remove noise,
If an integrating circuit having a CR time constant as shown in FIG. 9 is used on the input side of the circuit using the clock pulse and the present invention is combined with the integrating circuit, a further effect can be obtained.

The case where the driving method of the present invention is applied to the plasma display panel shown in FIGS. 4 to 5 has been described above. However, the present invention is not limited to such a type of panel, and may be applied to, for example, a so-called counter electrode type panel shown in FIG. 3 or a driving circuit of a DC type plasma display panel using high voltage and large current. Applicable.

[0014]

As described above, by using the driving method of the present invention, the sensitivity to noise mixed in the clock pulse in the logic circuit can be lowered. Therefore, the operation of the logic circuit can be maintained normally, which is very useful industrially.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an example of the present invention.

FIG. 2 is a normal drive voltage waveform diagram in the embodiment of the present invention.

FIG. 3 is a plan view showing an electrode arrangement of a facing plasma display panel to which the present invention can be applied.

FIG. 4 is a configuration diagram of an example of a plasma display panel.

FIG. 5 is an electrode layout diagram of a plasma display panel.

FIG. 6 is a configuration diagram of a circuit that drives the scanning side of the plasma display panel.

FIG. 7 is a diagram illustrating a situation where noise is mixed in a clock pulse by a conventional driving method of a plasma display panel.

FIG. 8 is a drive voltage waveform diagram of the plasma display panel malfunctioning as a result of noise mixing in the conventional circuit configuration.

FIG. 9 is a diagram in which an integrating circuit is connected to an input side of a circuit using a clock pulse.

[Explanation of symbols]

 1 First Insulating Substrate 2 Second Insulating Substrate 3 Row Electrode 4 Column Electrode 5,6 Insulating Layer 7 Protective Layer 8 Phosphor 9 Partition Wall 10 Discharge Space 11 Pixel 12 Sealing Part

Claims (1)

[Claims] 1. A method of driving a dot matrix display type AC plasma display panel having a memory function, wherein a phase of a clock pulse used in a drive circuit and having the same period as a sustain pulse is different from that of the sustain pulse. Driving method for plasma display panel.