JPH05225042A - Address conversion control circuit - Google Patents

Abstract

PURPOSE:To efficiently perform address conversion with respect to an address conversion circuit for plural address spaces provided in a main processor. CONSTITUTION:In the device provided with an address holding register where one address space IO bus 1 out of two address space IO busses 1 and 2 accessed by the main processor is held and an address comparing circuit which compares the address of this address holding register and the address of the main processor with each other are provided, and a circuit which executes the access to one address space IO bus 1 at the time of obtaining a coincidence output 4 from the address comparing circuit but executes the access to the other address space IO bus 2 at the time of obtaining a noncoincidence output 5, the address holding register where one address space is held is provided with a comparison indication bit, and only a bit indicated by this comparison indication bit is selectively compared to convert the address accessed by the main processor.

Description

Detailed Description of the Invention

[0001]

[Industrial field of use] In recent information processing devices,
From 16 bits to 32 bits, or more multi-bits are progressing, the range of access from the main processor is expanding, and not only general memory space but also input / output device and access address unique to main processor There are spaces and so on.

Addresses accessed by the main processor are usually assigned to circuits, elements, etc., which are directly accessed by the main processor in individual devices such as storage devices and input / output devices.

Therefore, when the system is constructed, the address space seen from the main processor is determined.
In particular, when controlling diversified I / O devices of high speed / low speed, a control circuit (attachment) for controlling high-speed I / O devices is mounted on, for example, a processor board,
A control circuit (attachment) for controlling a low speed input / output device is connected to a normal input / output bus to efficiently control a high speed input / output device.

FIG. 4 is a diagram showing an example of the configuration of a data processing apparatus, in which A1 and A2 indicate the above attachments. As is clear from this figure, when viewed from the main processor 1, the address space of the main memory and the input / output bus {I1 to which the attachment (A1) in the processor board is connected
Address space of O bus (1)} and normal attachment
It seems that there is an address space for the I / O bus {IO bus (2)} to which (A2) is connected.

In such a case, looking at the input / output bus from the main processor 1, a high-speed input / output bus {IO bus (1)
} And the low-speed input / output bus {IO bus (2)} exist, the address from the main processor that accesses the input / output device is set to the above two input / output buses {IO bus (1 ), (2)}, an efficient address conversion control circuit for switching is required.

[0006]

2. Description of the Related Art FIGS. 5 to 7 are views showing a conventional address translation control circuit. First, in FIG. 5, the processor address bus signal output from the main processor 1
Further, according to the space access instruction, the address determination unit 2 identifies the type of space for the address output from the main processor 1.

When the space access instruction A is "ON", it is used as an access instruction for the entire space of the memory bus, IO bus (1), IO bus (2), the address of the processor address bus signal is determined, and the memory is Determine whether it is a bus or an IO bus.

When the space access instruction B is "on", the access instruction is for the IO bus space only. When the space access instruction A is "ON" and the address is the memory bus space, the enable signal A is sent to the memory bus address driver 5, and the processor address is sent to the memory bus.

When the space access instruction A is "on",
When the address is the IO bus space and when the space access instruction B is "on", the compare result output instruction is output to the address comparison circuit (COMP) 4.

The address comparison circuit (COMP) 4, which has received the compare result output instruction, compares the address previously held in the address holding register 3 with the address sent from the processor address bus, and the addresses match. When (match signal is output), enable is output to IO bus address driver 6, and when mismatch (when mismatch signal is output), enable to IO bus address driver 7 Is output.

In the address comparison circuit (COMP) 4,
As shown in FIG. 6, since the logical product is formed for a specific bit, for example, in the case where the logical product of only the upper 8 bits is taken in the address space consisting of 16 bits, , A match output is output to the 256 address spaces, and a non-match output is output to the other address spaces.

Main processor 1 and address determination unit 2
Controls access to each input / output bus {IO bus (1), (2)} corresponding to the output address enable. In the above example, the processor address bus signal is output to the address space of the two IO buses (1) and (2), but when there are a plurality of IO buses, As shown in FIG. 7, a plurality of the address holding register 3 and the address comparison circuit 4 described in FIG. 5 are provided, and a mismatch address (a mismatch signal is output in the first address comparison circuit (COMP1) 40. Address)), the second address comparison circuit (COMP2) 41 and the second address holding register 31 repeatedly perform the same comparison processing to obtain a plurality of IO buses (1), (2 ), To address translation, and it is obvious that a plurality of address spaces can be accessed by configuring in this way.

[0013]

In the conventional address translation control circuit as described above, the address holding register is used.
The content of 3 is fixed, and the comparison between the processor address and the holding address is always the same, so in advance,
Only in the address space of the defined range, IO bus (1),
Access to (2) was not possible.

Of course, by changing the contents of the address holding register 3 from the main processor 1, the coincident address in the address comparison circuit (COMP) 4 changes, so that the IO bus (1), Range of access to (2),
That is, although the address space can be changed, the comparison logic in the address comparison circuit 4 is fixed, so that the IO
When the address space for the buses (1) and (2) is changed significantly, for example, when it is desired to expand one address space and reduce the other, the address comparison circuit 4 must be recreated.

In view of the above-mentioned conventional drawbacks, the present invention provides a plurality of address spaces provided in the main processor, for example, the IO buses (1) and (2) with various hardware addresses with a small amount of hardware. It is an object of the present invention to provide an address conversion control circuit which can give a space address and flexibly cope with a change in system configuration.

[0016]

1 and 2 are views showing an embodiment of the present invention. The above problems are solved by the address translation control circuit configured as follows.

(1) A plurality of address holding registers for holding addresses of specific address spaces (A1, A2, ...) for a plurality of address spaces (A1, A2, ...) accessed by the main processor 1 , 31, and the addresses from the main processor 1 are stored in the plurality of first, second, ... Address holding registers 30,31 ,.
The address comparison circuits (COMP1,2,-) 40, 41, ... of, compare with each other, and in the comparison between the first address holding register 30 and the first address comparison circuit 40, a coincident output is obtained. In this case, the above-mentioned specific address space (A1) is accessed, and when a mismatch output is obtained, the second address holding register 31 and the second address comparison circuit (CO
MP2) 41, if a match output is obtained, access to the above specific address space (A2) is performed, and if a mismatch output is obtained, the address is stored in the next address holding register. , The next address comparison circuit is repeated to calculate the processor address into a plurality of address spaces (A1,
A2, ...) address translation control circuit 2, 30, 40, 31,
41, ..., In each of the plurality of address holding registers 30, 31 ,.
30a, 31a, ..., Comparing bit indicating means 30a, 31a
Bits designated by a, ... Are selectively compared to control the comparison operation of the plurality of address comparison circuits 40, 41 ,.

(2) In the above address translation control circuit,
The comparison bit designating means 30a, 31a, ... Are constituted as registers independent of the address holding registers 30, 31 ,.

[0019]

In the present invention, in order to convert addresses for a plurality of address spaces provided in the main processor, the main processor accesses, for example, two address spaces {IO buses (1), (2)}. An address holding register that holds one address space {IO bus (1)} of
The address of the address holding register is compared with the address from the main processor, and when they match, access to the one address space {IO bus (1)} is executed,
If they do not match, another address space {IO bus (2)}
In a device including an address comparison circuit for accessing a memory, a comparison instruction bit is provided in an address holding register that holds the one address space, and only the bit indicated by the comparison instruction bit is selectively compared. Then, the address from the main processor is converted.

Therefore, since the address space for each IO bus (1), (2) is variable within the range indicated by the comparison instruction bit, a relatively small amount of hardware can be used.
This has the effect of being able to flexibly deal with changes in the system configuration and the like.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 and 2 described above are diagrams showing an embodiment of the present invention, and FIG. 3 is a diagram showing another embodiment of the present invention.

In the present invention, the main processor 1 accesses an address conversion control circuit for converting addresses for a plurality of address spaces provided in the main processor 1, for example, two address spaces {IO bus (1) , (2)
}, An address holding register 3 holding one address space {IO bus (1)}, and the address holding register 3
Address comparison circuit 4 for comparing the address held in the memory with the address from the main processor, and when a match output is obtained in the address comparison circuit 4, the one address space {IO bus (1)} To access another address space {IO bus (2)} when a mismatch output is obtained.
In the device including, the address holding register 3 holding the one address space is provided with a comparison instruction bit 3a, and only the bit indicated by the comparison instruction bit 3a is selectively compared, The means for translating the address of is the means necessary to implement the invention.
The same reference numerals denote the same objects throughout the drawings.

1 to 3 with reference to FIGS.
The configuration and operation of the address translation control circuit of the present invention will be described with reference to FIG. First, in FIG. 1, the main processor 1
The signal of the processor address bus and the space access instruction that are output from the
Access control to the memory bus is also the same.

When the space access instruction A is the IO space or the space access instruction B is turned "ON", the address comparison in the address comparison circuit (COMP) 4 is held by the address holding register 3. Address holding register 3 and the processor address.
When the comparison result is compared by the comparison instruction bit 3a in the above, and the comparison result is the same, as in the conventional example, the IO bus (1)
The enable is sent to the address driver 6, and if they do not match, the enable is sent to the IO bus (2) address driver 7.

The address comparison operation in the address comparison circuit (COMP) 4 to which the present invention is applied will be described with reference to FIG. Comparison address, as shown in FIG. 2, 2 ^{15-2 8} (i.e. the processor address, 2 ^{7-2 0} when the one block 256 word represented by bit, 256 block, the address to be compared and the number of space), the comparison instruction bits 3a, for example, be composed of two bits, the value of the comparison instruction bit 3a is the case of "01 (= B)", the comparison of two ^{15-2 9} bits Target {In this case, one of 128 blocks becomes the matching address and is assigned to IO bus (1)}
If the value of the comparison instruction bit 3a is "10 (= C)", only 2 ¹⁵ bits are to be compared {in this case, 2 ¹⁵
Since a coincidence output is output when bit = 0 or 1, 128 blocks are assigned to IO buses (1) and (2)}, and the value of the comparison instruction bit 3a is "00".
In the case of (= A) ", regardless of the comparison result, it is an instruction to access only the IO bus (2), that is, an instruction to always output a mismatch output, and the value of the comparison instruction bit 3a is" 11 ".
In the case of (= D) ", regardless of the comparison result, the instruction is to make only the IO bus (1) the access target, that is, the instruction to always output the coincidence output.

Specifically, the comparison instruction bit 3a is "0".
"If the decoder (DEC) 9 B-output is" 1 1 ", the 2 ^{15-2 8} of the bits, 2 ⁸ bits, the decoder
The B output signal (DEC) 9, always will output a coincidence signal, is compared with the remaining 2 ^{15-2 9} bits is performed.

Similarly, the comparison instruction bit 3a is set to "1".
"If the decoder (DEC) 9 C output is" 0 1 ", and the comparison of the above 2 ^{15-2 9} bits, always will output a coincidence signal, the row comparison only two ^15-bit Be seen.

Similarly, the comparison instruction bit 3a is "0".
In the case of "0", the A output of the decoder (DEC) 9 becomes "1", the comparison result of all bits is always "off", and the mismatch signal is output.

Similarly, the comparison instruction bit 3a is set to "1".
In the case of 1 ", the D output of the decoder (DEC) 9 becomes" 1 ", the comparison result of all bits is always" on ", and the coincidence signal is output.

Therefore, in the above-mentioned embodiment, by setting the comparison instruction bit consisting of, for example, 2 bits of the address holding register 3 to a predetermined value, without changing the hardware, the IO bus ( For 1) and (2),
4 types of address space above {Decoder (DEC) output = A to D
Can be accessed.

When the number of comparison instruction bits is 3 bits, a total of 8 types of address spaces can be allocated to the IO buses (1) and (2), and a finer address space is allocated. be able to.

FIG. 3 shows another embodiment of the present invention, in which I
When there are multiple O-buses, the processor address is
Distribute (convert) to any of the plurality of IO buses
An example of an address conversion control circuit in the case is shown.

Basically, it is the same as the conventional example shown in FIG. 7, and each of the address holding registers 30, 31, ...
The difference is that the comparison instruction bits 30a, 31a, ... are provided. Therefore, the same comparison processing is performed by the second address comparison circuit (COMP2) 41 and the address holding register 31 with respect to the mismatch address {mismatch output} in the first address comparison circuit (COMP1) 40. Repeat for multiple I
Address conversion is performed for the O buses (1), (2) ,.

As shown by the dotted line in FIG. 2, the non-coincidence output is input to a gate circuit for generating an IO bus address driver enable signal to activate the second address comparison circuit (COMP2). You can

At this time, each address comparison circuit 4
0,41, ..., Corresponding comparison instruction bits 30a, 31a,
By performing a selective comparison of only the bits pointed to by,
Flexible address translation can be performed for various system configurations for a plurality of IO buses (1), (2) ,.

The comparison instruction bits 3a, 30a, 31a, ... Described in the above embodiment have been described in the example provided in the address comparison registers 3,30,31.
Needless to say, the configuration may be independent of 31.

As described above, according to the present invention, the main processor accesses, for example, two address spaces {IO bus.
(1), (2)} address holding register holding one address space {IO bus (1)} and the address set in the address holding register and the address from the main processor are compared, A device provided with a circuit for executing access to the one address space {IO bus (1)} in the case of a match, and accessing another address space {IO bus (2)} in the case of a mismatch In the above, in the address holding register which holds the one address space, a comparison instruction bit is provided, and only the bit indicated by the comparison instruction bit is selectively compared to convert the address from the main processor. However, there is a feature.

[0038]

As described above in detail, the address translation control circuit of the present invention can access, for example, two address spaces {IO buses (1), (2)} by the main processor.
Address holding register that holds one address space {IO bus (1)} of the above and the address set in the address holding register and the address from the main processor are compared. Address space {IO
Bus (1)} is accessed, and if they do not match,
In a device provided with a circuit for executing access to another address space {IO bus (2)}, a comparison instruction bit is provided in an address holding register holding the one address space, or the address holding register Since a register for comparison instruction independent of and is provided, and only the bit indicated by the comparison instruction bit is selectively compared, the address from the main processor is converted.
A predetermined address comparison can be performed only by changing the comparison instruction bit, and a processor address can be converted into an address space corresponding to various system configurations with a relatively small amount of hardware. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 2 is a diagram showing an embodiment of the present invention (part 2).

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a diagram showing a configuration example of a data processing device.

FIG. 5 is a diagram showing a conventional address translation control circuit (No. 1).

FIG. 6 is a diagram showing a conventional address translation control circuit (part 2).

FIG. 7 is a diagram showing a conventional address translation control circuit (part 3).

[Explanation of symbols]

1 Main processor 2 Address judgment unit 3,30,31, ~ Address holding register 3a, 30a, 31a, ~ Comparison instruction bit 4,40,41 Address comparison circuit (COMP, COMP1, COMP2, ~) 5 Decoder (DEC) processor Address bus signal Space access instruction A, B signal Compare result output instruction signal Match signal, Match output mismatch signal, or Mismatch output A, B, C, D Decoder (DEC) output signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasutoshi Sakurai 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Koichi Odawara, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takumi Nonaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, within Fujitsu Limited (72) Inventor Kenji Hoshi, 1015 Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Within Fujitsu Limited (72) Inventor, Eiji Kanaya Kanagawa Prefecture 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited

Claims (2)

[Claims] 1. A plurality of address holdings for holding an address of a specific address space (A1, A2, ...) for a plurality of address spaces (A1, A2, ...) accessed by a main processor (1). Registers (30, 31, ...) and addresses from the main processor (1) are transferred to a plurality of first, second, ... address holding registers (30, 31, ...) corresponding to the plurality of first The first and second address comparison circuits (COMP1,2, ...) (40,41, ...) are compared to obtain the first address holding register (30) and the first address comparison circuit (40). When a match output () is obtained in the comparison with, the access to the specific address space (A1) is performed, and when a mismatch output () is obtained,
Address conversion for converting the main processor address into a plurality of address spaces (A1, A2, ...) by repeating comparison between the second address holding register (31) and the second address comparison circuit (41) In a device provided with a control circuit (2, 30, 40, 31, 41, ...), in each of the plurality of address holding registers (30, 31, ...), comparison bit instruction means (30a, 31a, ...) Is provided, and the bits designated by the comparison bit designating means (30a, 31a, ...) are selectively compared, and the plurality of address comparison circuits (40,
41, ...) The address conversion control circuit characterized by controlling the comparison operation. 2. The address conversion control circuit, wherein the comparison bit designating means (30a, 31a, ...) Is constituted as a register independent of the address holding registers (30, 31 ,. The address translation control circuit according to claim 1.