JPH05218431A - Field effect transistor - Google Patents

Field effect transistor

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Publication number
JPH05218431A
JPH05218431A JP4601592A JP4601592A JPH05218431A JP H05218431 A JPH05218431 A JP H05218431A JP 4601592 A JP4601592 A JP 4601592A JP 4601592 A JP4601592 A JP 4601592A JP H05218431 A JPH05218431 A JP H05218431A
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JP
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Patent type
Prior art keywords
region
effect transistor
field effect
drain region
channel region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4601592A
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Japanese (ja)
Inventor
Masanori Funaki
正紀 舟木
Original Assignee
Victor Co Of Japan Ltd
日本ビクター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Abstract

PURPOSE: To provide the title field effect transistor having high reliability without breaking down a gate oxide film.
CONSTITUTION: Within the title field effect transistor, a source region 2 and a drain region 3 implanted with impurities are formed on an insulating layer 1; a channel region 4 containing almost no impurities at all is formed between these regions 2 and 3; and then a gate region 6 is provided on the channel region 4 through the intermediary of a gate insulating film 5 comprising SiO2, etc. In such a constitution, the thickness of the source region 2 and the drain region 3 is to be thinner than that of the channel region 4 so that the surface of the source region 2 and the drain region 3 may be located on a position lower than that of the channel region 4.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はSOIMOSFET(Si BACKGROUND OF THE INVENTION This invention is SOIMOSFET (Si
licon On Insulator Metal Oxide Semiconductor Field licon On Insulator Metal Oxide Semiconductor Field
Effect Transistor)に関する。 Effect Transistor) on.

【0002】 [0002]

【従来の技術】ラッチアップフリー、ソフトエラー耐性、低浮遊容量、集積回路の三次元化の可能性等において、バルクSi素子にない利点を有するSOIMOSF BACKGROUND OF THE INVENTION latch-up free, soft error resistance, low stray capacitance, the potential or the like of the three-dimensional integrated circuits, SOIMOSF having advantages over bulk Si device
ETが注目されている。 ET has been attracting attention. このSOIMOSFETは図8 This SOIMOSFET Figure 8
に示すように、SiO 2等の絶縁体10の上にシリコン層11を形成し、このシリコン層11の一部に不純物を注入してソース領域12及びドレイン領域13を形成するとともに、これらソース領域12とドレイン領域13との間をチャネル領域14とし、このチャネル領域14の上に酸化膜15を介してゲート領域16を形成した構造になっている。 As shown in the silicon layer 11 is formed on an insulator 10 such as SiO 2, to form a source region 12 and drain region 13 by implanting an impurity into a portion of the silicon layer 11, source region between 12 and drain region 13 and channel region 14, and is formed with a structure in which a gate region 16 through the oxide film 15 on the channel region 14.

【0003】そして、上記のSOIMOSFETは通常のMOSFETと異なり、チャネル領域14領域の不純物を殆どゼロにすることができるので、不純物の散乱を抑えられ、高速のデバイスを作ることができる。 [0003] The above SOIMOSFET Unlike conventional MOSFET, it is possible to almost zero the impurity in the channel region 14 region, is suppressed scattering of impurities, it is possible to make a high-speed devices. 特に薄いSOI膜を形成することにより、キンク効果及びドレイン電流オーバシュート現象を抑制でき、高性能化を達成することができる。 By forming a particularly thin SOI film, it can be suppressed kink effect, and the drain current overshoot phenomenon, it is possible to achieve high performance.

【0004】 [0004]

【発明が解決しようとする課題】ところで、上述のSO The object of the invention is to be Solved by the way, the above-mentioned SO
IMOSFETにあっては、図9に示すようにチャネル領域14を介してソース領域12からドレイン領域13 In the IMOSFET, drain region 13 from source region 12 through the channel region 14 as shown in FIG. 9
に向けて電流が流れる場合、高電界によって高エネルギ状態になったエレクトロン(ホットエレクトロン)がシリコン結晶格子に衝突して電子・ホール対を発生させ、 If the current flows in, to generate electron-hole pairs electrons becomes high energy state by a high electric field (hot electrons) collide with the silicon crystal lattice,
これがゲート酸化膜15に飛込んで膜を破壊したり、界面準位を発生してデバイス特性が狂い信頼性が低下する。 This destroy the film jump into the gate oxide film 15, the device characteristics and generating a interface state deviation reliability is lowered. 特に、上記の不利は薄いSOI膜を形成した場合にドレイン近傍の電界が大きくなるので顕著になる。 In particular, it becomes significant since the electric field near the drain is increased when the above disadvantages by forming a thin SOI film.

【0005】 [0005]

【課題を解決するための手段】上記課題を解決すべく本発明は、絶縁体上にシリコン(Si)層を形成し、このシリコン層に不純物を注入してソース領域及びドレイン領域を形成した電界効果トランジスタにおいて、前記ドレイン領域の厚みをチャネル領域の厚みよりも薄くした。 Means for Solving the Problems The present invention to solve the above problems, the silicon (Si) layer was formed on an insulator, to form a source region and a drain region by implanting an impurity into the silicon layer field in effect transistor, and the thickness of the drain region thinner than the thickness of the channel region.

【0006】 [0006]

【作用】ドレイン領域の厚みがチャネル領域の厚みよりも薄くなっているので、ドレイン領域の上面がゲート酸化膜の下面よりも下に位置し、その結果電流の経路は強電界部分から離れた部分を通ってドレイン領域に入るので、発生するホットエレクトロンを低減することができる。 Since the thickness of the working drain region is thinner than the thickness of the channel region, positioned below the lower surface of the upper surface of the drain region is a gate oxide film, the path of the resulting current away from the strong electric field portion parts since entering the drain region through, it is possible to reduce the generated hot electrons.

【0007】 [0007]

【実施例】以下に本発明の実施例を添付図面に基づいて説明する。 EXAMPLES be described with reference to the embodiment accompanying drawings of the invention are described below. ここで、図1は本発明に係る電界効果トランジスタの断面図、図2は同電界効果トランジスタの要部拡大断面図、図3乃至図7は電界効果トランジスタの製作方法を示す図である。 Here, FIG. 1 is a sectional view of a field effect transistor according to the present invention, FIG. 2 is a fragmentary enlarged sectional view of the field effect transistor, FIGS. 3 to 7 are views showing a manufacturing method of the field effect transistor.

【0008】本発明の電界効果トランジスタはSiO 2等の絶縁層1上にシリコン(Si)に不純物を注入してなるソース領域2とドレイン領域3を形成し、これらソース領域2とドレイン領域3間を不純物が殆ど含まれないチャネル領域4とし、このチャネル領域4上にSiO 2等のゲート酸化膜5を介してゲート領域6を設けた構造になっている。 [0008] field effect transistor of the present invention to form a source region 2 and drain region 3 formed by implanting an impurity into the silicon (Si) on the insulating layer 1, such as SiO 2, between these source and drain regions 2 and 3 the impurities and the channel region 4 contains almost no, it has become the provided structure gate region 6 via a gate oxide film 5 of SiO 2 or the like is formed on the channel region 4.

【0009】そして、前記ソース領域2とドレイン領域3はその厚みがチャネル領域4の厚みよりも薄くされ、 [0009] Then, the source region 2 and drain region 3 is the thickness is thinner than the thickness of the channel region 4,
ソース領域2とドレイン領域3の上面がチャネル領域4 Upper surface of the source region 2 and drain region 3 is the channel region 4
の上面よりも下がった位置にある。 In down position than the upper surface of the.

【0010】以上において、ゲート領域6に電圧を印加してチャネル領域4の抵抗をコントロールしてソース領域2とドレイン領域3間に電流を流すと、図2の矢印に示すように電流はソース領域2からチャネル領域4を通ってドレイン領域3に流れる。 [0010] In the above, when to control the resistance of the channel region 4 by applying a voltage to the gate region 6 a current flows between the source region 2 and drain region 3, the current source region, as shown by an arrow in FIG. 2 It flows to the drain region 3 from 2 through the channel region 4. そして、このときドレイン領域3の上面はチャネル領域4上面よりも下がった位置にあるので、電流は最も高い電界の部分を避けてドレイン領域4に流入する。 Then, the upper surface of this case the drain region 3 is in the position falls below the channel region 4 top, current flows into the drain region 4 to avoid the part of the highest electric field.

【0011】次に、上記の電界効果トランジスタ(SO [0011] Next, the above-mentioned field-effect transistor (SO
IMOSFET)の製作方法を図3乃至図7に基づいて説明する。 It will be described with reference to FIGS. 3 to 7 the method of fabricating IMOSFET). 先ず図3に示すように、SiO 2等の絶縁層1 First, as shown in FIG. 3, the insulating layer 1 of SiO 2 or the like
上にシリコン(Si)層7をエピタキシャル成長法等によって500Å程度の厚さまで形成し、このシリコン層7表面にSiO 2等の酸化膜5aを形成し、更にこの酸化膜5aの表面にゲート領域6となるポリシリコン層6a Silicon (Si) layer 7 is formed to a thickness of about 500Å by epitaxial growth method or the like above, the oxide film 5a of SiO 2 or the like is formed on the silicon layer 7 surface, further a gate region 6 on the surface of the oxide film 5a polysilicon layer 6a made
を形成し、このポリシリコン層6aの表面にレジストマスク8をかけ、レジストマスク8の上からプラズマ等でエッチングを行なう。 Is formed and subjected to resist mask 8 to the surface of the polysilicon layer 6a, is etched by plasma or the like from above the resist mask 8.

【0012】すると、図4に示すように、レジストマスク8の部分を残してポリシリコン層6aが除去されてゲート領域6が形成され、更にエッチングを継続すると、 [0012] Then, as shown in FIG. 4, the gate region 6 polysilicon layer 6a is removed leaving the portions of the resist mask 8 is formed and further continuing the etching,
図5に示すようにレジストマスク8の部分を残して酸化膜5aが除去されてゲート酸化膜5が形成される。 Oxide film 5a to leave portions of the resist mask 8 is removed and the gate oxide film 5 is formed as shown in FIG.

【0013】従来であれば上記の位置でエッチングを停止するのであるが、本発明にあっては更にエッチングを継続して図6に示すようにゲート酸化膜5の下面より更に下までレジストマスク8から露出しているシリコン層7を掘り下げる。 [0013] If conventional but of stopping etching in the above position, the resist mask 8 to further down than the lower surface of the gate oxide film 5 as in the present invention is to further continue the etching shown in FIG. 6 digging into the silicon layer 7 exposed from.

【0014】この後、図7に示すように、レジストマスク8から露出しているシリコン層7にAs等の不純物を注入してソース領域2及びドレイン領域3を形成し、更にアッシングによってレジストマスク8を除去することによって図1に示した電界効果トランジスタを得ることができる。 [0014] The resist mask 8 Thereafter, as shown in FIG. 7, by injecting impurities such as As and forming a source region 2 and drain region 3 in the silicon layer 7 exposed from the resist mask 8, by further ashing it is possible to obtain the field-effect transistor shown in FIG. 1 by removing the.

【0015】尚、実施例にあってはデバイスの対称性を考慮して、ソース領域の厚さもドレイン領域と等しくなるようにしたが、ソース領域については従来と同様にチャネル領域上面と面一となるようにしてもよい。 [0015] In Example in consideration of symmetry of the device, but as the thickness of the source region is also equal to the drain region, the source region and the prior art as well as the channel region top surface flush it may be made.

【0016】 [0016]

【発明の効果】以上に説明したように本発明のSOIM SOIM of the present invention as described above, according to the present invention
OS電界効果トランジスタにによれば、ドレイン領域の厚みをチャネル領域の厚みよりも薄くし、ドレイン領域上面がゲート酸化膜下面よりも下に位置するようにしたので、電流の経路が強電界部分から離れた部分を通ってドレイン領域に入ることとなり、発生するホットエレクトロンを低減することができる。 According to the OS field effect transistor, the thickness of the drain region thinner than the thickness of the channel region, the drain region upper surface is to be positioned below the gate oxide film lower surface, the path is a strong electric field portion of the current becomes to enter the drain region through the distant parts, it is possible to reduce the generated hot electrons. したがって、SOI膜を500Å程度まで薄くしてもゲート酸化膜を破壊することがなく、信頼性の高い電界効果トランジスタを得ることができる。 Therefore, it is possible to break down the gate oxide film be thinned SOI film to about 500 Å, it is possible to obtain a highly reliable field effect transistor.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明に係る電界効果トランジスタの断面図 Sectional view of a field effect transistor according to the present invention; FIG

【図2】同電界効果トランジスタの要部拡大断面図 [Figure 2] enlarged sectional view of the field-effect transistor

【図3】本発明に係る電界効果トランジスタの製作方法を示す図 Shows a fabrication method of the field effect transistor according to the present invention; FIG

【図4】本発明に係る電界効果トランジスタの製作方法を示す図 Shows a fabrication method of a field effect transistor according to the present invention; FIG

【図5】本発明に係る電界効果トランジスタの製作方法を示す図 Shows a fabrication method of the field effect transistor according to the present invention; FIG

【図6】本発明に係る電界効果トランジスタの製作方法を示す図 Shows a fabrication method of the field effect transistor according to the present invention; FIG

【図7】本発明に係る電界効果トランジスタの製作方法を示す図 It shows a fabrication method of the field effect transistor according to [7] The present invention

【図8】従来の電界効果トランジスタの断面図 Figure 8 is a cross-sectional view of a conventional field effect transistor

【図9】従来の電界効果トランジスタの要部拡大断面図 9 enlarged sectional view of a conventional field effect transistor

【符号の説明】 DESCRIPTION OF SYMBOLS

1…絶縁層、2…ソース領域、3…ドレイン領域、4… 1 ... insulating layer, 2 ... source region, 3 ... drain region, 4 ...
チャネル領域、5…ゲート酸化膜、6…ゲート領域、7 The channel region, 5 ... gate oxide film, 6 ... gate region 7
…シリコン層、8…レジストマスク。 ... silicon layer, 8 ... resist mask.

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 絶縁体上にシリコン(Si)層を形成し、このシリコン層に不純物を注入してソース領域及びドレイン領域を形成した電界効果トランジスタにおいて、前記ドレイン領域の厚みをチャネル領域の厚みよりも薄くしたことを特徴とする電界効果トランジスタ。 1. A form a silicon (Si) layer on an insulator, in a field effect transistor forming the source and drain regions by implanting impurities into the silicon layer, the thickness of the channel region the thickness of the drain region field effect transistor, characterized in that thinner than.
JP4601592A 1992-01-31 1992-01-31 Field effect transistor Pending JPH05218431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4601592A JPH05218431A (en) 1992-01-31 1992-01-31 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4601592A JPH05218431A (en) 1992-01-31 1992-01-31 Field effect transistor

Publications (1)

Publication Number Publication Date
JPH05218431A true true JPH05218431A (en) 1993-08-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP4601592A Pending JPH05218431A (en) 1992-01-31 1992-01-31 Field effect transistor

Country Status (1)

Country Link
JP (1) JPH05218431A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6683350B1 (en) 1993-02-05 2004-01-27 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6683350B1 (en) 1993-02-05 2004-01-27 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the same
US7011993B2 (en) 1993-02-05 2006-03-14 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the same
US7394130B2 (en) 1993-02-05 2008-07-01 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the same

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